diff --git a/CHANGELOG.md b/CHANGELOG.md new file mode 100644 index 0000000..d73f1b8 --- /dev/null +++ b/CHANGELOG.md @@ -0,0 +1,7 @@ +# Eleph changelog +**Legend:** _"Hardware version/Software version"_ + + + +#### v1/1.0 - February 14, 2021 +- Initial release \ No newline at end of file diff --git a/Firmware/CubeIDE/.cproject b/Firmware/CubeIDE/.cproject new file mode 100644 index 0000000..a13076e --- /dev/null +++ b/Firmware/CubeIDE/.cproject @@ -0,0 +1,175 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Firmware/CubeIDE/.project b/Firmware/CubeIDE/.project new file mode 100644 index 0000000..fb0c81c --- /dev/null +++ b/Firmware/CubeIDE/.project @@ -0,0 +1,31 @@ + + + Eleph + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUManagedMakefileProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/Firmware/CubeIDE/.settings/language.settings.xml b/Firmware/CubeIDE/.settings/language.settings.xml new file mode 100644 index 0000000..8f7f220 --- /dev/null +++ b/Firmware/CubeIDE/.settings/language.settings.xml @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Firmware/CubeIDE/.settings/org.eclipse.cdt.core.prefs b/Firmware/CubeIDE/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 0000000..4025163 --- /dev/null +++ b/Firmware/CubeIDE/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,6 @@ +doxygen/doxygen_new_line_after_brief=true +doxygen/doxygen_use_brief_tag=false +doxygen/doxygen_use_javadoc_tags=true +doxygen/doxygen_use_pre_tag=false +doxygen/doxygen_use_structural_commands=false +eclipse.preferences.version=1 diff --git a/Firmware/CubeIDE/CMSIS/inc/core_cm3.h b/Firmware/CubeIDE/CMSIS/inc/core_cm3.h new file mode 100644 index 0000000..2b6b51a --- /dev/null +++ b/Firmware/CubeIDE/CMSIS/inc/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h b/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h new file mode 100644 index 0000000..561b84d --- /dev/null +++ b/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h @@ -0,0 +1,8336 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, + * High density, High density value line, Medium density, + * Medium density Value line, Low density, Low density Value line + * and XL-density devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + #define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ + /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. + - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - High-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #ifdef STM32F10X_CL + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_VALUE */ + + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F10x Standard Peripheral Library version number + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F10X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#ifdef STM32F10X_XL + #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ +#else + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#endif /* STM32F10X_XL */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + +#ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + +#ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_HD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ + TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ + TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is + mapped at position 60 only if the MISC_REMAP bit in + the AFIO_MAPR2 register is set) */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_XL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_XL */ + +#ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f10x.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + __IO uint32_t SR; +#endif +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +#ifdef STM32F10X_XL + uint32_t RESERVED1[8]; + __IO uint32_t KEYR2; + uint32_t RESERVED2; + __IO uint32_t SR2; + __IO uint32_t CR2; + __IO uint32_t AR2; +#endif /* STM32F10X_XL */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ + #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ + #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ +#endif /* STM32F10X_XL */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ +#endif /* STM32F10X_XL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ + #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ + #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ +#endif + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + +#ifdef STM32F10X_HD_VL + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ +#endif /* STM32F10X_XL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + +#ifdef STM32F10X_HD_VL +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ +#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ +#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ +#endif + +#ifdef STM32F10X_XL +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ +#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ +#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#endif + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CCR5 register *******************/ +#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CCR6 register *******************/ +#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR7 register *******************/ +#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNDTR1 register ******************/ +#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR2 register ******************/ +#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR3 register ******************/ +#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR4 register ******************/ +#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR5 register ******************/ +#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR6 register ******************/ +#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR7 register ******************/ +#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR1 register *******************/ +#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR2 register *******************/ +#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR3 register *******************/ +#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR4 register *******************/ +#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR5 register *******************/ +#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR6 register *******************/ +#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR7 register *******************/ +#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR1 register *******************/ +#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR2 register *******************/ +#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR3 register *******************/ +#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + + +/****************** Bit definition for DMA_CMAR4 register *******************/ +#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR5 register *******************/ +#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR6 register *******************/ +#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR7 register *******************/ +#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ +#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ +#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ + +#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ + +/******************** Bit definition for DAC_SR register ********************/ +#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ + +/******************************************************************************/ +/* */ +/* CEC */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CEC_CFGR register ******************/ +#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ +#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ +#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ + +/******************** Bit definition for CEC_OAR register ******************/ +#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ +#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ + +/******************** Bit definition for CEC_PRES register ******************/ +#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ + +/******************** Bit definition for CEC_ESR register ******************/ +#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ +#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ +#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ +#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ +#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ +#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ +#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ + +/******************** Bit definition for CEC_CSR register ******************/ +#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ +#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ +#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ +#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ +#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ +#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ +#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ +#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ + +/******************** Bit definition for CEC_TXD register ******************/ +#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ + +/******************** Bit definition for CEC_RXD register ******************/ +#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ +#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ +#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ +#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ +#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ + +#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ + +#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ + +#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ +#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ + +#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ + +#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ +#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ +#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ +#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ +#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ +#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ +#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ +#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ +#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ +#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ +#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ +#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ +#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ +#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ +#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ +#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ +#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ + +#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ +#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ +#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ +#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ +#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ +#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ +#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ +#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ +#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ +#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ + +#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ + +#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ +#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ +#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ +#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ +#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ +#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ +#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ +#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ +#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ +#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ +#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ +#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ +#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ +#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ +#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ +#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ +#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ +#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ +#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ +#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ +#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ +#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ +#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ +#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ +#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ +#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ +#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ +#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ +#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ +#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ +#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ +#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ +#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ +#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ +#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ +#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ +#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ +#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ + +#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ +#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ +#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ +#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ +#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ +#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ +#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ +#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ +#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ +#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ +#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ +#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ +#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ +#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ +#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ +#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ +#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ +#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ +#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ +#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ +#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ +#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ +#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ +#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ +#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ +#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ +#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ +#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ +#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ +#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ +#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ +#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ +#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ +#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ +#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ +#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ + +#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ +#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ +#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ + +#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ +#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ +#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ + +#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ +#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ +#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ +#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ +#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ +#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ +#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ +#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ +#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ +#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ +#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ +#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ +#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ +#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ +#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ +#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ +#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ +#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ +#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ +#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ +#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ +#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ +#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ +#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ +#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ +#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ +#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ +#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ + +#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ +#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ +#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ +#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ +#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ +#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ +#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ +#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ +#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ +#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ +#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ +#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ +#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ +#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ +#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ +#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ +#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ + +#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ +#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ +#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ +#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ +#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ +#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ +#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ +#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ +#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ +#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ +#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +#ifdef STM32F10X_CL +/******************************************************************************/ +/* Ethernet MAC Registers bits definitions */ +/******************************************************************************/ +/* Bit definition for Ethernet MAC Control Register register */ +#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ + #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling + a transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ + +/* Bit definition for Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ + +/* Bit definition for Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ + +/* Bit definition for Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ + +/* Bit definition for Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ + +/* Bit definition for Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ + +/* Bit definition for Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ + +/* Bit definition for Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. + Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ +/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask + Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask + Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask + Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask + Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command + Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset + Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 + Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +/* Bit definition for Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ + +/* Bit definition for Ethernet MAC Status Register */ +#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ + +/* Bit definition for Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ + +/* Bit definition for Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ + +/* Bit definition for Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ + +/* Bit definition for Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ + +/* Bit definition for Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ + +/* Bit definition for Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ + +/* Bit definition for Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* Ethernet MMC Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ + +/* Bit definition for Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ +#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ +#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ + +/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ +#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ +#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ + +/******************************************************************************/ +/* Ethernet PTP Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ + +/* Bit definition for Ethernet PTP Sub-Second Increment Register */ +#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ + +/* Bit definition for Ethernet PTP Time Stamp High Register */ +#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ + +/* Bit definition for Ethernet PTP Time Stamp Low Register */ +#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp High Update Register */ +#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ +#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Addend Register */ +#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ + +/* Bit definition for Ethernet PTP Target Time High Register */ +#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ + +/* Bit definition for Ethernet PTP Target Time Low Register */ +#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ + +/******************************************************************************/ +/* Ethernet DMA Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ + +/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ + +/* Bit definition for Ethernet DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ + +/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ + +/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ + +/* Bit definition for Ethernet DMA Status Register */ +#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ + /* combination with EBS[2:0] for GetFlagStatus function */ + #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ + +/* Bit definition for Ethernet DMA Operation Mode Register */ +#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ + +/* Bit definition for Ethernet DMA Interrupt Enable Register */ +#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ + +/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ + +/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ +#endif /* STM32F10X_CL */ + +/** + * @} + */ + + /** + * @} + */ + +#ifdef USE_STDPERIPH_DRIVER + #include "stm32f10x_conf.h" +#endif + +/** @addtogroup Exported_macro + * @{ + */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_H */ + +/** + * @} + */ + + /** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h b/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h new file mode 100644 index 0000000..739f332 --- /dev/null +++ b/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/CubeIDE/CMSIS/src/core_cm3.c b/Firmware/CubeIDE/CMSIS/src/core_cm3.c new file mode 100644 index 0000000..d202e36 --- /dev/null +++ b/Firmware/CubeIDE/CMSIS/src/core_cm3.c @@ -0,0 +1,784 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/Firmware/CubeIDE/CMSIS/src/system_stm32f10x.c b/Firmware/CubeIDE/CMSIS/src/system_stm32f10x.c new file mode 100644 index 0000000..6fb4579 --- /dev/null +++ b/Firmware/CubeIDE/CMSIS/src/system_stm32f10x.c @@ -0,0 +1,1094 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/CubeIDE/Code/inc/adc.h b/Firmware/CubeIDE/Code/inc/adc.h new file mode 100644 index 0000000..1f9c5c6 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/adc.h @@ -0,0 +1,12 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: adc.h +*/ + +void adc_init(void); +uint8_t adc_get_bat_voltage(void); +float get_bat_voltage(void); diff --git a/Firmware/CubeIDE/Code/inc/buttons.h b/Firmware/CubeIDE/Code/inc/buttons.h new file mode 100644 index 0000000..b70d75c --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/buttons.h @@ -0,0 +1,29 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: buttons.h +*/ + +#define BTN_NO_ACTION (0) + +#define BTN_UP (1) //PA1 +#define BTN_UP_LONG (2) + +#define BTN_DOWN (3) //PA2 +#define BTN_DOWN_LONG (4) + +#define BTN_OK (5) //PA3 +#define BTN_OK_LONG (6) + +#define BTN_PWR (7) //PA4 +#define BTN_PWR_LONG (8) + +#define BTN_ESC (9) //PA5 +#define BTN_ESC_LONG (10) + + + +uint8_t scan_buttons(void); diff --git a/Firmware/CubeIDE/Code/inc/gpio.h b/Firmware/CubeIDE/Code/inc/gpio.h new file mode 100644 index 0000000..3683b2e --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/gpio.h @@ -0,0 +1,36 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: gpio.h +*/ + +void gpio_init(void); +void ext_int_init(void); + +void led_board_on(void); +void led_board_off(void); +void led_red_on(void); +void led_red_off(void); +void led_green_on(void); +void led_green_off(void); + +void sdn_si4463_active(void); +void sdn_si4463_inactive(void); + +void cs_si4463_active(void); +void cs_si4463_inactive(void); + +void res_ssd1306_active(void); +void res_ssd1306_inactive(void); + +void ssd1306_data_mode(void); +void ssd1306_command_mode(void); + +void cs_ssd1306_active(void); +void cs_ssd1306_inactive(void); + +void bat_mon_on(void); +void bat_mon_off(void); diff --git a/Firmware/CubeIDE/Code/inc/gps.h b/Firmware/CubeIDE/Code/inc/gps.h new file mode 100644 index 0000000..ab908ec --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/gps.h @@ -0,0 +1,79 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: gps.h +*/ + +#define GPS_DATA_INVALID (0) +#define GPS_DATA_VALID (1) +#define GPS_POSITION_NOFIX (1) +#define GPS_POSITION_2DFIX (2) +#define GPS_POSITION_3DFIX (3) + + + +//GPS data from GNSS module (raw) +#define CHAR_RESERVE (2) +struct gps_raw_struct +{ + char time[sizeof("hhmmss.ss") + CHAR_RESERVE]; //UTC Time + char date[sizeof("ddmmyy") + CHAR_RESERVE]; //UTC Date + char latitude[sizeof("ddmm.mmmm") + CHAR_RESERVE]; //Shirota + char ns[sizeof("x") + CHAR_RESERVE]; //Northing + char longitude[sizeof("dddmm.mmmm") + CHAR_RESERVE]; //Dolgota + char ew[sizeof("x") + CHAR_RESERVE]; //Easting + char speed[sizeof("xxx.yyy") + CHAR_RESERVE]; //Speed over ground, knots + char course[sizeof("xxx.y") + CHAR_RESERVE]; //Course over ground, deg + char status[sizeof("x") + CHAR_RESERVE]; //A=Valid, V=Invalid + char altitude[sizeof("aaaaa.a") + CHAR_RESERVE]; //Altitude above means sea level, meters probably + char sat_view[sizeof("nn") + CHAR_RESERVE]; //Number of SVs used for navigation + char sat_used[sizeof("nn") + CHAR_RESERVE]; //Number of SVs used for navigation + char mode[sizeof("x") + CHAR_RESERVE]; //0=No, 1=2D, 2=3D + char pdop[sizeof("xx.yy") + CHAR_RESERVE]; //Positional dilution of precision +}; + + + +//Similar to (but not the same as) gps_raw_struct, in numerical format +struct gps_num_struct +{ + uint8_t hour; //UTC Time + uint8_t minute; + uint8_t second; + + uint8_t day; //UTC Date + uint8_t month; + uint8_t year; + + struct { + float in_deg; //Lat in decimal deg + double in_rad; //in radians (converted), scaled to double to improve relative pos calculation accuracy + } latitude; + + struct { + float in_deg; //Lon in decimal deg + double in_rad; //in radians (converted), scaled to double to improve relative pos calculation accuracy + } longitude; + + float speed; //kilometers per hour (converted) + float course; //decimal degrees + float altitude; //meters above means sea level, signed + + uint8_t sat_view; + uint8_t sat_used; + + uint8_t status; //0=Invalid, 1=Valid + uint8_t mode; //1=NoFix, 2=2D, 3=3D + float pdop; +}; + + + +uint8_t parse_gps(void); +char *get_nmea_buf(void); +struct gps_raw_struct *get_gps_raw(void); +struct gps_num_struct *get_gps_num(void); +uint8_t get_gps_status(void); diff --git a/Firmware/CubeIDE/Code/inc/i2c.h b/Firmware/CubeIDE/Code/inc/i2c.h new file mode 100644 index 0000000..04cb83f --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/i2c.h @@ -0,0 +1,10 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: i2c.h +*/ + +void i2c_init(void); diff --git a/Firmware/CubeIDE/Code/inc/lrns.h b/Firmware/CubeIDE/Code/inc/lrns.h new file mode 100644 index 0000000..d361b6c --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/lrns.h @@ -0,0 +1,115 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: lrns.h +*/ + +extern const double deg_to_rad; //deg to rad multiplyer + + + +//DEVICES +#define DEVICES_IN_GROUP (6) //total number of devices in group + + + +#define FLAGS_BATTERY (1) +#define FLAGS_GPS_FIX (2) +#define FLAGS_PDOP (3) +#define FLAGS_ALARM (4) + +#define FLAG_BATTERY_0_TO_10 (0) +#define FLAG_BATTERY_10_TO_25 (1) +#define FLAG_BATTERY_25_TO_50 (2) +#define FLAG_BATTERY_50_TO_75 (3) +#define FLAG_BATTERY_75_TO_100 (4) +#define FLAG_GPS_FIX_2D (0) +#define FLAG_GPS_FIX_3D (1) +#define FLAG_PDOP_BAD (0) +#define FLAG_PDOP_GOOD (1) +#define FLAG_ALARM_OFF (0) +#define FLAG_ALARM_ON (1) + + + +void init_lrns(void); +void set_device_flags(uint8_t parameter_to_set, uint8_t parameter_value); +uint8_t get_device_flags(uint8_t device_number, uint8_t parameter_to_get); + +uint8_t check_alarms(void); +void calc_timeout(uint32_t current_uptime); +uint8_t check_timeout(void); +uint8_t check_fence(void); + +void process_all_devices(void); + +void gps_air_update_my_data(uint32_t uptime); +void fill_air_packet_with_struct_data(void); +uint8_t fill_struct_with_air_packet_data(uint32_t uptime); +void calc_relative_position(uint8_t another_device); + +struct gps_air_struct **get_gps_air(void); +struct gps_rel_struct **get_gps_rel(void); +struct dev_aux_struct **get_dev_aux(void); + + + +//Data to be transferred over-the-air +struct gps_air_struct +{ + char device_id[DEVICE_ID_LEN]; //user id, ASCII symbols + uint8_t flags; //device flags + + union + { + float as_float; //latitude in decimal degrees (-90...+90) + uint8_t as_array[4]; + } latitude; + + union + { + float as_float; //longitude in decimal degrees (-180...+180) + uint8_t as_array[4]; + } longitude; + + union + { + int16_t as_integer; //altitude in meters, signed + uint8_t as_array[2]; + } altitude; + + uint8_t speed; //speed in km/h, unsigned + + union + { + uint16_t as_integer; //course in degrees, unsigned + uint8_t as_array[2]; + } course; +}; + + + +//Data with relative position info +struct gps_rel_struct +{ + uint32_t distance; //distance in meters between this device and another one + uint16_t heading; //heading to another device, degrees + int16_t altitude_diff; //difference in altitudes, in meters, signed +}; + + + +//Auxiliary information about devices +struct dev_aux_struct +{ + uint8_t exist_flag; //is this device exist? (i.e. at least one successful receprion is exist) + uint32_t timestamp; //"uptime" value at the moment of packet reception + uint32_t timeout; //timeout value at the moment of calculation via check_timeout(); equals uptime-timestamp + uint8_t timeout_flag; //flag, indicates that timeout occured + uint8_t fence_flag; //indicates if distance to a device is bigger than predefined fence radius + uint8_t memory_point_flag; //is this device was loaded as a point from memory? + char point_name[MEMORY_POINT_NAME_LENGTH + 1]; //user-defined point name in the slot +}; diff --git a/Firmware/CubeIDE/Code/inc/m24c64.h b/Firmware/CubeIDE/Code/inc/m24c64.h new file mode 100644 index 0000000..fa04220 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/m24c64.h @@ -0,0 +1,19 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: m24c64.h +*/ + +#define M24C64_PAGE_SIZE (32) +#define M24C64_EMPTY_CELL_VALUE (0xFF) + +uint8_t m24c64_poll(void); +uint8_t m24c64_read_byte(uint16_t memory_address); +void m24c64_write_byte(uint8_t data_byte, uint16_t memory_address); +void m24c64_read_page(uint8_t data_array[], uint8_t page_address); +void m24c64_write_page(uint8_t data_array[], uint8_t page_address); +void m24c64_erase_page(uint8_t page_address); +void m24c64_erase_all(void); diff --git a/Firmware/CubeIDE/Code/inc/main.h b/Firmware/CubeIDE/Code/inc/main.h new file mode 100644 index 0000000..d0484a0 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/main.h @@ -0,0 +1,23 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: main.h +*/ + +uint32_t get_uptime(void); +struct main_flags_struct *get_main_flags(void); + + + +struct main_flags_struct +{ + uint8_t gps_ready; + uint8_t gps_sync; + uint8_t rx_ready; + uint8_t time_slots_end; + uint8_t battery_low; + uint8_t act_status; +}; diff --git a/Firmware/CubeIDE/Code/inc/menu.h b/Firmware/CubeIDE/Code/inc/menu.h new file mode 100644 index 0000000..fd4fe16 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/menu.h @@ -0,0 +1,12 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: menu.h +*/ + +void init_menu(void); +void change_menu(uint8_t button_code); +void draw_current_menu(void); diff --git a/Firmware/CubeIDE/Code/inc/points.h b/Firmware/CubeIDE/Code/inc/points.h new file mode 100644 index 0000000..3e5cbd6 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/points.h @@ -0,0 +1,30 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: points.h +*/ + +#define MEMORY_POINT_NAME_LENGTH (5) //excluding string-end symbol \0 +#define MEMORY_SLOTS_TOTAL (5) + + + +void init_points(void); +struct memory_slot_struct **get_memory_slot(void); +void read_memory_slots(void); +void save_memory_point(uint8_t dev_num, char *point_name, uint8_t slot_num); +void load_memory_point(uint8_t dev_num, uint8_t slot_num); +void delete_memory_point(uint8_t slot_num); + + + +struct memory_slot_struct +{ + uint8_t exist_flag; //is this point exist (was previously saved) in memory? + char slot_name[sizeof("SX")]; //slot name S1...S5, not user-defined + char point_name[MEMORY_POINT_NAME_LENGTH + 1]; //user-defined point name in the slot + char save_date[sizeof("ddmmyy")]; //point save date +}; diff --git a/Firmware/CubeIDE/Code/inc/radio_config_Si4463.h b/Firmware/CubeIDE/Code/inc/radio_config_Si4463.h new file mode 100644 index 0000000..62d0eae --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/radio_config_Si4463.h @@ -0,0 +1,633 @@ +/*! @file radio_config.h + * @brief This file contains the automatically generated + * configurations. + * + * @n WDS GUI Version: 3.2.11.0 + * @n Device: Si4463 Rev.: B1 + * + * @b COPYRIGHT + * @n Silicon Laboratories Confidential + * @n Copyright 2017 Silicon Laboratories, Inc. + * @n http://www.silabs.com + */ + +#ifndef RADIO_CONFIG_H_ +#define RADIO_CONFIG_H_ + +// USER DEFINED PARAMETERS +// Define your own parameters here + +// INPUT DATA +/* +// Crys_freq(Hz): 26000000 Crys_tol(ppm): 50 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 1 ANT_DIV: 0 PM_pattern: 0 +// MOD_type: 3 Rsymb(sps): 3000 Fdev(Hz): 6000 RXBW(Hz): 100000 Manchester: 0 AFC_en: 1 Rsymb_error: 0.0 Chip-Version: 2 +// RF Freq.(MHz): 433.05 API_TC: 29 fhst: 25000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1 +// +// # RX IF frequency is -406250 Hz +// # WB filter 1 (BW = 99.20 kHz); NB-filter 15 (BW = 22.48 kHz) +// +// Modulation index: 4 +*/ + + +// CONFIGURATION PARAMETERS +#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 26000000L +#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x01 +#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07 +#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03 +#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000 + + +// CONFIGURATION COMMANDS + +/* +// Command: RF_POWER_UP +// Description: Command to power-up the device and select the operational mode and functionality. +*/ +#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0x8C, 0xBA, 0x80 + +/* +// Command: RF_GPIO_PIN_CFG +// Description: Configures the GPIO pins. +*/ +#define RF_GPIO_PIN_CFG 0x13, 0x44, 0x08, 0x21, 0x20, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_GLOBAL_XO_TUNE_2 +// Number of properties: 2 +// Group ID: 0x00 +// Start ID: 0x00 +// Default values: 0x40, 0x00, +// Descriptions: +// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator. +// GLOBAL_CLK_CFG - Clock configuration options. +*/ +#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x46, 0x00 + +/* +// Set properties: RF_GLOBAL_CONFIG_1 +// Number of properties: 1 +// Group ID: 0x00 +// Start ID: 0x03 +// Default values: 0x20, +// Descriptions: +// GLOBAL_CONFIG - Global configuration settings. +*/ +#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60 + +/* +// Set properties: RF_INT_CTL_ENABLE_2 +// Number of properties: 2 +// Group ID: 0x01 +// Start ID: 0x00 +// Default values: 0x04, 0x00, +// Descriptions: +// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin. +// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin. +*/ +#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x18 + +/* +// Set properties: RF_FRR_CTL_A_MODE_4 +// Number of properties: 4 +// Group ID: 0x02 +// Start ID: 0x00 +// Default values: 0x01, 0x02, 0x09, 0x00, +// Descriptions: +// FRR_CTL_A_MODE - Fast Response Register A Configuration. +// FRR_CTL_B_MODE - Fast Response Register B Configuration. +// FRR_CTL_C_MODE - Fast Response Register C Configuration. +// FRR_CTL_D_MODE - Fast Response Register D Configuration. +*/ +#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x0A, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PREAMBLE_TX_LENGTH_9 +// Number of properties: 9 +// Group ID: 0x10 +// Start ID: 0x00 +// Default values: 0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PREAMBLE_TX_LENGTH - Configure length of TX Preamble. +// PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. +// PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern. +// PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern. +// PREAMBLE_CONFIG - General configuration bits for the Preamble field. +// PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern. +// PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern. +// PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern. +// PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern. +*/ +#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x08, 0x14, 0x00, 0x0F, 0x31, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_SYNC_CONFIG_5 +// Number of properties: 5 +// Group ID: 0x11 +// Start ID: 0x00 +// Default values: 0x01, 0x2D, 0xD4, 0x2D, 0xD4, +// Descriptions: +// SYNC_CONFIG - Sync Word configuration bits. +// SYNC_BITS_31_24 - Sync word. +// SYNC_BITS_23_16 - Sync word. +// SYNC_BITS_15_8 - Sync word. +// SYNC_BITS_7_0 - Sync word. +*/ +#define RF_SYNC_CONFIG_5 0x11, 0x11, 0x05, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00 + +/* +// Set properties: RF_PKT_CRC_CONFIG_7 +// Number of properties: 7 +// Group ID: 0x12 +// Start ID: 0x00 +// Default values: 0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, +// Descriptions: +// PKT_CRC_CONFIG - Select a CRC polynomial and seed. +// PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening) +// PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening) +// PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening) +// PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening) +// PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling. +// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet. +*/ +#define RF_PKT_CRC_CONFIG_7 0x11, 0x12, 0x07, 0x00, 0x84, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x02 + +/* +// Set properties: RF_PKT_LEN_12 +// Number of properties: 12 +// Group ID: 0x12 +// Start ID: 0x08 +// Default values: 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PKT_LEN - Configuration bits for reception of a variable length packet. +// PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s). +// PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length). +// PKT_TX_THRESHOLD - TX FIFO almost empty threshold. +// PKT_RX_THRESHOLD - RX FIFO Almost Full threshold. +// PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value. +// PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value. +// PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1. +// PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1. +// PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value. +// PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value. +// PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2. +*/ +#define RF_PKT_LEN_12 0x11, 0x12, 0x0C, 0x08, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x11, 0x04, 0xAA, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PKT_FIELD_2_CRC_CONFIG_12 +// Number of properties: 12 +// Group ID: 0x12 +// Start ID: 0x14 +// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2. +// PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value. +// PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value. +// PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3. +// PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3. +// PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value. +// PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value. +// PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4. +// PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4. +// PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value. +// PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value. +// PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5. +*/ +#define RF_PKT_FIELD_2_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PKT_FIELD_5_CRC_CONFIG_12 +// Number of properties: 12 +// Group ID: 0x12 +// Start ID: 0x20 +// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5. +// PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value. +// PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value. +// PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1. +// PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1. +// PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value. +// PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value. +// PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2. +// PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2. +// PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value. +// PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value. +// PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3. +*/ +#define RF_PKT_FIELD_5_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PKT_RX_FIELD_3_CRC_CONFIG_9 +// Number of properties: 9 +// Group ID: 0x12 +// Start ID: 0x2C +// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3. +// PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value. +// PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value. +// PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4. +// PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4. +// PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value. +// PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value. +// PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5. +// PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5. +*/ +#define RF_PKT_RX_FIELD_3_CRC_CONFIG_9 0x11, 0x12, 0x09, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_MODEM_MOD_TYPE_12 +// Number of properties: 12 +// Group ID: 0x20 +// Start ID: 0x00 +// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, +// Descriptions: +// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation. +// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits. +// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer. +// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate +// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate +// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate +// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. +// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. +// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. +// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. +// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. +// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. +*/ +#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x01, 0xD4, 0xC0, 0x05, 0x8C, 0xBA, 0x80, 0x00, 0x01 + +/* +// Set properties: RF_MODEM_FREQ_DEV_0_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x0C +// Default values: 0xD3, +// Descriptions: +// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. +*/ +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xE4 + +/* +// Set properties: RF_MODEM_TX_RAMP_DELAY_8 +// Number of properties: 8 +// Group ID: 0x20 +// Start ID: 0x18 +// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, +// Descriptions: +// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting. +// MODEM_MDM_CTRL - MDM control. +// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation. +// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number). +// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number). +// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number). +// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter. +// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter. +*/ +#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20 + +/* +// Set properties: RF_MODEM_BCR_OSR_1_9 +// Number of properties: 9 +// Group ID: 0x20 +// Start ID: 0x22 +// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, +// Descriptions: +// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). +// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). +// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number). +// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number). +// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number). +// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value. +// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value. +// MODEM_BCR_GEAR - RX BCR loop gear control. +// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop. +*/ +#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x04, 0x3B, 0x00, 0x78, 0xFD, 0x00, 0x3D, 0x02, 0xC2 + +/* +// Set properties: RF_MODEM_AFC_GEAR_7 +// Number of properties: 7 +// Group ID: 0x20 +// Start ID: 0x2C +// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0, +// Descriptions: +// MODEM_AFC_GEAR - RX AFC loop gear control. +// MODEM_AFC_WAIT - RX AFC loop wait time control. +// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. +// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. +// MODEM_AFC_LIMITER_1 - Set the AFC limiter value. +// MODEM_AFC_LIMITER_0 - Set the AFC limiter value. +// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. +*/ +#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0xC0, 0x0A, 0x48, 0x18, 0xC0 + +/* +// Set properties: RF_MODEM_AGC_CONTROL_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x35 +// Default values: 0xE0, +// Descriptions: +// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. +*/ +#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2 + +/* +// Set properties: RF_MODEM_AGC_WINDOW_SIZE_9 +// Number of properties: 9 +// Group ID: 0x20 +// Start ID: 0x38 +// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, +// Descriptions: +// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm. +// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors. +// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors. +// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression. +// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression. +// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold. +// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold. +// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code. +// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector. +*/ +#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0xED, 0xED, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x2B + +/* +// Set properties: RF_MODEM_OOK_CNT1_9 +// Number of properties: 9 +// Group ID: 0x20 +// Start ID: 0x42 +// Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, +// Descriptions: +// MODEM_OOK_CNT1 - OOK control. +// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. +// MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors. +// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode. +// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold. +// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold. +// MODEM_ANT_DIV_MODE - Antenna diversity mode settings. +// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. +// MODEM_RSSI_THRESH - Configures the RSSI threshold. +*/ +#define RF_MODEM_OOK_CNT1_9 0x11, 0x20, 0x09, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x00, 0x3C, 0x01, 0x80, 0xFF + +/* +// Set properties: RF_MODEM_RSSI_CONTROL_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x4C +// Default values: 0x01, +// Descriptions: +// MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s). +*/ +#define RF_MODEM_RSSI_CONTROL_1 0x11, 0x20, 0x01, 0x4C, 0x02 + +/* +// Set properties: RF_MODEM_RSSI_COMP_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x4E +// Default values: 0x32, +// Descriptions: +// MODEM_RSSI_COMP - RSSI compensation value. +*/ +#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40 + +/* +// Set properties: RF_MODEM_CLKGEN_BAND_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x51 +// Default values: 0x08, +// Descriptions: +// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. +*/ +#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A + +/* +// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 +// Number of properties: 12 +// Group ID: 0x21 +// Start ID: 0x00 +// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, +// Descriptions: +// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. +*/ +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01 + +/* +// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 +// Number of properties: 12 +// Group ID: 0x21 +// Start ID: 0x0C +// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, +// Descriptions: +// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. +*/ +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66 + +/* +// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 +// Number of properties: 12 +// Group ID: 0x21 +// Start ID: 0x18 +// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, +// Descriptions: +// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. +*/ +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PA_MODE_4 +// Number of properties: 4 +// Group ID: 0x22 +// Start ID: 0x00 +// Default values: 0x08, 0x7F, 0x00, 0x5D, +// Descriptions: +// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size). +// PA_PWR_LVL - Configuration of PA output power level. +// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source. +// PA_TC - Configuration of PA ramping parameters. +*/ +#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x05, 0x00, 0x3D + +/* +// Set properties: RF_SYNTH_PFDCP_CPFF_7 +// Number of properties: 7 +// Group ID: 0x23 +// Start ID: 0x00 +// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, +// Descriptions: +// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection. +// SYNTH_PFDCP_CPINT - Integration charge pump current selection. +// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path. +// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter. +// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter. +// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. +// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. +*/ +#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 + +/* +// Set properties: RF_MATCH_VALUE_1_12 +// Number of properties: 12 +// Group ID: 0x30 +// Start ID: 0x00 +// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte. +// MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte. +// MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1. +// MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte. +// MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte. +// MATCH_CTRL_2 - Configuration of Match Byte 2. +// MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte. +// MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte. +// MATCH_CTRL_3 - Configuration of Match Byte 3. +// MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte. +// MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte. +// MATCH_CTRL_4 - Configuration of Match Byte 4. +*/ +#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_FREQ_CONTROL_INTE_8 +// Number of properties: 8 +// Group ID: 0x40 +// Start ID: 0x00 +// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, +// Descriptions: +// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number. +// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number. +// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number. +// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number. +// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size. +// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size. +// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. +// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. +*/ +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x0C, 0xFC, 0x0F, 0x07, 0xE0, 0x20, 0xFE + + +// AUTOMATICALLY GENERATED CODE! +// DO NOT EDIT/MODIFY BELOW THIS LINE! +// -------------------------------------------- + +#ifndef FIRMWARE_LOAD_COMPILE +#define RADIO_CONFIGURATION_DATA_ARRAY { \ + 0x07, RF_POWER_UP, \ + 0x08, RF_GPIO_PIN_CFG, \ + 0x06, RF_GLOBAL_XO_TUNE_2, \ + 0x05, RF_GLOBAL_CONFIG_1, \ + 0x06, RF_INT_CTL_ENABLE_2, \ + 0x08, RF_FRR_CTL_A_MODE_4, \ + 0x0D, RF_PREAMBLE_TX_LENGTH_9, \ + 0x09, RF_SYNC_CONFIG_5, \ + 0x0B, RF_PKT_CRC_CONFIG_7, \ + 0x10, RF_PKT_LEN_12, \ + 0x10, RF_PKT_FIELD_2_CRC_CONFIG_12, \ + 0x10, RF_PKT_FIELD_5_CRC_CONFIG_12, \ + 0x0D, RF_PKT_RX_FIELD_3_CRC_CONFIG_9, \ + 0x10, RF_MODEM_MOD_TYPE_12, \ + 0x05, RF_MODEM_FREQ_DEV_0_1, \ + 0x0C, RF_MODEM_TX_RAMP_DELAY_8, \ + 0x0D, RF_MODEM_BCR_OSR_1_9, \ + 0x0B, RF_MODEM_AFC_GEAR_7, \ + 0x05, RF_MODEM_AGC_CONTROL_1, \ + 0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \ + 0x0D, RF_MODEM_OOK_CNT1_9, \ + 0x05, RF_MODEM_RSSI_CONTROL_1, \ + 0x05, RF_MODEM_RSSI_COMP_1, \ + 0x05, RF_MODEM_CLKGEN_BAND_1, \ + 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \ + 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \ + 0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \ + 0x08, RF_PA_MODE_4, \ + 0x0B, RF_SYNTH_PFDCP_CPFF_7, \ + 0x10, RF_MATCH_VALUE_1_12, \ + 0x0C, RF_FREQ_CONTROL_INTE_8, \ + 0x00 \ + } +#else +#define RADIO_CONFIGURATION_DATA_ARRAY { 0 } +#endif + +// DEFAULT VALUES FOR CONFIGURATION PARAMETERS +#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L +#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00 +#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10 +#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01 +#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000 + +#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00 +#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00 +#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { } + +#ifndef RADIO_CONFIGURATION_DATA_ARRAY +#error "This property must be defined!" +#endif + +#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ +#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT +#endif + +#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER +#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT +#endif + +#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH +#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT +#endif + +#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP +#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT +#endif + +#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET +#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT +#endif + +#define RADIO_CONFIGURATION_DATA { \ + Radio_Configuration_Data_Array, \ + RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \ + RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \ + RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \ + RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \ + } + +#endif /* RADIO_CONFIG_H_ */ diff --git a/Firmware/CubeIDE/Code/inc/service.h b/Firmware/CubeIDE/Code/inc/service.h new file mode 100644 index 0000000..0a041c6 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/service.h @@ -0,0 +1,18 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: service.h +*/ + +void convert_timeout(uint32_t timeout_val, char *buffer); + +void delay_cyc(uint32_t cycles); +void copy_string(char *from, char *to); + +float atof32(char *input); +void ftoa32(float value, uint8_t precision, char *buffer); +int32_t atoi32(char *input); +void itoa32(int32_t value, char *buffer); diff --git a/Firmware/CubeIDE/Code/inc/settings.h b/Firmware/CubeIDE/Code/inc/settings.h new file mode 100644 index 0000000..9e9fc7b --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/settings.h @@ -0,0 +1,67 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: settings.h +*/ + +#define DEVICE_ID_LEN (2) //length of device ID, two ASCII characters +#define TIMEOUT_ALARM_DISABLED (0) +#define FENCE_ALARM_DISABLED (0) + + + +//Send interval settings +#define SEND_INTERVAL_1S_SETTING (0) +#define SEND_INTERVAL_5S_SETTING (1) +#define SEND_INTERVAL_10S_SETTING (2) +#define SEND_INTERVAL_30S_SETTING (3) +#define SEND_INTERVAL_60S_SETTING (4) + + + +//POWER SETTINGS +#define TX_POWER_10MILLIW_SETTING (0) +#define TX_POWER_25MILLIW_SETTING (1) +#define TX_POWER_40MILLIW_SETTING (2) +#define TX_POWER_100MILLIW_SETTING (3) + + + +//Structure with settings +struct settings_struct +{ + uint8_t device_number; //this device number in group, 1...DEVICES_IN_GROUP + + char device_id[DEVICE_ID_LEN]; //user id, ASCII symbols + + uint8_t freq_channel; //frequency tx/rx channel + + uint8_t tx_power_opt; //tx power option, not an actual value + + uint8_t send_interval_opt; //send interval option, not an actual value + + union + { + uint16_t as_integer; //timeout treshold in seconds, unsigned. if it == 0, then timeout alarm not trigger (but, anyway, timeout is counting). See TIMEOUT_ALARM_DISABLED + uint8_t as_array[2]; + } timeout_threshold; + + union + { + uint16_t as_integer; //fence treshold in meters, unsigned. if it == 0, then fence alarm not trigger. See FENCE_ALARM_DISABLED + uint8_t as_array[2]; + } fence_threshold; + +}; + + + +struct settings_struct *get_settings(void); +uint8_t *get_send_interval_values(void); +uint8_t *get_tx_power_values(void); +void settings_save_default(void); +void settings_load(void); +void settings_save(struct settings_struct *settings); diff --git a/Firmware/CubeIDE/Code/inc/si4463.h b/Firmware/CubeIDE/Code/inc/si4463.h new file mode 100644 index 0000000..e7f5292 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/si4463.h @@ -0,0 +1,15 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: si4463.h +*/ + +void si4463_init(void); +void si4463_tx_packet(void); +void si4463_start_rx(void); +uint8_t si4463_get_rx_packet(void); +uint8_t *get_air_packet_tx(void); +uint8_t *get_air_packet_rx(void); diff --git a/Firmware/CubeIDE/Code/inc/spi.h b/Firmware/CubeIDE/Code/inc/spi.h new file mode 100644 index 0000000..004c055 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/spi.h @@ -0,0 +1,13 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: spi.h +*/ + +void spi1_init(void); +void spi2_init(void); +uint8_t spi1_trx(uint8_t send_data); +uint8_t spi2_trx(uint8_t send_data); diff --git a/Firmware/CubeIDE/Code/inc/ssd1306.h b/Firmware/CubeIDE/Code/inc/ssd1306.h new file mode 100644 index 0000000..d7afe1c --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/ssd1306.h @@ -0,0 +1,47 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: ssd1306.h +*/ + +#define LCD_LAST_COL (20) +#define LCD_LAST_ROW (7) + + + +//Special sympols +#define SYMB_ARROW_UP ('\x80') +#define SYMB_ARROW_DOWN ('\x81') +#define SYMB_NO_SATT ('\x82') +#define SYMB_SATT_1D ('\x83') +#define SYMB_SATT_2D ('\x84') +#define SYMB_SATT_3D ('\x85') +#define SYMB_TIMEOUT ('\x86') +#define SYMB_ALARM ('\x87') +#define SYMB_BAT_0OF4 ('\x88') +#define SYMB_BAT_1OF4 ('\x89') +#define SYMB_BAT_2OF4 ('\x8A') +#define SYMB_BAT_3OF4 ('\x8B') +#define SYMB_BAT_4OF4 ('\x8C') +#define SYMB_DEGREE ('\x8D') +#define SYMB_FENCE ('\x8E') +#define SYMB_NOTE ('\x8F') + + + +void ssd1306_init(void); +void ssd1306_fill(void); +void ssd1306_clear(void); +void ssd1306_pixel(uint8_t x, uint8_t y, int8_t action); +void ssd1306_pos(uint8_t row, uint8_t col); +void ssd1306_char(char chr, uint8_t inv); +void ssd1306_char_pos(uint8_t row, uint8_t col, char chr, uint8_t inv); +void ssd1306_print(uint8_t row, uint8_t col, char *p_str, uint8_t inv); +void ssd1306_print_next(char *p_str, uint8_t inv); +void ssd1306_print_viceversa(uint8_t row, uint8_t col, char *p_str, uint8_t inv); +void ssd1306_bitmap(const uint8_t arr[]); +void ssd1306_update(void); +void ssd1306_print_byte(uint8_t row, uint8_t col, uint8_t *p_byte, uint8_t amount); diff --git a/Firmware/CubeIDE/Code/inc/ssd1306_bitmaps.h b/Firmware/CubeIDE/Code/inc/ssd1306_bitmaps.h new file mode 100644 index 0000000..59a1420 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/ssd1306_bitmaps.h @@ -0,0 +1,13 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: ssd1306_bitmaps.h +*/ + +extern const uint8_t startup_screen[1024]; +extern const uint8_t devices_blank[1024]; +extern const uint8_t radar_blank[1024]; +extern const uint8_t info_blank[1024]; diff --git a/Firmware/CubeIDE/Code/inc/ssd1306_font6x8.h b/Firmware/CubeIDE/Code/inc/ssd1306_font6x8.h new file mode 100644 index 0000000..1c68334 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/ssd1306_font6x8.h @@ -0,0 +1,157 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: ssd1306_font6x8.h +*/ + +//font 5x8 (intercharacter space not included, 6x8 with it) http://dotmatrixtool.com/ +const uint8_t font[][5] = +{ + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 0 //all symbols from 0x00 to 0x1F are ASCII '0' + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 1 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 2 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 3 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 4 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 5 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 6 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 7 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 8 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 9 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 10 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 11 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 12 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 13 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 14 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 15 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 16 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 17 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 18 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 19 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 20 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 21 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 22 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 23 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 24 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 25 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 26 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 27 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 28 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 29 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 30 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 31 + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // 0x20 32 + { 0x00, 0x00, 0x5F, 0x00, 0x00 }, // ! 0x21 33 + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " 0x22 34 + { 0x14, 0x7F, 0x14, 0x7F, 0x14 }, // # 0x23 35 + { 0x24, 0x2A, 0x7F, 0x2A, 0x12 }, // $ 0x24 36 + { 0x4C, 0x2C, 0x10, 0x68, 0x64 }, // % 0x25 37 + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & 0x26 38 + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' 0x27 39 + { 0x00, 0x1C, 0x22, 0x41, 0x00 }, // ( 0x28 40 + { 0x00, 0x41, 0x22, 0x1C, 0x00 }, // ) 0x29 41 + { 0x14, 0x08, 0x3E, 0x08, 0x14 }, // * 0x2A 42 + { 0x08, 0x08, 0x3E, 0x08, 0x08 }, // + 0x2B 43 + { 0x00, 0x00, 0x50, 0x30, 0x00 }, // , 0x2C 44 + { 0x10, 0x10, 0x10, 0x10, 0x10 }, // - 0x2D 45 + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . 0x2E 46 + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / 0x2F 47 + { 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 0x30 48 + { 0x00, 0x42, 0x7F, 0x40, 0x00 }, // 1 0x31 49 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 0x32 50 + { 0x21, 0x41, 0x45, 0x4B, 0x31 }, // 3 0x33 51 + { 0x18, 0x14, 0x12, 0x7F, 0x10 }, // 4 0x34 52 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 0x35 53 + { 0x3C, 0x4A, 0x49, 0x49, 0x30 }, // 6 0x36 54 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 0x37 55 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 0x38 56 + { 0x06, 0x49, 0x49, 0x29, 0x1E }, // 9 0x39 57 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : 0x3A 58 + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; 0x3B 59 + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < 0x3C 60 + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = 0x3D 61 + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > 0x3E 62 + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? 0x3F 63 + { 0x32, 0x49, 0x79, 0x41, 0x3E }, // @ 0x40 64 + { 0x7E, 0x11, 0x11, 0x11, 0x7E }, // A 0x41 65 + { 0x7F, 0x49, 0x49, 0x49, 0x36 }, // B 0x42 66 + { 0x3E, 0x41, 0x41, 0x41, 0x22 }, // C 0x43 67 + { 0x7F, 0x41, 0x41, 0x22, 0x1C }, // D 0x44 68 + { 0x7F, 0x49, 0x49, 0x49, 0x41 }, // E 0x45 69 + { 0x7F, 0x09, 0x09, 0x09, 0x01 }, // F 0x46 70 + { 0x3E, 0x41, 0x49, 0x49, 0x7A }, // G 0x47 71 + { 0x7F, 0x08, 0x08, 0x08, 0x7F }, // H 0x48 72 + { 0x00, 0x41, 0x7F, 0x41, 0x00 }, // I 0x49 73 + { 0x20, 0x40, 0x41, 0x3F, 0x01 }, // J 0x4A 74 + { 0x7F, 0x08, 0x14, 0x22, 0x41 }, // K 0x4B 75 + { 0x7F, 0x40, 0x40, 0x40, 0x40 }, // L 0x4C 76 + { 0x7F, 0x02, 0x0C, 0x02, 0x7F }, // M 0x4D 77 + { 0x7F, 0x04, 0x08, 0x10, 0x7F }, // N 0x4E 78 + { 0x3E, 0x41, 0x41, 0x41, 0x3E }, // O 0x4F 79 + { 0x7F, 0x09, 0x09, 0x09, 0x06 }, // P 0x50 80 + { 0x3E, 0x41, 0x51, 0x21, 0x5E }, // Q 0x51 81 + { 0x7F, 0x09, 0x19, 0x29, 0x46 }, // R 0x52 82 + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S 0x53 83 + { 0x01, 0x01, 0x7F, 0x01, 0x01 }, // T 0x54 84 + { 0x3F, 0x40, 0x40, 0x40, 0x3F }, // U 0x55 85 + { 0x1F, 0x20, 0x40, 0x20, 0x1F }, // V 0x56 86 + { 0x3F, 0x40, 0x38, 0x40, 0x3F }, // W 0x57 87 + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X 0x58 88 + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y 0x59 89 + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z 0x5A 90 + { 0x00, 0x7F, 0x41, 0x41, 0x00 }, // [ 0x5B 91 + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // \ 0x5C 92 + { 0x00, 0x41, 0x41, 0x7F, 0x00 }, // ] 0x5D 93 + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ 0x5E 94 + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ 0x5F 95 + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` 0x60 96 + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a 0x61 97 + { 0x7F, 0x48, 0x44, 0x44, 0x38 }, // b 0x62 98 + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c 0x63 99 + { 0x38, 0x44, 0x44, 0x48, 0x7F }, // d 0x64 100 + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e 0x65 101 + { 0x08, 0x7E, 0x09, 0x01, 0x02 }, // f 0x66 102 + { 0x0C, 0x52, 0x52, 0x52, 0x3E }, // g 0x67 103 + { 0x7F, 0x08, 0x04, 0x04, 0x78 }, // h 0x68 104 + { 0x00, 0x44, 0x7D, 0x40, 0x00 }, // i 0x69 105 + { 0x20, 0x40, 0x44, 0x3D, 0x00 }, // j 0x6A 106 + { 0x7F, 0x10, 0x28, 0x44, 0x00 }, // k 0x6B 107 + { 0x00, 0x41, 0x7F, 0x40, 0x00 }, // l 0x6C 108 + { 0x7C, 0x04, 0x18, 0x04, 0x78 }, // m 0x6D 109 + { 0x7C, 0x08, 0x04, 0x04, 0x78 }, // n 0x6E 110 + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o 0x6F 111 + { 0x7C, 0x14, 0x14, 0x14, 0x08 }, // p 0x70 112 + { 0x08, 0x14, 0x14, 0x18, 0x7C }, // q 0x71 113 + { 0x7C, 0x08, 0x04, 0x04, 0x08 }, // r 0x72 114 + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s 0x73 115 + { 0x04, 0x3F, 0x44, 0x40, 0x20 }, // t 0x74 116 + { 0x3C, 0x40, 0x40, 0x20, 0x7C }, // u 0x75 117 + { 0x1C, 0x20, 0x40, 0x20, 0x1C }, // v 0x76 118 + { 0x3C, 0x40, 0x30, 0x40, 0x3C }, // w 0x77 119 + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x 0x78 120 + { 0x0C, 0x50, 0x50, 0x50, 0x3C }, // y 0x79 121 + { 0x44, 0x64, 0x54, 0x4C, 0x44 }, // z 0x7A 122 + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { 0x7B 123 + { 0x00, 0x00, 0x7F, 0x00, 0x00 }, // | 0x7C 124 + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } 0x7D 125 + { 0x08, 0x04, 0x08, 0x10, 0x08 }, // ~ 0x7E 126 + { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, //  0x7F 127 + { 0x00, 0x00, 0x04, 0x02, 0x7f }, // 0x80 128 arrow up + { 0x00, 0x7f, 0x20, 0x10, 0x00 }, // 0x81 129 arrow down + { 0x22, 0x14, 0x08, 0x14, 0x22 }, // 0x82 130 no sattelites + { 0x71, 0x03, 0x41, 0x00, 0x40 }, // 0x83 131 sattelites only time fix + { 0x71, 0x03, 0x79, 0x00, 0x40 }, // 0x84 132 sattelites 2D fix + { 0x71, 0x03, 0x79, 0x00, 0x7c }, // 0x85 133 sattelites 3D fix + { 0x63, 0x75, 0x79, 0x75, 0x63 }, // 0x86 134 timeout + { 0x10, 0x1e, 0x3f, 0x1e, 0x10 }, // 0x87 135 alarm + { 0x7e, 0x43, 0x43, 0x43, 0x7e }, // 0x88 136 battery 0/4 + { 0x7e, 0x63, 0x63, 0x63, 0x7e }, // 0x89 137 battery 1/4 + { 0x7e, 0x73, 0x73, 0x73, 0x7e }, // 0x8A 138 battery 2/4 + { 0x7e, 0x7b, 0x7b, 0x7b, 0x7e }, // 0x8B 139 battery 3/4 + { 0x7e, 0x7f, 0x7f, 0x7f, 0x7e }, // 0x8C 140 battery 4/4 + { 0x07, 0x05, 0x07, 0x00, 0x00 }, // 0x8D 141 degree sign + { 0x55, 0x00, 0x41, 0x00, 0x55 }, // 0x8E 142 fence + { 0x60, 0x60, 0x7f, 0x02, 0x0c }, // 0x8F 143 note +}; diff --git a/Firmware/CubeIDE/Code/inc/timer.h b/Firmware/CubeIDE/Code/inc/timer.h new file mode 100644 index 0000000..ca7e37d --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/timer.h @@ -0,0 +1,17 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: timer.h +*/ + +void timers_init(void); +void make_a_beep(void); +void toggle_mute(void); +uint8_t get_mute_flag(void); +void timer1_start(void); +void timer1_stop_reload(void); +void timer2_stop(void); +void timer3_stop(void); diff --git a/Firmware/CubeIDE/Code/inc/uart.h b/Firmware/CubeIDE/Code/inc/uart.h new file mode 100644 index 0000000..2a1e129 --- /dev/null +++ b/Firmware/CubeIDE/Code/inc/uart.h @@ -0,0 +1,18 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: uart.h +*/ + +#define UART_BUF_LEN (1024) + + + +void uart_dma_init(void); +void uart_dma_stop(void); +void uart_dma_restart(void); +void backup_and_clear_uart_buffer(void); +void uart_tx(uint8_t data); diff --git a/Firmware/CubeIDE/Code/src/adc.c b/Firmware/CubeIDE/Code/src/adc.c new file mode 100644 index 0000000..43aee82 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/adc.c @@ -0,0 +1,126 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: adc.c +*/ + +#include "stm32f10x.h" +#include "adc.h" +#include "service.h" +#include "settings.h" +#include "points.h" +#include "lrns.h" +#include "gpio.h" + + + +#define GET_BAT_VOLTAGE_INTERVAL (10) + +#define V_BATTERY_0_TO_10 (3.0) +#define V_BATTERY_10_TO_25 (3.1) +#define V_BATTERY_25_TO_50 (3.3) +#define V_BATTERY_50_TO_75 (3.6) +#define V_BATTERY_75_TO_100 (3.9) + + + +const float vref = 3.3; +uint8_t bat_interval_counter = 0; +float bat_voltage; + + + +//ADC Init +void adc_init(void) +{ + //ADC prescaller + RCC->CFGR &= ~RCC_CFGR_ADCPRE; //div by 8 + + //ADC clock on + RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; + + //Sample time + ADC1->SMPR2 |= ADC_SMPR2_SMP0_1; //13.5 cycles + + //Number of conversions in regular sequence + ADC1->SQR1 &= ~ADC_SQR1_L; //1 conversion + + //First channel in regular sequence + ADC1->SQR3 &= ~ADC_SQR3_SQ1; //channel #0 + + //Extermal trigger enable for regular sequence + ADC1->CR2 |= ADC_CR2_EXTTRIG; + + //Event to start regular sequence + ADC1->CR2 |= ADC_CR2_EXTSEL; //start by software + + //ADC enable + ADC1->CR2 |= ADC_CR2_ADON; + + //Calibration + delay_cyc(100000); + ADC1->CR2 |= ADC_CR2_CAL; //start cal + while (ADC1->CR2 & ADC_CR2_CAL); //wait +} + + + +//Get battery voltage +uint8_t adc_get_bat_voltage(void) +{ + bat_interval_counter++; + + if (bat_interval_counter >= GET_BAT_VOLTAGE_INTERVAL) + { + bat_interval_counter = 0; + + bat_mon_on(); //Enable resistive divider and wait a bit + delay_cyc(100); + + //Start conversation + ADC1->CR2 |= ADC_CR2_SWSTART; + + //Wait for conversation end + while (!(ADC1->SR & ADC_SR_EOC)); + + bat_mon_off(); //Disable resistive divider + + //Convert + bat_voltage = 2 * ((ADC1->DR * vref) / 4096); //x2 due to resistive voltage divider before ADC input + + //Refresh flags + if (bat_voltage > V_BATTERY_75_TO_100) + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_75_TO_100); + } + else if (bat_voltage > V_BATTERY_50_TO_75) + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_50_TO_75); + } + else if (bat_voltage > V_BATTERY_25_TO_50) + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_25_TO_50); + } + else if (bat_voltage > V_BATTERY_10_TO_25) + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_10_TO_25); + } + else + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_0_TO_10); + return 1; + } + } + + return 0; +} + + + +float get_bat_voltage(void) +{ + return bat_voltage; +} diff --git a/Firmware/CubeIDE/Code/src/buttons.c b/Firmware/CubeIDE/Code/src/buttons.c new file mode 100644 index 0000000..ff74a1d --- /dev/null +++ b/Firmware/CubeIDE/Code/src/buttons.c @@ -0,0 +1,157 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: buttons.c +*/ + +#include "stm32f10x.h" +#include "buttons.h" + + + +//SCAN_INTERVAL: 1000000 = 0.8 s; 1500 = 1 ms +#define SCAN_INTERVAL (1500) + +#define BUTTONS_NUM (5) //five buttons total + +#define BUTTON_WEIGHT_MAX (16) +#define BUTTON_WEIGHT_MIN (0) + +#define BUTTON_THRESHOLD_HI (12) //0.8 of BUTTON_WEIGHT_MAX +#define BUTTON_THRESHOLD_LO (4) //0.2 of BUTTON_WEIGHT_MAX + +#define BUTTON_PRESSED (0) +#define BUTTON_RELEASED (1) + +#define BUTTON_PRESSED_COUNTER_MAX (UINT16_MAX) +#define BUTTON_PRESSED_COUNTER_THRESHOLD (350) //short or long cick? + +#define TIMEOUT_NO_OVERFLOW (0) +#define TIMEOUT_OVERFLOW (1) + +#define BUTTON_ACTIONS_NUM (2) //two actions: short click, long click +#define BUTTON_ACTION_SHORT (0) +#define BUTTON_ACTION_LONG (1) + + + +uint32_t scan_interval_counter = 0; +uint32_t idr_register_copy = 0; + +uint8_t button_weight[BUTTONS_NUM] = {BUTTON_WEIGHT_MAX, + BUTTON_WEIGHT_MAX, + BUTTON_WEIGHT_MAX, + BUTTON_WEIGHT_MAX, + BUTTON_WEIGHT_MAX}; + +uint8_t button_state[BUTTONS_NUM] = {BUTTON_RELEASED, + BUTTON_RELEASED, + BUTTON_RELEASED, + BUTTON_RELEASED, + BUTTON_RELEASED}; + +uint8_t button_prev_state[BUTTONS_NUM] = {BUTTON_RELEASED, + BUTTON_RELEASED, + BUTTON_RELEASED, + BUTTON_RELEASED, + BUTTON_RELEASED}; + +uint16_t button_pressed_counter[BUTTONS_NUM] = {0}; + +uint8_t timeout_state[BUTTONS_NUM] = {TIMEOUT_NO_OVERFLOW, + TIMEOUT_NO_OVERFLOW, + TIMEOUT_NO_OVERFLOW, + TIMEOUT_NO_OVERFLOW, + TIMEOUT_NO_OVERFLOW}; + +uint8_t timeout_prev_state[BUTTONS_NUM] = {TIMEOUT_NO_OVERFLOW, + TIMEOUT_NO_OVERFLOW, + TIMEOUT_NO_OVERFLOW, + TIMEOUT_NO_OVERFLOW, + TIMEOUT_NO_OVERFLOW}; + + + +//button return code = {ButtonNumber(0...BUTTONS_NUM-1) * BUTTON_ACTIONS_NUM + BUTTON_ACTION(_SHORT)(_LONG)} + 1 +uint8_t scan_buttons(void) +{ + if (scan_interval_counter < SCAN_INTERVAL) + { + scan_interval_counter++; //increase counter + } + else + { + scan_interval_counter = 0; //time to scan buttons! reset counter + + idr_register_copy = GPIOA->IDR; //save pins data + idr_register_copy &= (GPIO_IDR_IDR1 | //mask needed pins + GPIO_IDR_IDR2 | + GPIO_IDR_IDR3 | + GPIO_IDR_IDR4 | + GPIO_IDR_IDR5); + + idr_register_copy >>= 1; //align bits to the left, now IDR1(PA1) is in LSBit position + + for (uint8_t i = 0; i < BUTTONS_NUM; i++) //update buttons weight (digital capacitor, increase or decrease "charge") + { + if (idr_register_copy & ((uint32_t)1 << i)) //check pin state + { + if (button_weight[i] < BUTTON_WEIGHT_MAX) + { + button_weight[i] += 1; // if input pin = 1, increase weight + } + } + else + { + if (button_weight[i] > BUTTON_WEIGHT_MIN) + { + button_weight[i] -= 1; // if input pin = 0, decrease weight + } + } + } + + for (uint8_t i = 0; i < BUTTONS_NUM; i++) //make a desicion "button is pressed or not?" (with hysteresis) + { + if (button_weight[i] > BUTTON_THRESHOLD_HI) + { + button_prev_state[i] = button_state[i]; + button_state[i] = BUTTON_RELEASED; + } + else if (button_weight[i] < BUTTON_THRESHOLD_LO) + { + button_prev_state[i] = button_state[i]; + button_state[i] = BUTTON_PRESSED; + } + } + + for (uint8_t i = 0; i < BUTTONS_NUM; i++) //check click duration. short click after button released (and before timeout overflow); long click after timeout overflow + { + if ((button_state[i] == BUTTON_PRESSED) && (button_pressed_counter[i] < BUTTON_PRESSED_COUNTER_MAX)) //increase timeout counter, update overflow states + { + button_pressed_counter[i]++; + + timeout_prev_state[i] = timeout_state[i]; + timeout_state[i] = (button_pressed_counter[i] > BUTTON_PRESSED_COUNTER_THRESHOLD); //overflow or not? 1 or 0? + } + + if ((button_state[i] == BUTTON_RELEASED) && (button_prev_state[i] == BUTTON_PRESSED)) //button has been released + { + button_pressed_counter[i] = 0; + + if (timeout_state[i] == TIMEOUT_NO_OVERFLOW) + { + return (i * BUTTON_ACTIONS_NUM + BUTTON_ACTION_SHORT) + 1; //if before overflow, then short click + } + } + + if ((timeout_state[i] == TIMEOUT_OVERFLOW) && (timeout_prev_state[i] == TIMEOUT_NO_OVERFLOW)) //overflow occured + { + return (i * BUTTON_ACTIONS_NUM + BUTTON_ACTION_LONG) + 1; //long click + } + } + } + return BTN_NO_ACTION; +} diff --git a/Firmware/CubeIDE/Code/src/gpio.c b/Firmware/CubeIDE/Code/src/gpio.c new file mode 100644 index 0000000..06c8887 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/gpio.c @@ -0,0 +1,332 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: gpio.c +*/ + +#include "stm32f10x.h" +#include "gpio.h" + + + +//Initialization of all used ports +void gpio_init(void) +{ + //Port A + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; + + //PA0 - ADC0 (Battery voltage) + GPIOA->CRL &= ~GPIO_CRL_MODE0; //input mode + GPIOA->CRL &= ~GPIO_CRL_CNF0; //analog input + + //PA1 - Button 1 + GPIOA->CRL &= ~GPIO_CRL_MODE1; //input mode + GPIOA->CRL &= ~GPIO_CRL_CNF1_0; //input with pull + GPIOA->CRL |= GPIO_CRL_CNF1_1; + GPIOA->ODR |= GPIO_ODR_ODR1; //pull-up on + + //PA2 - Button 2 + GPIOA->CRL &= ~GPIO_CRL_MODE2; //input mode + GPIOA->CRL &= ~GPIO_CRL_CNF2_0; //input with pull + GPIOA->CRL |= GPIO_CRL_CNF2_1; + GPIOA->ODR |= GPIO_ODR_ODR2; //pull-up on + + //PA3 - Button 3 + GPIOA->CRL &= ~GPIO_CRL_MODE3; //input mode + GPIOA->CRL &= ~GPIO_CRL_CNF3_0; //input with pull + GPIOA->CRL |= GPIO_CRL_CNF3_1; + GPIOA->ODR |= GPIO_ODR_ODR3; //pull-up on + + //PA4 - Button 4 + GPIOA->CRL &= ~GPIO_CRL_MODE4; //input mode + GPIOA->CRL &= ~GPIO_CRL_CNF4_0; //input with pull + GPIOA->CRL |= GPIO_CRL_CNF4_1; + GPIOA->ODR |= GPIO_ODR_ODR4; //pull-up on + + //PA5 - Button 5 + GPIOA->CRL &= ~GPIO_CRL_MODE5; //input mode + GPIOA->CRL &= ~GPIO_CRL_CNF5_0; //input with pull + GPIOA->CRL |= GPIO_CRL_CNF5_1; + GPIOA->ODR |= GPIO_ODR_ODR5; //pull-up on + + //PA6 - Battery monitor switch + GPIOA->CRL |= GPIO_CRL_MODE6; //output 50 MHz + GPIOA->CRL &= ~GPIO_CRL_CNF6; //output push-pull + + //PA7 - Piezo Buzzer (PWM) + GPIOA->CRL |= GPIO_CRL_MODE7; //output mode + GPIOA->CRL &= ~GPIO_CRL_CNF7_0; //alternate output push-pull + GPIOA->CRL |= GPIO_CRL_CNF7_1; + + //PA8 - RES (SSD1306) + GPIOA->CRH |= GPIO_CRH_MODE8; //output 50 MHz + GPIOA->CRH &= ~GPIO_CRH_CNF8; //output push-pull + + //PA9 - USART TX1 (Debug out) + GPIOA->CRH |= GPIO_CRH_MODE9; //output 50 MHz + GPIOA->CRH &= ~GPIO_CRH_CNF9_0; //alternate output push-pull + GPIOA->CRH |= GPIO_CRH_CNF9_1; + + //PA10 - USART RX1 (GPS NMEA here) + GPIOA->CRH &= ~GPIO_CRH_MODE10; //input + GPIOA->CRH |= GPIO_CRH_CNF10_0; //alternate input floating + GPIOA->CRH &= ~GPIO_CRH_CNF10_1; + + //PA11 - GPS (PPS interrupt) + GPIOA->CRH &= ~GPIO_CRH_MODE11; //input mode + GPIOA->CRH &= ~GPIO_CRH_CNF11_0; //input with pull + GPIOA->CRH |= GPIO_CRH_CNF11_1; + GPIOA->ODR &= ~GPIO_ODR_ODR11; //pull-down + + //PA12 - CTS (SI4463) + GPIOA->CRH &= ~GPIO_CRH_MODE11; //input mode + GPIOA->CRH &= ~GPIO_CRH_CNF11_0; //input with pull + GPIOA->CRH |= GPIO_CRH_CNF11_1; + GPIOA->ODR &= ~GPIO_ODR_ODR11; //pull-down + + //PA15 - CS (SI4463) + GPIOA->CRH |= GPIO_CRH_MODE15; //output 50 MHz + GPIOA->CRH &= ~GPIO_CRH_CNF15; //output push-pull + + + //Port B + RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; + + //PB0 - Red LED + GPIOB->CRL |= GPIO_CRL_MODE0; //output 50 MHz + GPIOB->CRL &= ~GPIO_CRL_CNF0; //output push-pull + + //PB1 - Green LED + GPIOB->CRL |= GPIO_CRL_MODE1; //output 50 MHz + GPIOB->CRL &= ~GPIO_CRL_CNF1; //output push-pull + + //PB3 - SCK (SI4463) + GPIOB->CRL |= GPIO_CRL_MODE3; //output 50 MHz + GPIOB->CRL &= ~GPIO_CRL_CNF3_0; //alternate output push-pull + GPIOB->CRL |= GPIO_CRL_CNF3_1; + + //PB4 - MISO (SI4463) + GPIOB->CRL &= ~GPIO_CRL_MODE4; //input mode + GPIOB->CRL |= GPIO_CRL_CNF4_0; //floating input + GPIOB->CRL &= ~GPIO_CRL_CNF4_1; + + //PB5 - MOSI (SI4463) + GPIOB->CRL |= GPIO_CRL_MODE5; //output 50 MHz + GPIOB->CRL &= ~GPIO_CRL_CNF5_0; //alternate output push-pull + GPIOB->CRL |= GPIO_CRL_CNF5_1; + + //PB6 - IRQn (SI4463 interrupt) + GPIOB->CRL &= ~GPIO_CRL_MODE6; //input mode + GPIOB->CRL &= ~GPIO_CRL_CNF6_0; //input with pull + GPIOB->CRL |= GPIO_CRL_CNF6_1; + GPIOB->ODR |= GPIO_ODR_ODR6; //pull-up + + //PB7 - SDN (SI4463) + GPIOB->CRL |= GPIO_CRL_MODE7; //output 50 MHz + GPIOB->CRL &= ~GPIO_CRL_CNF7; //output push-pull + + //PB10 - I2C SCL + GPIOB->CRH |= GPIO_CRH_MODE10; //output 50 MHz + GPIOB->CRH |= GPIO_CRH_CNF10; //alternate function open-drain + + //PB11 - I2C SDA + GPIOB->CRH |= GPIO_CRH_MODE11; //output max speed + GPIOB->CRH |= GPIO_CRH_CNF11; //alternate function open-drain + + //PB12 - CS (SSD1306) + GPIOB->CRH |= GPIO_CRH_MODE12; //output 50 MHz + GPIOB->CRH &= ~GPIO_CRH_CNF12; //output push-pull + + //PB13 - SCK (SSD1306) + GPIOB->CRH |= GPIO_CRH_MODE13; //output 50 MHz + GPIOB->CRH &= ~GPIO_CRH_CNF13_0; //alternate output push-pull + GPIOB->CRH |= GPIO_CRH_CNF13_1; + + //PB14 - D/C (SSD1306) + GPIOB->CRH |= GPIO_CRH_MODE14; //output 50 MHz + GPIOB->CRH &= ~GPIO_CRH_CNF14; //output push-pull + + //PB15 - MOSI (SSD1306) + GPIOB->CRH |= GPIO_CRH_MODE15; //output 50 MHz + GPIOB->CRH &= ~GPIO_CRH_CNF15_0; //alternate output push-pull + GPIOB->CRH |= GPIO_CRH_CNF15_1; + + + //Port C + RCC->APB2ENR |= RCC_APB2ENR_IOPCEN; + + //PC13 - Blue led + GPIOC->CRH |= GPIO_CRH_MODE13; //output 50 MHz + GPIOC->CRH &= ~GPIO_CRH_CNF13; //output push-pull + led_board_off(); +} + + + +//Init external interrupts +void ext_int_init(void) +{ + RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; //enable afio clock + + //PA11 GPS PPS interrupt on rising edge + AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI11_PA; //exti 11 source is port A + EXTI->RTSR |= EXTI_RTSR_TR11; //interrupt 11 on rising edge + EXTI->IMR |= EXTI_IMR_MR11; //unmask interrupt 11 + NVIC_EnableIRQ(EXTI15_10_IRQn); //enable interrupt + + //PB6 SI4463 RX interrupt on falling edge + AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI6_PB; //exti 6 source is port B + EXTI->FTSR |= EXTI_FTSR_TR6; //interrupt 6 on falling edge + EXTI->IMR |= EXTI_IMR_MR6; //unmask interrupt 6 + NVIC_EnableIRQ(EXTI9_5_IRQn); //enable interrupt + + EXTI->PR = (uint32_t)0x0007FFFF; //clear all pending interrupts +} + + + +//Red led on +void led_red_on(void) +{ + GPIOB->BSRR = GPIO_BSRR_BS0; +} + + + +//Red led off +void led_red_off(void) +{ + GPIOB->BSRR = GPIO_BSRR_BR0; +} + + + +//Red green on +void led_green_on(void) +{ + GPIOB->BSRR = GPIO_BSRR_BS1; +} + + + +//Red green off +void led_green_off(void) +{ + GPIOB->BSRR = GPIO_BSRR_BR1; +} + + + +//Blue led on +void led_board_on(void) +{ + GPIOC->BSRR = GPIO_BSRR_BR13; +} + + + +//Blue led off +void led_board_off(void) +{ + GPIOC->BSRR = GPIO_BSRR_BS13; +} + + + +//SDN SI4463 active +void sdn_si4463_active(void) +{ + GPIOB->BSRR = GPIO_BSRR_BS7; +} + + + +//SDN SI4463 inactive +void sdn_si4463_inactive(void) +{ + GPIOB->BSRR = GPIO_BSRR_BR7; +} + + + +//CS SI4463 active +void cs_si4463_active(void) +{ + GPIOA->BSRR = GPIO_BSRR_BR15; +} + + + +//CS SI4463 inactive +void cs_si4463_inactive(void) +{ + GPIOA->BSRR = GPIO_BSRR_BS15; +} + + + +//RES SSD1306 active +void res_ssd1306_active(void) +{ + GPIOA->BSRR = GPIO_BSRR_BR8; +} + + + +//RES SSD1306 inactive +void res_ssd1306_inactive(void) +{ + GPIOA->BSRR = GPIO_BSRR_BS8; +} + + + +//Data mode SSD1306 +void ssd1306_data_mode(void) +{ + GPIOB->BSRR = GPIO_BSRR_BS14; +} + + + +//Command mode SSD1306 +void ssd1306_command_mode(void) +{ + GPIOB->BSRR = GPIO_BSRR_BR14; +} + + + +//CS SSD1306 active +void cs_ssd1306_active(void) +{ + GPIOB->BSRR = GPIO_BSRR_BR12; +} + + + +//CS SSD1306 inactive +void cs_ssd1306_inactive(void) +{ + GPIOB->BSRR = GPIO_BSRR_BS12; +} + + + +//Battery monitoring on +void bat_mon_on(void) +{ + GPIOA->BSRR = GPIO_BSRR_BS6; +} + + + +//Battery monitoring off +void bat_mon_off(void) +{ + GPIOA->BSRR = GPIO_BSRR_BR6; +} + diff --git a/Firmware/CubeIDE/Code/src/gps.c b/Firmware/CubeIDE/Code/src/gps.c new file mode 100644 index 0000000..437283e --- /dev/null +++ b/Firmware/CubeIDE/Code/src/gps.c @@ -0,0 +1,461 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: gps.c +*/ + +#include +#include "stm32f10x.h" +#include "main.h" +#include "gps.h" +#include "uart.h" +#include "service.h" +#include "settings.h" +#include "points.h" +#include "lrns.h" + + + +void gps_raw_convert_to_numerical(void); + + + +const float knots_to_kph = 1.852; //knots to kilometers per hour multiplyer + + +uint8_t nmea_checksum(uint16_t pos); +uint8_t parse_RMC(void); +uint8_t parse_GGA(void); +uint8_t parse_GSA(void); +uint8_t parse_GSV(void); + + + +char nmea_data[UART_BUF_LEN]; +struct gps_raw_struct gps_raw; +struct gps_num_struct gps_num; + + + +char tmp_char[15]; +uint8_t tmp_uint8; +float tmp_float; + + + +//Parse all gps fields all together +uint8_t parse_gps(void) +{ + memset(&gps_raw, 0, sizeof(gps_raw)); + if (parse_RMC() && parse_GGA() && parse_GSA() && parse_GSV()) + { + memset(&gps_num, 0, sizeof(gps_num)); + gps_raw_convert_to_numerical(); + return 1; + } + else + { + return 0; + } +} + + + +//Converts gps_raw data (symbols) to gps_num data (numbers) with conversions if needed +void gps_raw_convert_to_numerical(void) +{ + //Time + tmp_char[0] = gps_raw.time[0]; + tmp_char[1] = gps_raw.time[1]; + tmp_char[2] = 0; + gps_num.hour = (uint8_t)atoi32(&tmp_char[0]); + + tmp_char[0] = gps_raw.time[2]; + tmp_char[1] = gps_raw.time[3]; + tmp_char[2] = 0; + gps_num.minute = (uint8_t)atoi32(&tmp_char[0]); + + tmp_char[0] = gps_raw.time[4]; + tmp_char[1] = gps_raw.time[5]; + tmp_char[2] = 0; + gps_num.second = (uint8_t)atoi32(&tmp_char[0]); + + + //Date + tmp_char[0] = gps_raw.date[0]; + tmp_char[1] = gps_raw.date[1]; + tmp_char[2] = 0; + gps_num.day = (uint8_t)atoi32(&tmp_char[0]); + + tmp_char[0] = gps_raw.date[2]; + tmp_char[1] = gps_raw.date[3]; + tmp_char[2] = 0; + gps_num.month = (uint8_t)atoi32(&tmp_char[0]); + + tmp_char[0] = gps_raw.date[4]; + tmp_char[1] = gps_raw.date[5]; + tmp_char[2] = 0; + gps_num.year = (uint8_t)atoi32(&tmp_char[0]); + + + //Latitude + tmp_char[0] = gps_raw.latitude[0]; + tmp_char[1] = gps_raw.latitude[1]; + tmp_char[2] = 0; + tmp_uint8 = (uint8_t)atoi32(&tmp_char[0]); //int part of lat + tmp_float = atof32(&(gps_raw.latitude[2])); //frac part of lat + + tmp_float /= 60.0; //convert ddmm.mmmm to dd.dddddd + tmp_float += tmp_uint8; + + if (gps_raw.ns[0] == 'S') + { + gps_num.latitude.in_deg = tmp_float * -1.0; //negative (southern) latitudes + } + else + { + gps_num.latitude.in_deg = tmp_float; + } + + gps_num.latitude.in_rad = gps_num.latitude.in_deg * deg_to_rad; + + + //Longitude + tmp_char[0] = gps_raw.longitude[0]; + tmp_char[1] = gps_raw.longitude[1]; + tmp_char[2] = gps_raw.longitude[2]; + tmp_char[3] = 0; + tmp_uint8 = (uint8_t)atoi32(&tmp_char[0]); //int part of lon + tmp_float = atof32(&(gps_raw.longitude[3])); //frac part of lon + + tmp_float /= 60.0; //convert dddmm.mmmm to ddd.dddddd + tmp_float += tmp_uint8; + + if (gps_raw.ew[0] == 'W') + { + gps_num.longitude.in_deg = tmp_float * -1.0; //negative (western) longitudes + } + else + { + gps_num.longitude.in_deg = tmp_float; + } + + gps_num.longitude.in_rad = gps_num.longitude.in_deg * deg_to_rad; + + + //Speed + gps_num.speed = atof32(&(gps_raw.speed[0])) * knots_to_kph; + + //Course + gps_num.course = atof32(&(gps_raw.course[0])); + + //Altitude + gps_num.altitude = atof32(&(gps_raw.altitude[0])); + + //Satellites + gps_num.sat_view = (uint8_t)atoi32(&(gps_raw.sat_view[0])); + gps_num.sat_used = (uint8_t)atoi32(&(gps_raw.sat_used[0])); + + + //Status, Mode, PDOP + if (gps_raw.status[0] == 'A') + { + gps_num.status = GPS_DATA_VALID; + } + else + { + gps_num.status = GPS_DATA_INVALID; + } + + gps_num.mode = (uint8_t)atoi32(&(gps_raw.mode[0])); + + gps_num.pdop = atof32(&(gps_raw.pdop[0])); +} + + + +//Parse RMC sentence +uint8_t parse_RMC(void) +{ + uint8_t comma = 0; + uint8_t sym = 0; + uint16_t pos = 0; + + while (!((nmea_data[pos] == '$') && + (nmea_data[pos + 3] == 'R') && + (nmea_data[pos + 4] == 'M') && + (nmea_data[pos + 5] == 'C')) && pos < UART_BUF_LEN) //search for start pos + { + pos++; + } + + if(nmea_checksum(pos) == 0) + { + return 0; //checksum error + } + + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + { + if (nmea_data[i] == '*') return 1; //end of the sentence + + if (nmea_data[i] == ',') + { + comma++; //increase comma counter + sym = 0; + } + else + { + switch (comma) //surfing through RMC data fields + { + case 1: + gps_raw.time[sym++] = nmea_data[i]; + break; + case 2: + gps_raw.status[sym++] = nmea_data[i]; + break; + case 3: + gps_raw.latitude[sym++] = nmea_data[i]; + break; + case 4: + gps_raw.ns[sym++] = nmea_data[i]; + break; + case 5: + gps_raw.longitude[sym++] = nmea_data[i]; + break; + case 6: + gps_raw.ew[sym++] = nmea_data[i]; + break; + case 7: + gps_raw.speed[sym++] = nmea_data[i]; + break; + case 8: + gps_raw.course[sym++] = nmea_data[i]; + break; + case 9: + gps_raw.date[sym++] = nmea_data[i]; + break; + default: + break; + } + } + } + return 1; +} + + + +//Parse GGA sentence +uint8_t parse_GGA(void) +{ + uint8_t comma = 0; + uint8_t sym = 0; + uint16_t pos = 0; + + while (!((nmea_data[pos] == '$') && + (nmea_data[pos + 3] == 'G') && + (nmea_data[pos + 4] == 'G') && + (nmea_data[pos + 5] == 'A')) && pos < UART_BUF_LEN) //search for start pos + { + pos++; + } + + if(nmea_checksum(pos) == 0) + { + return 0; //checksum error + } + + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + { + if (nmea_data[i] == '*') return 1; //end of the sentence + + if (nmea_data[i] == ',') + { + comma++; //increase comma counter + sym = 0; + } + else + { + switch (comma) //surfing through GGA data fields + { + case 7: + gps_raw.sat_used[sym++] = nmea_data[i]; + break; + case 9: + gps_raw.altitude[sym++] = nmea_data[i]; + break; + default: + break; + } + } + } + return 1; +} + + + +//Parse GSA sentence +uint8_t parse_GSA(void) +{ + uint8_t comma = 0; + uint8_t sym = 0; + uint16_t pos = 0; + + while (!((nmea_data[pos] == '$') && + (nmea_data[pos + 3] == 'G') && + (nmea_data[pos + 4] == 'S') && + (nmea_data[pos + 5] == 'A')) && pos < UART_BUF_LEN) //search for start pos + { + pos++; + } + + if(nmea_checksum(pos) == 0) + { + return 0; //checksum error + } + + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + { + if (nmea_data[i] == '*') return 1; //end of the sentence + + if (nmea_data[i] == ',') + { + comma++; //increase comma counter + sym = 0; + } + else + { + switch (comma) //surfing through GSA data fields + { + case 2: + gps_raw.mode[sym++] = nmea_data[i]; + break; + case 15: + gps_raw.pdop[sym++] = nmea_data[i]; + break; + default: + break; + } + } + } + return 1; +} + + + +//Parse GSV sentence +uint8_t parse_GSV(void) +{ + uint8_t comma = 0; + uint8_t sym = 0; + uint16_t pos = 0; + + while (!((nmea_data[pos] == '$') && + (nmea_data[pos + 3] == 'G') && + (nmea_data[pos + 4] == 'S') && + (nmea_data[pos + 5] == 'V')) && pos < UART_BUF_LEN) //search for start pos + { + pos++; + } + + if(nmea_checksum(pos) == 0) + { + return 0; //checksum error + } + + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + { + if (nmea_data[i] == '*') return 1; //end of the sentence + + if (nmea_data[i] == ',') + { + comma++; //increase comma counter + sym = 0; + } + else + { + switch (comma) //surfing through GSV data fields + { + case 3: + gps_raw.sat_view[sym++] = nmea_data[i]; + break; + default: + break; + } + } + } + return 1; +} + + + +//NMEA checksum +uint8_t nmea_checksum(uint16_t pos) +{ + uint8_t CheckSum = 0; + uint8_t MessageCheckSum = 0; + + pos++; //pick up symbol right after $ + while (nmea_data[pos] != '*') + { + CheckSum ^= nmea_data[pos]; + if (++pos >= UART_BUF_LEN) return 0; //check sum not found + } + + if (nmea_data[++pos] > 0x40) + { + MessageCheckSum = (nmea_data[pos] - 0x37) << 4; //ascii hex to number + } + else + { + MessageCheckSum = (nmea_data[pos] - 0x30) << 4; + } + + if (nmea_data[++pos] > 0x40) + { + MessageCheckSum += (nmea_data[pos] - 0x37); //ascii hex to number + } + else + { + MessageCheckSum += (nmea_data[pos] - 0x30); + } + + if (MessageCheckSum == CheckSum) + { + return 1; + } + else + { + return 0; + } +} + + + +uint8_t get_gps_status(void) +{ + return gps_num.status; +} + + + +char *get_nmea_buf(void) +{ + return &nmea_data[0]; +} + + + +struct gps_raw_struct *get_gps_raw(void) +{ + return &gps_raw; +} + + + +struct gps_num_struct *get_gps_num(void) +{ + return &gps_num; +} diff --git a/Firmware/CubeIDE/Code/src/i2c.c b/Firmware/CubeIDE/Code/src/i2c.c new file mode 100644 index 0000000..18a57af --- /dev/null +++ b/Firmware/CubeIDE/Code/src/i2c.c @@ -0,0 +1,33 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: gpio.c +*/ + +#include "stm32f10x.h" +#include "i2c.h" +#include "service.h" + + + +#define I2C_CLOCK_DELAY (500) + + + +void i2c_init(void) +{ + //I2C config + RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; //enable i2c clock + + I2C2->CR2 &= ~I2C_CR2_FREQ; //clear bits before set + I2C2->CR2 |= (uint16_t)10; //10 MHz periph clock + + //Stndard mode + I2C2->CCR |= (uint16_t)180; //CCR = TSCL/(2 * TPCLK1); TSCL = 1 / 100kHz standard mode freq; TPCLK1 = 1 / APB1 clock 36 MHz + I2C2->TRISE |= (uint16_t)37; //TRISE = (Tr max/TPCLK1)+1; Tr max = 1000nS for standard mode + + I2C2->CR1 |= I2C_CR1_PE; //enable i2c2 +} diff --git a/Firmware/CubeIDE/Code/src/lrns.c b/Firmware/CubeIDE/Code/src/lrns.c new file mode 100644 index 0000000..a245f84 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/lrns.c @@ -0,0 +1,491 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: lrns.c +*/ + +#include +#include +#include "stm32f10x.h" +#include "main.h" +#include "service.h" +#include "settings.h" +#include "gps.h" +#include "points.h" +#include "lrns.h" +#include "si4463.h" +#include "gpio.h" + + + +//(bit) start position in "flag" variable +#define FLAGS_BATTERY_POS (0) +#define FLAGS_GPS_FIX_POS (3) +#define FLAGS_PDOP_POS (4) +#define FLAGS_ALARM_POS (5) + +//bit masks in "flag" variable +#define FLAGS_BATTERY_MASK (0x07) +#define FLAGS_GPS_FIX_MASK (0x08) +#define FLAGS_PDOP_MASK (0x10) +#define FLAGS_ALARM_MASK (0x20) + + + +//Air packet structure and fields position (must match structure "gps_air") +#define PACKET_DEVICE_NUMBER_POS (0) +#define PACKET_DEVICE_ID_POS (1) +#define PACKET_FLAGS_POS (3) +#define PACKET_LATITUDE_POS (4) +#define PACKET_LONGITUDE_POS (8) +#define PACKET_ALTITUDE_POS (12) +#define PACKET_SPEED_POS (14) +#define PACKET_COURSE_POS (15) + + + +#define PDOP_THRESHOLD (6.0) + + + +const double rad_to_deg = 57.29577951308232; //rad to deg multiplyer +const double deg_to_rad = 0.0174532925199433; //deg to rad multiplyer + +const double twice_mean_earth_radius = 12742016.0; // 2 * 6371008 meters +const double pi_div_by_4 = 0.7853981633974483; // pi / 4 + + + +struct gps_air_struct gps_air[DEVICES_IN_GROUP + 1]; //structure for devices from 1 to DEVICES_IN_GROUP. Index 0 is invalid and always empty +struct gps_air_struct *p_gps_air[DEVICES_IN_GROUP + 1]; + +struct gps_rel_struct gps_rel[DEVICES_IN_GROUP + 1]; //structure with relative coordinates. Indexing is the same as above +struct gps_rel_struct *p_gps_rel[DEVICES_IN_GROUP + 1]; + +struct dev_aux_struct dev_aux[DEVICES_IN_GROUP + 1]; //structure with auxiliary information. Indexing is the same as above +struct dev_aux_struct *p_dev_aux[DEVICES_IN_GROUP + 1]; + +struct settings_struct *p_settings; +struct gps_num_struct *p_gps_num; +uint8_t *p_air_packet_tx; +uint8_t *p_air_packet_rx; + +uint8_t device_number; + + + +void init_lrns(void) +{ + //Clear mem + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + memset(&gps_air[dev], 0, sizeof(gps_air[dev])); + memset(&gps_rel[dev], 0, sizeof(gps_rel[dev])); + } + + //Get external things + p_settings = get_settings(); + p_gps_num = get_gps_num(); + p_air_packet_tx = get_air_packet_tx(); + p_air_packet_rx = get_air_packet_rx(); + + //This device number + device_number = p_settings->device_number; + + //Exist flag + dev_aux[device_number].exist_flag = 1; + + //ID + gps_air[device_number].device_id[0] = p_settings->device_id[0]; //note: ID loads only once at startup + gps_air[device_number].device_id[1] = p_settings->device_id[1]; +} + + + +//Set this device flags +void set_device_flags(uint8_t parameter_to_set, uint8_t parameter_value) +{ + uint8_t mask; + uint8_t pos; + + switch (parameter_to_set) + { + case FLAGS_BATTERY: + mask = FLAGS_BATTERY_MASK; + pos = FLAGS_BATTERY_POS; + break; + + case FLAGS_GPS_FIX: + mask = FLAGS_GPS_FIX_MASK; + pos = FLAGS_GPS_FIX_POS; + break; + + case FLAGS_PDOP: + mask = FLAGS_PDOP_MASK; + pos = FLAGS_PDOP_POS; + break; + + case FLAGS_ALARM: + mask = FLAGS_ALARM_MASK; + pos = FLAGS_ALARM_POS; + break; + } + + gps_air[device_number].flags &= ~mask; //clear bits + parameter_value &= (mask >> pos); //clear non-masked bits + gps_air[device_number].flags |= (parameter_value << pos); //add to flags +} + + + +//Get any device flags +uint8_t get_device_flags(uint8_t dev_num, uint8_t parameter_to_get) +{ + uint8_t mask; + uint8_t pos; + + switch (parameter_to_get) + { + case FLAGS_BATTERY: + mask = FLAGS_BATTERY_MASK; + pos = FLAGS_BATTERY_POS; + break; + + case FLAGS_GPS_FIX: + mask = FLAGS_GPS_FIX_MASK; + pos = FLAGS_GPS_FIX_POS; + break; + + case FLAGS_PDOP: + mask = FLAGS_PDOP_MASK; + pos = FLAGS_PDOP_POS; + break; + + case FLAGS_ALARM: + mask = FLAGS_ALARM_MASK; + pos = FLAGS_ALARM_POS; + break; + } + + return (gps_air[dev_num].flags & mask) >> pos; +} + + + +//Check alarm status of each device and make red led on if any alarm exist +uint8_t check_alarms(void) +{ + uint8_t led_status = 0; + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + if (get_device_flags(dev, FLAGS_ALARM) == FLAG_ALARM_ON) + { + led_status = 1; + } + } + + if (led_status == 1) + { + led_red_on(); + return 1; + } + else + { + led_red_off(); + return 0; + } +} + + + +void calc_timeout(uint32_t current_uptime) +{ + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + if (dev_aux[dev].exist_flag == 1) + { + dev_aux[dev].timeout = current_uptime - dev_aux[dev].timestamp; + } + } +} + + + +//Check devices timeout and set flags if needed +uint8_t check_timeout(void) +{ + uint8_t timeout_status = 0; + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + if (dev_aux[dev].memory_point_flag == 0) //no timeout alarm for memory points + { + if (p_settings->timeout_threshold.as_integer != TIMEOUT_ALARM_DISABLED) + { + if (dev_aux[dev].timeout > p_settings->timeout_threshold.as_integer) + { + dev_aux[dev].timeout_flag = 1; + timeout_status = 1; + } + else + { + dev_aux[dev].timeout_flag = 0; + } + } + } + } + + if (timeout_status == 1) + { + return 1; + } + else + { + return 0; + } +} + + + +uint8_t check_fence(void) +{ + uint8_t fence_status = 0; + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + if (dev_aux[dev].exist_flag) + { + if (gps_rel[dev].distance > p_settings->fence_threshold.as_integer) + { + dev_aux[dev].fence_flag = 1; + fence_status = 1; + } + else + { + dev_aux[dev].fence_flag = 0; + } + } + } + + if (fence_status == 1) + { + return 1; + } + else + { + return 0; + } +} + + + +void process_all_devices(void) +{ + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + if (dev_aux[dev].exist_flag == 1) //process mem points too + { + calc_relative_position(dev); + } + } +} + + + +//Update gps_air structure with coordinates of this device in order to transmit them further +void gps_air_update_my_data(uint32_t uptime) +{ + + //Timestamp + dev_aux[device_number].timestamp = uptime; + + + //Flags + if (p_gps_num->mode == GPS_POSITION_3DFIX) + { + set_device_flags(FLAGS_GPS_FIX, FLAG_GPS_FIX_3D); + } + else + { + set_device_flags(FLAGS_GPS_FIX, FLAG_GPS_FIX_2D); + } + + if (p_gps_num->pdop <= PDOP_THRESHOLD) + { + set_device_flags(FLAGS_PDOP, FLAG_PDOP_GOOD); + } + else + { + set_device_flags(FLAGS_PDOP, FLAG_PDOP_BAD); + } + + //Latitude & Longitude + gps_air[device_number].latitude.as_float = p_gps_num->latitude.in_deg; + gps_air[device_number].longitude.as_float = p_gps_num->longitude.in_deg; + + //Altitude + gps_air[device_number].altitude.as_integer = (int16_t)p_gps_num->altitude; + + //Speed + gps_air[device_number].speed = (uint8_t)p_gps_num->speed; + + //Course + gps_air[device_number].course.as_integer = (uint16_t)p_gps_num->course; +} + + + +//Copy gps_air struct data to the TX air packet +void fill_air_packet_with_struct_data(void) +{ + p_air_packet_tx[PACKET_DEVICE_NUMBER_POS] = device_number; //this device number + p_air_packet_tx[PACKET_DEVICE_ID_POS] = gps_air[device_number].device_id[0]; + p_air_packet_tx[PACKET_DEVICE_ID_POS + 1] = gps_air[device_number].device_id[1]; + p_air_packet_tx[PACKET_FLAGS_POS] = gps_air[device_number].flags; + p_air_packet_tx[PACKET_LATITUDE_POS] = gps_air[device_number].latitude.as_array[0]; + p_air_packet_tx[PACKET_LATITUDE_POS + 1] = gps_air[device_number].latitude.as_array[1]; + p_air_packet_tx[PACKET_LATITUDE_POS + 2] = gps_air[device_number].latitude.as_array[2]; + p_air_packet_tx[PACKET_LATITUDE_POS + 3] = gps_air[device_number].latitude.as_array[3]; + p_air_packet_tx[PACKET_LONGITUDE_POS] = gps_air[device_number].longitude.as_array[0]; + p_air_packet_tx[PACKET_LONGITUDE_POS + 1] = gps_air[device_number].longitude.as_array[1]; + p_air_packet_tx[PACKET_LONGITUDE_POS + 2] = gps_air[device_number].longitude.as_array[2]; + p_air_packet_tx[PACKET_LONGITUDE_POS + 3] = gps_air[device_number].longitude.as_array[3]; + p_air_packet_tx[PACKET_ALTITUDE_POS] = gps_air[device_number].altitude.as_array[0]; + p_air_packet_tx[PACKET_ALTITUDE_POS + 1] = gps_air[device_number].altitude.as_array[1]; + p_air_packet_tx[PACKET_SPEED_POS] = gps_air[device_number].speed; + p_air_packet_tx[PACKET_COURSE_POS] = gps_air[device_number].course.as_array[0]; + p_air_packet_tx[PACKET_COURSE_POS + 1] = gps_air[device_number].course.as_array[1]; +} + + + +//Copy RX air packet data to the gps_air struct +uint8_t fill_struct_with_air_packet_data(uint32_t uptime) +{ + uint8_t rx_device = p_air_packet_rx[PACKET_DEVICE_NUMBER_POS]; //extract device number from received packet + + dev_aux[rx_device].exist_flag = 1; + dev_aux[rx_device].timestamp = uptime; + gps_air[rx_device].device_id[0] = p_air_packet_rx[PACKET_DEVICE_ID_POS]; + gps_air[rx_device].device_id[1] = p_air_packet_rx[PACKET_DEVICE_ID_POS + 1]; + gps_air[rx_device].flags = p_air_packet_rx[PACKET_FLAGS_POS]; + gps_air[rx_device].latitude.as_array[0] = p_air_packet_rx[PACKET_LATITUDE_POS]; + gps_air[rx_device].latitude.as_array[1] = p_air_packet_rx[PACKET_LATITUDE_POS + 1]; + gps_air[rx_device].latitude.as_array[2] = p_air_packet_rx[PACKET_LATITUDE_POS + 2]; + gps_air[rx_device].latitude.as_array[3] = p_air_packet_rx[PACKET_LATITUDE_POS + 3]; + gps_air[rx_device].longitude.as_array[0] = p_air_packet_rx[PACKET_LONGITUDE_POS]; + gps_air[rx_device].longitude.as_array[1] = p_air_packet_rx[PACKET_LONGITUDE_POS + 1]; + gps_air[rx_device].longitude.as_array[2] = p_air_packet_rx[PACKET_LONGITUDE_POS + 2]; + gps_air[rx_device].longitude.as_array[3] = p_air_packet_rx[PACKET_LONGITUDE_POS + 3]; + gps_air[rx_device].altitude.as_array[0] = p_air_packet_rx[PACKET_ALTITUDE_POS]; + gps_air[rx_device].altitude.as_array[1] = p_air_packet_rx[PACKET_ALTITUDE_POS + 1]; + gps_air[rx_device].speed = p_air_packet_rx[PACKET_SPEED_POS]; + gps_air[rx_device].course.as_array[0] = p_air_packet_rx[PACKET_COURSE_POS]; + gps_air[rx_device].course.as_array[1] = p_air_packet_rx[PACKET_COURSE_POS + 1]; + + return rx_device; +} + + + +// Heart of the device <3 +//Calculates distance between two GPS points (using haversine formula) +//Calculates heading between two GPS points (loxodrome, or rhumb line) +//Calculates altitude difference +void calc_relative_position(uint8_t another_device) +{ + double lat1, lat2, lon1, lon2; + double distance, heading; + + //my position + lat1 = p_gps_num->latitude.in_rad; + lon1 = p_gps_num->longitude.in_rad; + + //position of the device to calculate relative position + lat2 = gps_air[another_device].latitude.as_float * deg_to_rad; + lon2 = gps_air[another_device].longitude.as_float * deg_to_rad; + + if (lat1 == lat2) + { + lat2 += 0.00000001; //slightly shift the position + } + + if (lon1 == lon2) + { + lon2 += 0.00000001; //slightly shift the position + } + + distance = twice_mean_earth_radius * + asin( sqrt( pow(sin((lat2 - lat1) / 2), 2) + + cos(lat2) * cos(lat1) * pow(sin((lon2 - lon1) / 2), 2))); + + heading = atan((lon2 - lon1) / + log(tan(pi_div_by_4 + lat2 / 2) / tan(pi_div_by_4 + lat1 / 2))); + + + if ((lat2 > lat1) && (lon2 > lon1)) + { + heading *= rad_to_deg; + } + else if ((lat2 > lat1) && (lon2 < lon1)) + { + heading = 360.0 + heading * rad_to_deg; + } + else if (lat2 < lat1) + { + heading = 180.0 + heading * rad_to_deg; + } + + gps_rel[another_device].distance = (uint32_t)distance; + + if (gps_rel[another_device].distance == 0) + { + gps_rel[another_device].heading = 0; //if distance is zero then make heading equals zero too + } + else + { + gps_rel[another_device].heading = (uint16_t)heading; + } + + gps_rel[another_device].altitude_diff = gps_air[another_device].altitude.as_integer - (int16_t)p_gps_num->altitude; +} + + + +struct gps_air_struct **get_gps_air(void) +{ + for (uint8_t i = 0; i <= DEVICES_IN_GROUP; i++) + { + p_gps_air[i] = &gps_air[i]; + } + + return &p_gps_air[0]; +} + + + +struct gps_rel_struct **get_gps_rel(void) +{ + for (uint8_t i = 0; i <= DEVICES_IN_GROUP; i++) + { + p_gps_rel[i] = &gps_rel[i]; + } + + return &p_gps_rel[0]; +} + + + +struct dev_aux_struct **get_dev_aux(void) +{ + for (uint8_t i = 0; i <= DEVICES_IN_GROUP; i++) + { + p_dev_aux[i] = &dev_aux[i]; + } + + return &p_dev_aux[0]; +} diff --git a/Firmware/CubeIDE/Code/src/m24c64.c b/Firmware/CubeIDE/Code/src/m24c64.c new file mode 100644 index 0000000..44e1a89 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/m24c64.c @@ -0,0 +1,396 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: m24c64.c +*/ + +#include "stm32f10x.h" +#include "m24c64.h" +#include "i2c.h" + + + +#define M24C64_POLL_ATTEMPTS (100) //takes ~10ms @ 100 kHz I2C + +#define M24C64_ADDRESS_WRITE_MODE (0xA0) +#define M24C64_ADDRESS_READ_MODE (0xA1) + +#define M24C64_WHOLE_SIZE (8192) +#define M24C64_PAGES_TOTAL (256) + + + +uint8_t m24c64_poll(void) +{ + uint16_t SR1_tmp; + uint16_t SR2_tmp; + uint8_t attempts = M24C64_POLL_ATTEMPTS; + + while (attempts) + { + //Start + I2C2->CR1 |= I2C_CR1_START; + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + { + } + //Clear + SR1_tmp = I2C2->SR1; + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_WRITE_MODE; + //Wait for address end of transmission or NAK reception + do + { + SR1_tmp = I2C2->SR1; + } + while (!(SR1_tmp & I2C_SR1_ADDR) && !(SR1_tmp & I2C_SR1_AF)); //"ADDR is not set after a NACK reception" + //Clear + SR1_tmp = I2C2->SR1; + SR2_tmp = I2C2->SR2; + + //Check acknowledge failure + if (SR1_tmp & I2C_SR1_AF) + { + //no acknowledge is returned, slave is busy + I2C2->SR1 = ~(I2C_SR1_AF); //write 0 to clear AF bit + + attempts--; //slave is not ready, decrement attmepts counter + } + else if (SR1_tmp & I2C_SR1_ADDR) + { + //Stop + I2C2->CR1 |= I2C_CR1_STOP; + + return 1; //slave is ready + } + else + { + attempts--; //??? + } + } + + SR2_tmp = SR2_tmp + 1; + + //Stop before end + I2C2->CR1 |= I2C_CR1_STOP; + + return 0; //end of attmepts, slave is busy or absent +} + + + +uint8_t m24c64_read_byte(uint16_t memory_address) +{ + uint8_t result = 0; + + if (m24c64_poll()) + { + uint16_t SR_tmp; + + //Start + I2C2->CR1 |= I2C_CR1_START; + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + { + } + //Clear + SR_tmp = I2C2->SR1; + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_WRITE_MODE; + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + { + } + //Clear + SR_tmp = I2C2->SR1; + SR_tmp = I2C2->SR2; + + //Memory address high byte + I2C2->DR = (uint8_t)(memory_address >> 8); + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + { + } + + //Memory address low byte + I2C2->DR = (uint8_t)memory_address; + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + { + } + + + //Start (restart actually) + I2C2->CR1 |= I2C_CR1_START; + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + { + } + //Clear + SR_tmp = I2C2->SR1; + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_READ_MODE; + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + { + } + //Clear + SR_tmp = I2C2->SR1; + SR_tmp = I2C2->SR2; + + //NACK next byte + I2C2->CR1 &= ~I2C_CR1_ACK; + //Stop + I2C2->CR1 |= I2C_CR1_STOP; + //Wait for data register not empty + while (!(I2C2->SR1 & I2C_SR1_RXNE)) + { + } + + SR_tmp = SR_tmp + 1; + + //Read requested byte + result = I2C2->DR; + } + else + { + result = 0; + } + + return result; +} + + + +void m24c64_write_byte(uint8_t data_byte, uint16_t memory_address) +{ + if (m24c64_poll()) + { + uint8_t SR_tmp; + + //Start + I2C2->CR1 |= I2C_CR1_START; + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + { + } + //Clear + SR_tmp = I2C2->SR1; + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_WRITE_MODE; + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + { + } + //Clear + SR_tmp = I2C2->SR1; + SR_tmp = I2C2->SR2; + + //Memory address high byte + I2C2->DR = (uint8_t)(memory_address >> 8); + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + { + } + + //Memory address low byte + I2C2->DR = (uint8_t)memory_address; + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + { + } + + //Write byte + I2C2->DR = data_byte; + //Wait byte transfer finish + while (!(I2C2->SR1 & I2C_SR1_BTF)) + { + } + + SR_tmp = SR_tmp + 1; + + //Stop + I2C2->CR1 |= I2C_CR1_STOP; + } +} + + + +void m24c64_read_page(uint8_t data_array[], uint8_t page_address) +{ + if (m24c64_poll()) + { + uint8_t SR_tmp; + uint16_t memory_address = page_address * M24C64_PAGE_SIZE; + + //Start + I2C2->CR1 |= I2C_CR1_START; + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + { + } + //Clear + SR_tmp = I2C2->SR1; + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_WRITE_MODE; + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + { + } + //Clear + SR_tmp = I2C2->SR1; + SR_tmp = I2C2->SR2; + + //Memory address high byte + I2C2->DR = (uint8_t)(memory_address >> 8); + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + { + } + + //Memory address low byte + I2C2->DR = (uint8_t)memory_address; + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + { + } + + + //Start (restart actually) + I2C2->CR1 |= I2C_CR1_START; + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + { + } + //Clear + SR_tmp = I2C2->SR1; + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_READ_MODE; + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + { + } + //Clear + SR_tmp = I2C2->SR1; + SR_tmp = I2C2->SR2; + + for (uint8_t i = 0; i < M24C64_PAGE_SIZE - 1; i++) + { + //ACK next byte + I2C2->CR1 |= I2C_CR1_ACK; + //Wait for data register not empty + while (!(I2C2->SR1 & I2C_SR1_RXNE)) + { + } + + //Read byte + data_array[i] = I2C2->DR; + } + + //NACK last byte + I2C2->CR1 &= ~I2C_CR1_ACK; + //Stop + I2C2->CR1 |= I2C_CR1_STOP; + //Wait for data register not empty + while (!(I2C2->SR1 & I2C_SR1_RXNE)) + { + } + + //Read last byte + data_array[M24C64_PAGE_SIZE - 1] = I2C2->DR; + + SR_tmp = SR_tmp + 1; + } +} + + + +void m24c64_write_page(uint8_t data_array[], uint8_t page_address) +{ + if (m24c64_poll()) + { + uint8_t SR_tmp = 0; + uint16_t memory_address = page_address * M24C64_PAGE_SIZE; + + //Start + I2C2->CR1 |= I2C_CR1_START; + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + { + } + //Clear + SR_tmp = I2C2->SR1; + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_WRITE_MODE; + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + { + } + //Clear + SR_tmp = I2C2->SR1; + SR_tmp = I2C2->SR2; + + //Memory address high byte + I2C2->DR = (uint8_t)(memory_address >> 8); + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + { + } + + //Memory address low byte + I2C2->DR = (uint8_t)memory_address; + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + { + } + + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + { + //Write byte + I2C2->DR = data_array[i]; + //Wait byte transfer finish + while (!(I2C2->SR1 & I2C_SR1_BTF)) + { + } + } + + SR_tmp = SR_tmp + 1; + + //Stop + I2C2->CR1 |= I2C_CR1_STOP; + } +} + + + +void m24c64_erase_page(uint8_t page_address) +{ + uint8_t empty_page[M24C64_PAGE_SIZE]; + + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + { + empty_page[i] = M24C64_EMPTY_CELL_VALUE; + } + + m24c64_write_page(&empty_page[0], page_address); +} + + + +void m24c64_erase_all(void) +{ + for (uint16_t page = 0; page < M24C64_PAGES_TOTAL; page++) + { + m24c64_erase_page(page); + } +} diff --git a/Firmware/CubeIDE/Code/src/main.c b/Firmware/CubeIDE/Code/src/main.c new file mode 100644 index 0000000..3987a68 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/main.c @@ -0,0 +1,336 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: main.c +*/ + +#include +#include "stm32f10x.h" +#include "main.h" +#include "gpio.h" +#include "spi.h" +#include "ssd1306.h" +#include "service.h" +#include "uart.h" +#include "gps.h" +#include "si4463.h" +#include "timer.h" +#include "i2c.h" +#include "m24c64.h" +#include "settings.h" +#include "buttons.h" +#include "menu.h" +#include "adc.h" +#include "points.h" +#include "lrns.h" +#include "ssd1306_bitmaps.h" + + + +//TIMERS +uint32_t uptime = 0; +uint32_t pps_counter = 0; +uint8_t overflow_counter = 0; +uint8_t time_slot = 0; + + + +//MAIN +struct main_flags_struct main_flags = {0, 0, 0, 0, 0, 0}; +struct settings_struct *p_settings; +struct gps_num_struct *p_gps_num; +uint8_t *p_send_interval_values; + + + +//PROGRAM +int main(void) +{ + gpio_init(); + timers_init(); + spi1_init(); + spi2_init(); + i2c_init(); + uart_dma_init(); + settings_load(); + ssd1306_init(); + si4463_init(); + ext_int_init(); + adc_init(); + adc_get_bat_voltage(); + init_lrns(); + init_menu(); + init_points(); + + p_settings = get_settings(); + p_gps_num = get_gps_num(); + p_send_interval_values = get_send_interval_values(); + + ssd1306_bitmap(&startup_screen[0]); + ssd1306_update(); + delay_cyc(5000000); + draw_current_menu(); + + __enable_irq(); + make_a_beep(); + + while (1) + { + //Scan Keys + change_menu(scan_buttons()); + + + //Parse GPS after PPS interrupt or UART DMA overflow + if (main_flags.gps_ready == 1) + { + main_flags.gps_ready = 0; + + + if (parse_gps() == 1) + { + if (main_flags.gps_sync == 1) + { + if (get_gps_status() == GPS_DATA_VALID) + { + gps_air_update_my_data(uptime); + fill_air_packet_with_struct_data(); //fill air data with coordinates of this device (this occur before first time slot interrupt) + } + else //if PPS exist but data is invalid (rare situation) + { + timer1_stop_reload(); //stop time slot timer due to nothing to transmitt + } + } + + draw_current_menu(); + } + else if (main_flags.gps_sync == 1) + { + timer1_stop_reload(); //stop time slot timer due to nothing to transmitt + } + } + + + //Extract received packet + if (main_flags.rx_ready == 1) + { + main_flags.rx_ready = 0; + + if (si4463_get_rx_packet()) + { + fill_struct_with_air_packet_data(uptime); //parse air data from another device (which has ended TX in the current time_slot) + } + } + + + //Checks after receiving packets from all devices; performing beep + if (main_flags.time_slots_end == 1) + { + main_flags.time_slots_end = 0; + + process_all_devices(); //calculate relative position for each active device + + uint8_t any_alarm_status = 0; + any_alarm_status += check_alarms(); + any_alarm_status += check_timeout(); //check timeout flags and get the result only after the end of the TRX sequence + any_alarm_status += check_fence(); + + if (any_alarm_status > 0) + { + make_a_beep(); + } + + } + else if ((main_flags.battery_low == 1) && (main_flags.gps_sync == 0)) //else check battery low flag + { + make_a_beep(); + main_flags.battery_low = 0; + } + + } +} + + + + + +//DMA UART RX overflow +void DMA1_Channel5_IRQHandler(void) +{ + DMA1->IFCR = DMA_IFCR_CGIF5; //clear all interrupt flags for DMA channel 5 + + uart_dma_stop(); + backup_and_clear_uart_buffer(); + uart_dma_restart(); + + main_flags.gps_ready = 1; + main_flags.gps_sync = 0; //no pps signal + pps_counter = 0; + led_green_off(); +} + + + +//GPS PPS interrupt +void EXTI15_10_IRQHandler(void) +{ + EXTI->PR = EXTI_PR_PR11; //clear interrupt + timer1_start(); //the first thing to do is start time slot timer right after PPS + + uart_dma_stop(); //fix the data + backup_and_clear_uart_buffer(); + uart_dma_restart(); + + pps_counter++; + switch (pps_counter) + { + case 1: //skip first PPS, ignore previous nmea data + timer1_stop_reload(); + main_flags.gps_ready = 0; + main_flags.gps_sync = 0; + break; + + case 2: //skip second PPS, but fix the nmea data acquired after first PPS + timer1_stop_reload(); + main_flags.gps_ready = 1; + main_flags.gps_sync = 0; + break; + + default: //at the moment, the nmea data, captured after first PPS, is parsed + main_flags.gps_ready = 1; + main_flags.gps_sync = 1; + + if ((p_gps_num->second % p_send_interval_values[p_settings->send_interval_opt]) == 0) //calc division remainder + { + main_flags.act_status = 1; //we are ready to show we are in act + } + else + { + timer1_stop_reload(); + } + + break; + } +} + + + +//SI4463 RX interrupt (RX valid or CRC error) +void EXTI9_5_IRQHandler(void) +{ + EXTI->PR = EXTI_PR_PR6; //clear interrupt + + main_flags.rx_ready = 1; +} + + +/* + TIMINGS LEGEND (DEVICES_IN_GROUP = 6) + +----+ +----+ + | | | | + | | | | PPS Signal + | | | | ++-------+ +--------------------------------------------+ +------+ + + ^ ^ ^ ^ ^ ^ ^ ^ + | | | | | | | | + | | | | | | | | Time Slot # Timer Interrupt # Action + | | | | | | | | (time_slot) (overflow_counter) + | | | | | | | | + | | | | | | | | + | | | | | | | | + | | | | | | | | + | | | | | | | | + | | | | | | | | + | | | | | | | +---------------------+ 7 Stop Timer1, Set main_flags.time_slots_end + | | | | | | | 6 + | | | | | | +--------------------------+ 6 + | | | | | | 5 + | | | | | +-------------------------------+ 5 + | | | | | 4 + | | | | +------------------------------------+ 4 + | | | | 3 + | | | +-----------------------------------------+ 3 + | | | 2 + | | +----------------------------------------------+ 2 + | | 1 + | +---------------------------------------------------+ 1 + | Timer1 interval + +--------------------------------------------------------+ PPS Interrupt, Start Timer1 +*/ + +//Time slot interrupt +void TIM1_UP_IRQHandler(void) +{ + TIM1->SR &= ~TIM_SR_UIF; //clear interrupt + + overflow_counter++; //increment ovf counter (starts from 1) + + if(overflow_counter == (DEVICES_IN_GROUP + 1)) //if interrupt at the end of the last time slot + { + timer1_stop_reload(); + overflow_counter = 0; + main_flags.time_slots_end = 1; + led_green_off(); + } + else + { + time_slot = overflow_counter; + + if (time_slot == p_settings->device_number) + { + si4463_tx_packet(); + } + else + { + si4463_start_rx(); + } + } + + if (main_flags.act_status == 1) + { + main_flags.act_status = 0; + led_green_on(); //make ACT led on only here, after we are shure that gps data is valid (otherwise we would never reach this interrupt) + } +} + + + +//Uptime counter (every 1 second) +void SysTick_Handler(void) +{ + uptime++; + + main_flags.battery_low = adc_get_bat_voltage(); + + calc_timeout(uptime); //always calculate timeout for each device, even if this function is disabled + check_timeout(); //also check timeout in order to set/reset timeout flags +} + + + +//End of "beep" +void TIM2_IRQHandler(void) +{ + timer2_stop(); + TIM2->SR &= ~TIM_SR_UIF; //clear gating timer int + + timer3_stop(); + led_board_off(); +} + + + +uint32_t get_uptime(void) +{ + return uptime; +} + + + +struct main_flags_struct *get_main_flags(void) +{ + return &main_flags; +} diff --git a/Firmware/CubeIDE/Code/src/menu.c b/Firmware/CubeIDE/Code/src/menu.c new file mode 100644 index 0000000..8591fd9 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/menu.c @@ -0,0 +1,3194 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: menu.c +*/ + +#include +#include +#include "stm32f10x.h" +#include "menu.h" +#include "buttons.h" +#include "ssd1306.h" +#include "main.h" +#include "service.h" +#include "settings.h" +#include "m24c64.h" +#include "ssd1306_bitmaps.h" +#include "gpio.h" +#include "adc.h" +#include "gps.h" +#include "points.h" +#include "lrns.h" +#include "si4463.h" +#include "timer.h" + + + +char *FW_VERSION = "1.0"; //firmware +char *HW_VERSION = "1"; //hardware + + + +#define ANOTHER_DEVICE_START_ROW (3) +#define ANOTHER_RADAR_DEVICE_START_ROW (2) + + +#define FREQ_CHANNEL_FIRST (1) +#define FREQ_CHANNEL_LAST (69) + +#define DEVICE_ID_FIRST_SYMBOL ('A') +#define DEVICE_ID_LAST_SYMBOL ('Z') + +#define POINT_NAME_FIRST_SYMBOL (' ') +#define POINT_NAME_LAST_SYMBOL ('~') + +#define TX_POWER_FIRST_OPTION (TX_POWER_10MILLIW_SETTING) +#define TX_POWER_LAST_OPTION (TX_POWER_100MILLIW_SETTING) + + +#define SEND_INTERVAL_FIRST_OPTION (SEND_INTERVAL_1S_SETTING) +#define SEND_INTERVAL_LAST_OPTION (SEND_INTERVAL_60S_SETTING) + + +#define MEMORY_SLOT_FIRST (1) +#define MEMORY_SLOT_LAST (MEMORY_SLOTS_TOTAL) + + +#define DEVICE_NUMBER_FIRST (1) +#define DEVICE_NUMBER_LAST (DEVICES_IN_GROUP) + +#define MEMORY_POINT_DEFAULT_NAME ("ALPHA") + + + +void toggle_alarm(void); + +uint8_t get_current_item(void); +uint8_t get_last_item(void); +void set_current_item(uint8_t new_value); +void reset_current_item_in_menu(uint8_t menu); + +void scroll_up(void); +void scroll_down(void); +void switch_forward(void); +void switch_backward(void); + +void draw_main(void); +void draw_devices(void); +void draw_settings(void); +void draw_info(void); +void draw_edit_settings(void); +void draw_set_dev_num(void); +void draw_set_dev_id(void); +void draw_set_freq_ch(void); +void draw_set_tx_pow(void); +void draw_set_send_intvl(void); +void draw_set_to_thr(void); +void draw_set_fnc_thr(void); +void draw_confirm_settings_save(void); +void draw_restore_defaults(void); +void draw_erase_all(void); +void draw_each_device(void); +void draw_each_device_submenu(void); +void draw_radar(void); +void draw_points(void); +void draw_each_point(void); +void draw_load_point(void); +void draw_delete_point(void); +void draw_delete_device(void); +void draw_save_device(void); +void draw_save_device_as(void); +void draw_saved_popup(void); + +void set_dev_num_up(void); +void set_dev_num_down(void); +void set_dev_num_ok(void); +void set_dev_num_esc(void); +void set_dev_id_up(void); +void set_dev_id_down(void); +void set_dev_id_ok(void); +void set_dev_id_ok_long(void); +void set_dev_id_esc(void); +void set_freq_ch_up(void); +void set_freq_ch_down(void); +void set_freq_ch_ok(void); +void set_freq_ch_esc(void); +void set_tx_pow_up(void); +void set_tx_pow_down(void); +void set_tx_pow_ok(void); +void set_tx_pow_esc(void); +void set_send_intvl_up(void); +void set_send_intvl_down(void); +void set_send_intvl_ok(void); +void set_send_intvl_esc(void); +void set_to_thr_up(void); +void set_to_thr_down(void); +void set_to_thr_ok(void); +void set_to_thr_esc(void); +void set_fnc_thr_up(void); +void set_fnc_thr_down(void); +void set_fnc_thr_ok(void); +void set_fnc_thr_esc(void); +void confirm_settings_save_ok(void); +void confirm_settings_save_esc(void); +void restore_defaults_ok(void); +void erase_all_ok(void); +void devices_ok(void); +void each_device_up(void); +void each_device_down(void); +void each_device_ok(void); +void radar_up(void); +void radar_down(void); +void radar_ok(void); +void points_up(void); +void points_down(void); +void points_ok(void); +void points_esc(void); +void load_point_up(void); +void load_point_down(void); +void load_point_ok(void); +void load_point_esc(void); +void delete_point_ok(void); +void delete_device_ok(void); +void save_device_up(void); +void save_device_down(void); +void save_device_ok(void); +void save_device_esc(void); +void save_device_as_up(void); +void save_device_as_down(void); +void save_device_as_ok(void); +void save_device_as_ok_long(void); +void save_device_as_esc(void); +void saved_popup_esc(void); + + + +//ALL MENUS HERE +enum +{ + //menu numbers start from 1, because 0 is used as "end marker" in menu structs + M_MAIN = 1, + M_DEVICES, + M_EACH_DEVICE, + M_EACH_DEVICE_SUBMENU, + M_DELETE_DEVICE, + M_SAVE_DEVICE, + M_SAVE_DEVICE_AS, + M_SAVED_POPUP, + M_RADAR, + M_POINTS, + M_EACH_POINT, + M_LOAD_POINT, + M_DELETE_POINT, + M_SETTINGS, + M_INFO, + M_EDIT_SETTINGS, + M_SET_DEV_NUM, + M_SET_DEV_ID, + M_SET_FREQ_CH, + M_SET_TX_POW, + M_SET_SEND_INTVL, + M_SET_TO_THR, + M_SET_FNC_THR, + M_CONFIRM_SETTINGS_SAVE, + M_RESTORE_DEFAULTS, + M_ERASE_ALL +}; + + + +//ALL MENU ITEMS HERE (for each menu separately) +//note: for all menus first item always has index of 0 +#define M_ALL_I_FIRST (0) + +//MAIN +enum +{ + M_MAIN_I_DEVICES = 0, + M_MAIN_I_RADAR, + M_MAIN_I_POINTS, + M_MAIN_I_SETTINGS, + M_MAIN_I_INFO, //last item + M_MAIN_I_LAST = M_MAIN_I_INFO //copy last item here +}; + + +//SETTINGS +enum +{ + M_SETTINGS_I_EDIT = 0, + M_SETTINGS_I_RESTORE, + M_SETTINGS_I_ERASE, + M_SETTINGS_I_LAST = M_SETTINGS_I_ERASE +}; + + + +//EDIT SETTINGS +enum +{ + M_EDIT_SETTINGS_I_DEV_NUM = 0, + M_EDIT_SETTINGS_I_DEV_ID, + M_EDIT_SETTINGS_I_FREQ_CH, + M_EDIT_SETTINGS_I_TX_POW, + M_EDIT_SETTINGS_I_SEND_INTVL, + M_EDIT_SETTINGS_I_TO_THR, + M_EDIT_SETTINGS_I_FNC_THR, + M_EDIT_SETTINGS_I_LAST = M_EDIT_SETTINGS_I_FNC_THR +}; + + + +//EACH POINT +enum +{ + M_EACH_POINT_I_LOAD = 0, + M_EACH_POINT_I_DELETE, + M_EACH_POINT_I_LAST = M_EACH_POINT_I_DELETE +}; + + + +//EACH DEVICE SUBMENU +enum +{ + M_EACH_DEVICE_SUBMENU_I_SAVE = 0, + M_EACH_DEVICE_SUBMENU_I_DELETE, + M_EACH_DEVICE_SUBMENU_I_LAST = M_EACH_DEVICE_SUBMENU_I_DELETE +}; + + + +//Only exclusive (non default) actions here, for example edit a variable in settings +const struct +{ + uint8_t current_menu; + uint8_t button_pressed; + void (*execute_function)(void); +} menu_exclusive_table[] = +{ +// Current Menu Button pressed Action (function name) + {M_DEVICES, BTN_OK, devices_ok}, + {M_EACH_DEVICE, BTN_UP, each_device_up}, + {M_EACH_DEVICE, BTN_DOWN, each_device_down}, + {M_EACH_DEVICE, BTN_OK, each_device_ok}, + {M_RADAR, BTN_UP, radar_up}, + {M_RADAR, BTN_DOWN, radar_down}, + {M_RADAR, BTN_OK, radar_ok}, + {M_SAVE_DEVICE, BTN_UP, save_device_up}, + {M_SAVE_DEVICE, BTN_DOWN, save_device_down}, + {M_SAVE_DEVICE, BTN_OK, save_device_ok}, + {M_SAVE_DEVICE, BTN_ESC, save_device_esc}, + {M_SAVE_DEVICE_AS, BTN_UP, save_device_as_up}, + {M_SAVE_DEVICE_AS, BTN_DOWN, save_device_as_down}, + {M_SAVE_DEVICE_AS, BTN_OK, save_device_as_ok}, + {M_SAVE_DEVICE_AS, BTN_OK_LONG, save_device_as_ok_long}, + {M_SAVE_DEVICE_AS, BTN_ESC, save_device_as_esc}, + {M_SAVED_POPUP, BTN_ESC, saved_popup_esc}, + {M_DELETE_DEVICE, BTN_OK, delete_device_ok}, + {M_POINTS, BTN_UP, points_up}, + {M_POINTS, BTN_DOWN, points_down}, + {M_POINTS, BTN_OK, points_ok}, + {M_POINTS, BTN_ESC, points_esc}, + {M_LOAD_POINT, BTN_UP, load_point_up}, + {M_LOAD_POINT, BTN_DOWN, load_point_down}, + {M_LOAD_POINT, BTN_OK, load_point_ok}, + {M_LOAD_POINT, BTN_ESC, load_point_esc}, + {M_DELETE_POINT, BTN_OK, delete_point_ok}, + {M_SET_DEV_NUM, BTN_UP, set_dev_num_up}, + {M_SET_DEV_NUM, BTN_DOWN, set_dev_num_down}, + {M_SET_DEV_NUM, BTN_OK, set_dev_num_ok}, + {M_SET_DEV_NUM, BTN_ESC, set_dev_num_esc}, + {M_SET_DEV_ID, BTN_UP, set_dev_id_up}, + {M_SET_DEV_ID, BTN_DOWN, set_dev_id_down}, + {M_SET_DEV_ID, BTN_OK, set_dev_id_ok}, + {M_SET_DEV_ID, BTN_OK_LONG, set_dev_id_ok_long}, + {M_SET_DEV_ID, BTN_ESC, set_dev_id_esc}, + {M_SET_FREQ_CH, BTN_UP, set_freq_ch_up}, + {M_SET_FREQ_CH, BTN_DOWN, set_freq_ch_down}, + {M_SET_FREQ_CH, BTN_OK, set_freq_ch_ok}, + {M_SET_FREQ_CH, BTN_ESC, set_freq_ch_esc}, + {M_SET_TX_POW, BTN_UP, set_tx_pow_up}, + {M_SET_TX_POW, BTN_DOWN, set_tx_pow_down}, + {M_SET_TX_POW, BTN_OK, set_tx_pow_ok}, + {M_SET_TX_POW, BTN_ESC, set_tx_pow_esc}, + {M_SET_SEND_INTVL, BTN_UP, set_send_intvl_up}, + {M_SET_SEND_INTVL, BTN_DOWN, set_send_intvl_down}, + {M_SET_SEND_INTVL, BTN_OK, set_send_intvl_ok}, + {M_SET_SEND_INTVL, BTN_ESC, set_send_intvl_esc}, + {M_SET_TO_THR, BTN_UP, set_to_thr_up}, + {M_SET_TO_THR, BTN_DOWN, set_to_thr_down}, + {M_SET_TO_THR, BTN_OK, set_to_thr_ok}, + {M_SET_TO_THR, BTN_ESC, set_to_thr_esc}, + {M_SET_FNC_THR, BTN_UP, set_fnc_thr_up}, + {M_SET_FNC_THR, BTN_DOWN, set_fnc_thr_down}, + {M_SET_FNC_THR, BTN_OK, set_fnc_thr_ok}, + {M_SET_FNC_THR, BTN_ESC, set_fnc_thr_esc}, + {M_CONFIRM_SETTINGS_SAVE, BTN_OK, confirm_settings_save_ok}, + {M_CONFIRM_SETTINGS_SAVE, BTN_ESC, confirm_settings_save_esc}, + {M_RESTORE_DEFAULTS, BTN_OK, restore_defaults_ok}, + {M_ERASE_ALL, BTN_OK, erase_all_ok}, + {0, 0, 0} //end marker +}; + + + +//Defaul behaviour (non exclusive) when OK button has been pressed (move forward) +const struct +{ + uint8_t current_menu; + uint8_t current_item; + uint8_t next_menu; +} menu_forward_table[] = +{ +// Current Menu Current Item Next Menu + {M_MAIN, M_MAIN_I_DEVICES, M_DEVICES}, + {M_MAIN, M_MAIN_I_RADAR, M_RADAR}, + {M_MAIN, M_MAIN_I_POINTS, M_POINTS}, + {M_MAIN, M_MAIN_I_SETTINGS, M_SETTINGS}, + {M_MAIN, M_MAIN_I_INFO, M_INFO}, + {M_EACH_DEVICE_SUBMENU, M_EACH_DEVICE_SUBMENU_I_SAVE, M_SAVE_DEVICE}, + {M_EACH_DEVICE_SUBMENU, M_EACH_DEVICE_SUBMENU_I_DELETE, M_DELETE_DEVICE}, + {M_EACH_POINT, M_EACH_POINT_I_LOAD, M_LOAD_POINT}, + {M_EACH_POINT, M_EACH_POINT_I_DELETE, M_DELETE_POINT}, + {M_SETTINGS, M_SETTINGS_I_EDIT, M_EDIT_SETTINGS}, + {M_SETTINGS, M_SETTINGS_I_RESTORE, M_RESTORE_DEFAULTS}, + {M_SETTINGS, M_SETTINGS_I_ERASE, M_ERASE_ALL}, + {M_EDIT_SETTINGS, M_EDIT_SETTINGS_I_DEV_NUM, M_SET_DEV_NUM}, + {M_EDIT_SETTINGS, M_EDIT_SETTINGS_I_DEV_ID, M_SET_DEV_ID}, + {M_EDIT_SETTINGS, M_EDIT_SETTINGS_I_FREQ_CH, M_SET_FREQ_CH}, + {M_EDIT_SETTINGS, M_EDIT_SETTINGS_I_TX_POW, M_SET_TX_POW}, + {M_EDIT_SETTINGS, M_EDIT_SETTINGS_I_SEND_INTVL, M_SET_SEND_INTVL}, + {M_EDIT_SETTINGS, M_EDIT_SETTINGS_I_TO_THR, M_SET_TO_THR}, + {M_EDIT_SETTINGS, M_EDIT_SETTINGS_I_FNC_THR, M_SET_FNC_THR}, + {0, 0, 0} //end marker +}; + + + +//Defaul behaviour (non exclusive) when ESC button has been pressed (move backward) +const struct +{ + uint8_t current_menu; + uint8_t next_menu; +} menu_backward_table[] = +{ +// Current Menu Next Menu + {M_DEVICES, M_MAIN}, + {M_EACH_DEVICE, M_DEVICES}, + {M_EACH_DEVICE_SUBMENU, M_EACH_DEVICE}, + {M_SAVE_DEVICE, M_EACH_DEVICE_SUBMENU}, + {M_DELETE_DEVICE, M_EACH_DEVICE_SUBMENU}, + {M_RADAR, M_MAIN}, + {M_EACH_POINT, M_POINTS}, + {M_DELETE_POINT, M_EACH_POINT}, + {M_SETTINGS, M_MAIN}, + {M_INFO, M_MAIN}, + {M_EDIT_SETTINGS, M_CONFIRM_SETTINGS_SAVE}, + {M_RESTORE_DEFAULTS, M_SETTINGS}, + {M_ERASE_ALL, M_SETTINGS}, + {0, 0} //end marker +}; + + + +//Struct with list of menus and real-time values of current item in current menu. Last Item is needed for scroll function +//note: if current menu has no items (like INFO menu) no need to put it in structure below, because item functions (get, get last, set) automatically return 0 (which is zero item) +struct +{ + const uint8_t curent_menu; + uint8_t cur_item; + const uint8_t last_item; +} item_table[] = +{ +// Current Menu Current Item Last Item in Current Menu + {M_MAIN, M_ALL_I_FIRST, M_MAIN_I_LAST}, + {M_EACH_DEVICE_SUBMENU, M_ALL_I_FIRST, M_EACH_DEVICE_SUBMENU_I_LAST}, + {M_EACH_POINT, M_ALL_I_FIRST, M_EACH_POINT_I_LAST}, + {M_SETTINGS, M_ALL_I_FIRST, M_SETTINGS_I_LAST}, + {M_EDIT_SETTINGS, M_ALL_I_FIRST, M_EDIT_SETTINGS_I_LAST}, + {0, 0, 0} //end marker +}; + + + +//List of menus with appropriate functions to draw it (show on screen) +const struct +{ + uint8_t current; + void (*action)(void); +} menu_draw_table[] = +{ +// Current Menu Draw Function + {M_MAIN, draw_main}, + {M_DEVICES, draw_devices}, + {M_EACH_DEVICE, draw_each_device}, + {M_EACH_DEVICE_SUBMENU, draw_each_device_submenu}, + {M_SAVE_DEVICE, draw_save_device}, + {M_SAVE_DEVICE_AS, draw_save_device_as}, + {M_SAVED_POPUP, draw_saved_popup}, + {M_DELETE_DEVICE, draw_delete_device}, + {M_RADAR, draw_radar}, + {M_POINTS, draw_points}, + {M_EACH_POINT, draw_each_point}, + {M_LOAD_POINT, draw_load_point}, + {M_DELETE_POINT, draw_delete_point}, + {M_SETTINGS, draw_settings}, + {M_INFO, draw_info}, + {M_EDIT_SETTINGS, draw_edit_settings}, + {M_SET_DEV_NUM, draw_set_dev_num}, + {M_SET_DEV_ID, draw_set_dev_id}, + {M_SET_FREQ_CH, draw_set_freq_ch}, + {M_SET_TX_POW, draw_set_tx_pow}, + {M_SET_SEND_INTVL, draw_set_send_intvl}, + {M_SET_TO_THR, draw_set_to_thr}, + {M_SET_FNC_THR, draw_set_fnc_thr}, + {M_CONFIRM_SETTINGS_SAVE, draw_confirm_settings_save}, + {M_RESTORE_DEFAULTS, draw_restore_defaults}, + {M_ERASE_ALL, draw_erase_all}, + {0, 0} //end marker +}; + + + +struct settings_struct *p_settings; +struct settings_struct settings_copy; + +struct gps_raw_struct *p_gps_raw; +struct gps_num_struct *p_gps_num; +struct gps_air_struct **pp_gps_air; +struct gps_rel_struct **pp_gps_rel; +struct dev_aux_struct **pp_dev_aux; +struct memory_slot_struct **pp_memory_slot; + +uint8_t *p_send_interval_values; +uint8_t *p_get_tx_power_values; + +uint8_t current_menu; //Actually Current Menu value (real-time) +char buf[21]; //temporary char buffer for screen text fragments +float tmpf; //temporary float variable +uint32_t tmpui32; //temporary uint32 +int16_t tmpi16; //temporary int16 +uint8_t flag_settings_changed = 0; //is settings changed? +uint8_t device_id_current_symbol = 0; //current editing symbol in device_id[] + +const char point_to_save_default_name[MEMORY_POINT_NAME_LENGTH + 1] = MEMORY_POINT_DEFAULT_NAME; +char point_to_save_name[MEMORY_POINT_NAME_LENGTH + 1]; +uint8_t point_name_current_symbol = 0; + +uint8_t current_each_device = DEVICE_NUMBER_FIRST; //current device number in EACH DEVICE menu +uint8_t current_radar_device = 0; //current device number in RADAR menu, set to 0, see draw_radar() +uint8_t current_device_to_load = 0; +uint8_t current_slot_to_load = MEMORY_SLOT_FIRST; //currently selected point slot in points menu +uint8_t current_slot_to_save = 0; +uint8_t point_to_save_list[MEMORY_SLOTS_TOTAL + 1]; +uint8_t device_to_load_list[DEVICES_IN_GROUP + 1]; +uint8_t radar_list[DEVICES_IN_GROUP + 1]; //list of devices in radar menu, 5 devices total (because of except me); radar_list[device_number] = item; items start from 0 +uint8_t radar_list_hide[DEVICES_IN_GROUP + 1]; //if == 1 then hide device cross on the radar screen +uint8_t device_number; //this device number + +const uint8_t sx0 = 24; //radar center pixel on screen (i.e. my position) +const uint8_t sy0 = 31; +const uint8_t r_circ_dots = 20; //screen circle radius in dots + +uint8_t custom_exclam_mark[2] = {0, 0x5F}; + + + +//Init and show MAIN menu +void init_menu(void) +{ + p_gps_raw = get_gps_raw(); + p_gps_num = get_gps_num(); + pp_gps_air = get_gps_air(); + pp_gps_rel = get_gps_rel(); + pp_dev_aux = get_dev_aux(); + + pp_memory_slot = get_memory_slot(); + + p_settings = get_settings(); + settings_copy = *p_settings; + + device_number = p_settings->device_number; + + p_send_interval_values = get_send_interval_values(); + p_get_tx_power_values = get_tx_power_values(); + + //init variables + current_each_device = device_number; //set me current + current_menu = M_MAIN; + set_current_item(M_MAIN_I_DEVICES); +} + + + +//Check for buttons and change menu if needed +void change_menu(uint8_t button_code) +{ + if (button_code) + { + + //search for exclusive operation for this case + for (uint8_t i = 0; menu_exclusive_table[i].current_menu; i++) //until end marker + { + if (current_menu == menu_exclusive_table[i].current_menu && + button_code == menu_exclusive_table[i].button_pressed) + { + menu_exclusive_table[i].execute_function(); + return; //exit + } + } + + //well, there is no exclusive operations for that case, perform default action + switch (button_code) + { + case BTN_UP: + scroll_up(); + break; + + case BTN_DOWN: + scroll_down(); + break; + + case BTN_OK: + switch_forward(); + break; + + case BTN_ESC: + switch_backward(); + break; + + case BTN_PWR_LONG: + toggle_alarm(); + break; + + case BTN_ESC_LONG: + toggle_mute(); + draw_current_menu(); + break; + } + + } +} + + + +//Switch alarm status +void toggle_alarm(void) +{ + if (get_device_flags(device_number, FLAGS_ALARM) == FLAG_ALARM_OFF) + { + set_device_flags(FLAGS_ALARM, FLAG_ALARM_ON); + } + else + { + set_device_flags(FLAGS_ALARM, FLAG_ALARM_OFF); + } + + check_alarms(); //immediately update alarm indication + draw_current_menu(); +} + + + +//Scroll current menu Up +void scroll_up(void) +{ + uint8_t current = get_current_item(); + uint8_t last = get_last_item(); + + if (current == M_ALL_I_FIRST) + { + set_current_item(last); + } + else + { + set_current_item(current - 1); + } + + draw_current_menu(); +} + + + +//Scroll current menu Down +void scroll_down(void) +{ + uint8_t current = get_current_item(); + uint8_t last = get_last_item(); + + if (current == last) + { + set_current_item(M_ALL_I_FIRST); + } + else + { + set_current_item(current + 1); + } + + draw_current_menu(); +} + + + +//Switch menu forward by default +void switch_forward(void) +{ + for (uint8_t i = 0; menu_forward_table[i].current_menu; i++) + { + if (current_menu == menu_forward_table[i].current_menu && + get_current_item() == menu_forward_table[i].current_item) + { + current_menu = menu_forward_table[i].next_menu; + break; + } + } + draw_current_menu(); +} + + + +//Switch menu backward by default +void switch_backward(void) +{ + for (uint8_t i = 0; menu_backward_table[i].current_menu; i++) + { + if (current_menu == menu_backward_table[i].current_menu) + { + set_current_item(M_ALL_I_FIRST); //reset current item before exit + current_menu = menu_backward_table[i].next_menu; + break; + } + } + draw_current_menu(); +} + + + +//Get currently selected item in current menu +uint8_t get_current_item(void) +{ + for (uint8_t i = 0; item_table[i].curent_menu; i++) + { + if (current_menu == item_table[i].curent_menu) + { + return item_table[i].cur_item; + } + } + return 0; //automatically return 0 if item not found in item_table[] +} + + + +//Get last item in current menu +uint8_t get_last_item(void) +{ + for (uint8_t i = 0; item_table[i].curent_menu; i++) + { + if (current_menu == item_table[i].curent_menu) + { + return item_table[i].last_item; + } + } + return 0; //automatically return 0 if item not found in item_table[] +} + + + +//Set item to be current in current menu +void set_current_item(uint8_t new_value) +{ + for (uint8_t i = 0; item_table[i].curent_menu; i++) + { + if (current_menu == item_table[i].curent_menu) + { + item_table[i].cur_item = new_value; + break; + } + } +} + + + +//Reset item in any menu +void reset_current_item_in_menu(uint8_t menu) +{ + for (uint8_t i = 0; item_table[i].curent_menu; i++) + { + if (menu == item_table[i].curent_menu) + { + item_table[i].cur_item = M_ALL_I_FIRST; + break; + } + } +} + + + +//Draw current menu (after scroll) +void draw_current_menu(void) +{ + for (uint8_t i = 0; menu_draw_table[i].current; i++) + { + if (current_menu == menu_draw_table[i].current) + { + menu_draw_table[i].action(); + break; + } + } +} + + + +//MAIN +void draw_main(void) +{ + #define MAIN_ROW (2) + #define MAIN_COL (1) + + ssd1306_clear(); + ssd1306_print(0, MAIN_COL, "MENU", 0); + ssd1306_print(MAIN_ROW, MAIN_COL, "Devices", 0); + ssd1306_print(MAIN_ROW + 1, MAIN_COL, "Radar", 0); + ssd1306_print(MAIN_ROW + 2, MAIN_COL, "Points", 0); + ssd1306_print(MAIN_ROW + 3, MAIN_COL, "Settings", 0); + ssd1306_print(MAIN_ROW + 4, MAIN_COL, "Info", 0); + ssd1306_print(MAIN_ROW + get_current_item(), MAIN_COL - 1, ">", 0); + + ssd1306_char_pos(0, 20, SYMB_NOTE, 0); + if (get_mute_flag() == 1) + { + ssd1306_char_pos(0, 19, '!', 0); + } + + ssd1306_update(); +} + + + +//DEVICES +void draw_devices(void) +{ + ssd1306_clear(); + ssd1306_bitmap(&devices_blank[0]); + + //TRX + if (get_main_flags()->gps_sync) + { + ssd1306_char_pos(0, 18, SYMB_ARROW_UP, 0); + ssd1306_char_pos(0, 19, SYMB_ARROW_DOWN, 0); + } + + //Sattelites + if (p_gps_raw->time[0] == 0) //if no time received then no sattelites at all + { + ssd1306_char_pos(0, 20, SYMB_NO_SATT, 0); + } + else + { + if (p_gps_num->mode == GPS_POSITION_3DFIX && p_gps_num->status == GPS_DATA_VALID) + { + ssd1306_char_pos(0, 20, SYMB_SATT_3D, 0); //3D when data is valid + } + else if (p_gps_num->mode == GPS_POSITION_2DFIX && p_gps_num->status == GPS_DATA_VALID) + { + ssd1306_char_pos(0, 20, SYMB_SATT_2D, 0); //2D when data is valid + } + else + { + ssd1306_char_pos(0, 20, SYMB_SATT_1D, 0); //if not 2D or 3D then only time is avaliable + } + } + + uint8_t icon_col = LCD_LAST_COL; + + //Battery + switch (get_device_flags(device_number, FLAGS_BATTERY)) + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_4OF4, 0); + break; + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_3OF4, 0); + break; + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_2OF4, 0); + break; + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_1OF4, 0); + break; + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_0OF4, 0); + break; + } + + + + //Timeout + if (pp_dev_aux[device_number]->timeout_flag) + { + ssd1306_char_pos(1, icon_col--, SYMB_TIMEOUT, 0); + } + + + + //Alarm + if (get_device_flags(device_number, FLAGS_ALARM) == FLAG_ALARM_ON) + { + ssd1306_char_pos(1, icon_col--, SYMB_ALARM, 0); + } + + + + //Devices + uint8_t another_dev_row = ANOTHER_DEVICE_START_ROW; //start to print another devices from row 3 + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + if (dev == device_number) //if me + { + //Number + itoa32(dev, &buf[0]); + ssd1306_print(1, 0, &buf[0], 0); + + //ID + ssd1306_char_pos(1, 2, p_settings->device_id[0], 0); + ssd1306_char_pos(1, 3, p_settings->device_id[1], 0); + + //Speed + if (p_gps_num->speed < 10.0) //if speed is small show x.x format + { + ftoa32(p_gps_num->speed, 1, &buf[0]); + ssd1306_print_viceversa(1, 7, &buf[0], 0); + } + else //else show int format + { + itoa32(pp_gps_air[dev]->speed, &buf[0]); + ssd1306_print_viceversa(1, 7, &buf[0], 0); + } + + //Course + itoa32(pp_gps_air[dev]->course.as_integer, &buf[0]); + ssd1306_print_viceversa(1, 11, &buf[0], 0); + + //Altitude + itoa32(pp_gps_air[dev]->altitude.as_integer, &buf[0]); + ssd1306_print_viceversa(1, 16, &buf[0], 0); + } + else + { + if (pp_dev_aux[dev]->exist_flag == 1) //if not me & exist + { + //Number + itoa32(dev, &buf[0]); + ssd1306_print(another_dev_row, 0, &buf[0], 0); + + //ID + ssd1306_char_pos(another_dev_row, 2, pp_gps_air[dev]->device_id[0], 0); + ssd1306_char_pos(another_dev_row, 3, pp_gps_air[dev]->device_id[1], 0); + + //Distance + if (pp_gps_rel[dev]->distance < 1000) //1-999 m + { + itoa32(pp_gps_rel[dev]->distance, &buf[0]); + ssd1306_print_viceversa(another_dev_row, 7, &buf[0], 0); + } + else if (pp_gps_rel[dev]->distance < 10000) //1.0-9.9 km + { + tmpf = pp_gps_rel[dev]->distance / 1000.0; + ftoa32(tmpf, 1, &buf[0]); + ssd1306_print_viceversa(another_dev_row, 7, &buf[0], 0); + } + else if (pp_gps_rel[dev]->distance < 100000) //10.-99. km + { + tmpf = pp_gps_rel[dev]->distance / 1000.0; + itoa32((uint32_t)tmpf, &buf[0]); + ssd1306_print_viceversa(another_dev_row, 6, &buf[0], 0); + ssd1306_char_pos(another_dev_row, 7, '.', 0); + } + else // >100 km + { + ssd1306_print(another_dev_row, 5, "...", 0); + } + + //Heading + itoa32(pp_gps_rel[dev]->heading, &buf[0]); + ssd1306_print_viceversa(another_dev_row, 11, &buf[0], 0); + + //Delta Altitude + tmpi16 = pp_gps_rel[dev]->altitude_diff; + if (tmpi16 < 0) + { + tmpi16 *= -1; + } + + if (tmpi16 < 1000) //1-999 m + { + itoa32(pp_gps_rel[dev]->altitude_diff, &buf[0]); + ssd1306_print_viceversa(another_dev_row, 16, &buf[0], 0); + } + else if (tmpi16 < 10000) //1.0-9.9 km + { + tmpf = pp_gps_rel[dev]->altitude_diff / 1000.0; + ftoa32(tmpf, 1, &buf[0]); + ssd1306_print_viceversa(another_dev_row, 16, &buf[0], 0); + } + else //10.-99. km + { + tmpf = pp_gps_rel[dev]->altitude_diff / 1000.0; + itoa32((int32_t)tmpf, &buf[0]); + ssd1306_char_pos(another_dev_row, 16, '.', 0); + ssd1306_print_viceversa(another_dev_row, 15, &buf[0], 0); + } + + if (pp_gps_rel[dev]->altitude_diff > 0) + { + ssd1306_char('+', 0); + } + + + + uint8_t icon_col = LCD_LAST_COL; + + //Battery + if (pp_dev_aux[dev]->memory_point_flag == 0) //dont show battery icon for memory points + { + switch (get_device_flags(dev, FLAGS_BATTERY)) + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_4OF4, 0); + break; + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_3OF4, 0); + break; + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_2OF4, 0); + break; + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_1OF4, 0); + break; + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_0OF4, 0); + break; + } + } + + + //Timeout + if (pp_dev_aux[dev]->memory_point_flag == 0) //dont show timeout icon for memory points + { + if (pp_dev_aux[dev]->timeout_flag) + { + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_TIMEOUT, 0); + } + } + + + //Fence + if (pp_dev_aux[dev]->fence_flag) + { + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_FENCE, 0); + } + + + //Alarm + if (pp_dev_aux[dev]->memory_point_flag == 0) //dont show alarm icon for memory points + { + if (get_device_flags(dev, FLAGS_ALARM) == FLAG_ALARM_ON) + { + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_ALARM, 0); + } + } + + + another_dev_row++; //set next row + } + } + } + + ssd1306_update(); +} + + + +//EACH DEVICE +void draw_each_device(void) +{ + ssd1306_clear(); + + //My status row + uint8_t icon_col = LCD_LAST_COL; + + //Battery + switch (get_device_flags(device_number, FLAGS_BATTERY)) + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_4OF4, 0); + break; + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_3OF4, 0); + break; + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_2OF4, 0); + break; + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_1OF4, 0); + break; + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_0OF4, 0); + break; + } + + + + //Sattelites + if (p_gps_raw->time[0] == 0) //if no time received then no sattelites at all + { + ssd1306_char_pos(0, icon_col--, SYMB_NO_SATT, 0); + } + else + { + if (p_gps_num->mode == GPS_POSITION_3DFIX && p_gps_num->status == GPS_DATA_VALID) + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_3D, 0); //3D when data is valid + } + else if (p_gps_num->mode == GPS_POSITION_2DFIX && p_gps_num->status == GPS_DATA_VALID) + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_2D, 0); //2D when data is valid + } + else + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_1D, 0); //if not 2D or 3D then only time is avaliable + } + } + + + //TRX + if (get_main_flags()->gps_sync) + { + ssd1306_char_pos(0, icon_col--, SYMB_ARROW_DOWN, 0); + ssd1306_char_pos(0, icon_col--, SYMB_ARROW_UP, 0); + } + + + //Timeout + if (pp_dev_aux[device_number]->timeout_flag) + { + ssd1306_char_pos(0, icon_col--, SYMB_TIMEOUT, 0); + } + + + //Alarm + if (get_device_flags(device_number, FLAGS_ALARM) == FLAG_ALARM_ON) + { + ssd1306_char_pos(0, icon_col--, SYMB_ALARM, 0); + } + + + + if (current_each_device == device_number) //if me + { + ssd1306_print(0, 0, "#", 0); + itoa32(current_each_device, &buf[0]); + ssd1306_print(0, 1, &buf[0], 0); + + ssd1306_char_pos(0, 3, p_settings->device_id[0], 0); + ssd1306_char_pos(0, 4, p_settings->device_id[1], 0); + + ssd1306_print(0, 6, "(me)", 0); + + ssd1306_char_pos(1, 0, p_gps_raw->date[0], 0); + ssd1306_char_pos(1, 1, p_gps_raw->date[1], 0); + ssd1306_print(1, 2, ".", 0); + + ssd1306_char_pos(1, 3, p_gps_raw->date[2], 0); + ssd1306_char_pos(1, 4, p_gps_raw->date[3], 0); + ssd1306_print(1, 5, ".", 0); + + ssd1306_char_pos(1, 6, p_gps_raw->date[4], 0); + ssd1306_char_pos(1, 7, p_gps_raw->date[5], 0); + + ssd1306_char_pos(1, 9, p_gps_raw->time[0], 0); + ssd1306_char_pos(1, 10, p_gps_raw->time[1], 0); + ssd1306_print(1, 11, ":", 0); + + ssd1306_char_pos(1, 12, p_gps_raw->time[2], 0); + ssd1306_char_pos(1, 13, p_gps_raw->time[3], 0); + ssd1306_print(1, 14, ":", 0); + + ssd1306_char_pos(1, 15, p_gps_raw->time[4], 0); + ssd1306_char_pos(1, 16, p_gps_raw->time[5], 0); + + ssd1306_print(1, 18, "GMT", 0); + + ssd1306_print(2, 0, "LAT", 0); + ftoa32(p_gps_num->latitude.in_deg, 6, &buf[0]); + ssd1306_print_viceversa(2, 14, &buf[0], 0); + if (p_gps_num->latitude.in_deg >= 0) + { + ssd1306_char('+', 0); + ssd1306_print(2, 16, "(N)", 0); + } + else + { + ssd1306_print(2, 16, "(S)", 0); + } + + ssd1306_print(3, 0, "LON", 0); + ftoa32(p_gps_num->longitude.in_deg, 6, &buf[0]); + ssd1306_print_viceversa(3, 14, &buf[0], 0); + if (p_gps_num->longitude.in_deg >= 0) + { + ssd1306_char('+', 0); + ssd1306_print(3, 16, "(E)", 0); + } + else + { + ssd1306_print(3, 16, "(W)", 0); + } + + ssd1306_print(4, 0, "ALT", 0); + itoa32(p_gps_num->altitude, &buf[0]); + ssd1306_print(4, 4, &buf[0], 0); + ssd1306_print_next("m", 0); + + ssd1306_print(4, 11, "FIX", 0); + if (p_gps_num->status == GPS_DATA_VALID) + { + ssd1306_print(4, 15, "A/", 0); + } + else + { + ssd1306_print(4, 15, "V/", 0); + } + + if (p_gps_num->mode == GPS_POSITION_2DFIX) + { + ssd1306_print(4, 17, "2D", 0); + } + else if (p_gps_num->mode == GPS_POSITION_3DFIX) + { + ssd1306_print(4, 17, "3D", 0); + } + else + { + ssd1306_print(4, 17, "NO", 0); + } + + ssd1306_print(5, 0, "COG", 0); + itoa32(p_gps_num->course, &buf[0]); + ssd1306_print(5, 4, &buf[0], 0); + ssd1306_char(SYMB_DEGREE, 0); + + ssd1306_print(5, 11, "DOP", 0); + ftoa32(p_gps_num->pdop, 2, &buf[0]); + ssd1306_print(5, 15, &buf[0], 0); + + ssd1306_print(6, 0, "SOG", 0); + if (p_gps_num->speed < 10.0) //if speed is small show x.x format + { + ftoa32(p_gps_num->speed, 1, &buf[0]); + ssd1306_print(6, 4, &buf[0], 0); + } + else //else show int format + { + itoa32((int16_t)p_gps_num->speed, &buf[0]); + ssd1306_print(6, 4, &buf[0], 0); + } + ssd1306_print_next("kph", 0); + + ssd1306_print(6, 11, "SAT", 0); + itoa32(p_gps_num->sat_used, &buf[0]); + ssd1306_print(6, 15, &buf[0], 0); + ssd1306_print_next("/", 0); + itoa32(p_gps_num->sat_view, &buf[0]); + ssd1306_print_next(&buf[0], 0); + + if (pp_dev_aux[device_number]->timeout_flag == 1) + { + ssd1306_print(7, 0, "TOC", 1); + } + else + { + ssd1306_print(7, 0, "TOC", 0); + } + convert_timeout(pp_dev_aux[device_number]->timeout, &buf[0]); + ssd1306_print(7, 4, &buf[0], 0); + + ssd1306_print(7, 11, "BAT", 0); + ftoa32(get_bat_voltage(), 2, &buf[0]); + ssd1306_print(7, 15, &buf[0], 0); + ssd1306_char('V', 0); + } + else //if not me + { + ssd1306_print(0, 1, "#", 0); + itoa32(current_each_device, &buf[0]); + ssd1306_print(0, 2, &buf[0], 0); + + ssd1306_char_pos(0, 4, pp_gps_air[current_each_device]->device_id[0], 0); + ssd1306_char_pos(0, 5, pp_gps_air[current_each_device]->device_id[1], 0); + + if (pp_dev_aux[current_each_device]->memory_point_flag == 1) //print memory point name + { + ssd1306_print(0, 7, pp_dev_aux[current_each_device]->point_name, 0); + } + + ssd1306_print(1, 0, "LAT", 0); + ftoa32(pp_gps_air[current_each_device]->latitude.as_float, 6, &buf[0]); + ssd1306_print_viceversa(1, 14, &buf[0], 0); + if (pp_gps_air[current_each_device]->latitude.as_float >= 0) + { + ssd1306_char('+', 0); + ssd1306_print(1, 16, "(N)", 0); + } + else + { + ssd1306_print(1, 16, "(S)", 0); + } + + ssd1306_print(2, 0, "LON", 0); + ftoa32(pp_gps_air[current_each_device]->longitude.as_float, 6, &buf[0]); + ssd1306_print_viceversa(2, 14, &buf[0], 0); + if (pp_gps_air[current_each_device]->longitude.as_float >= 0) + { + ssd1306_char('+', 0); + ssd1306_print(2, 16, "(E)", 0); + } + else + { + ssd1306_print(2, 16, "(W)", 0); + } + + ssd1306_print(3, 0, "ALT", 0); + itoa32(pp_gps_air[current_each_device]->altitude.as_integer, &buf[0]); + ssd1306_print(3, 4, &buf[0], 0); + ssd1306_print_next("m", 0); + + + ssd1306_print(3, 11, "DLT", 0); + tmpi16 = pp_gps_rel[current_each_device]->altitude_diff; + + if (tmpi16 < 0) + { + tmpi16 *= -1; + ssd1306_char_pos(3, 14, ' ', 0); + } + else if (tmpi16 > 0) + { + ssd1306_char_pos(3, 15, '+', 0); + } + else + { + ssd1306_char_pos(3, 14, ' ', 0); + } + + if (tmpi16 < 10000) //0-9999 m + { + itoa32(pp_gps_rel[current_each_device]->altitude_diff, &buf[0]); + ssd1306_print_next(&buf[0], 0); + ssd1306_print_next("m", 0); + } + else // >=10000 km + { + tmpf = pp_gps_rel[current_each_device]->altitude_diff / 1000.0; + ftoa32(tmpf, 1, &buf[0]); + ssd1306_print_next(&buf[0], 0); + ssd1306_print_next("k", 0); + } + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + { + ssd1306_print(4, 0, "COG", 0); + itoa32(pp_gps_air[current_each_device]->course.as_integer, &buf[0]); + ssd1306_print(4, 4, &buf[0], 0); + ssd1306_char(SYMB_DEGREE, 0); + } + + ssd1306_print(4, 11, "BRG", 0); + itoa32(pp_gps_rel[current_each_device]->heading, &buf[0]); + ssd1306_print(4, 15, &buf[0], 0); + ssd1306_char(SYMB_DEGREE, 0); + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + { + ssd1306_print(5, 0, "SOG", 0); + itoa32(pp_gps_air[current_each_device]->speed, &buf[0]); + ssd1306_print(5, 4, &buf[0], 0); + ssd1306_print_next("kph", 0); + } + + + ssd1306_print(5, 11, "DST", 0); + + if (pp_gps_rel[current_each_device]->distance < 100000) // 0-99999 m + { + itoa32(pp_gps_rel[current_each_device]->distance, &buf[0]); + ssd1306_print(5, 15, &buf[0], 0); + ssd1306_print_next("m", 0); + } + else if (pp_gps_rel[current_each_device]->distance < 1000000) // 100-999.9 km + { + tmpf = pp_gps_rel[current_each_device]->distance / 1000.0; + ftoa32(tmpf, 1, &buf[0]); + ssd1306_print(5, 15, &buf[0], 0); + ssd1306_print_next("k", 0); + } + else // 1000-... km + { + tmpf = pp_gps_rel[current_each_device]->distance / 1000000.0; + ftoa32(tmpf, 1, &buf[0]); + ssd1306_print(5, 15, &buf[0], 0); + ssd1306_print_next("M", 0); + } + + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + { + ssd1306_print(6, 0, "FIX", 0); + if (get_device_flags(current_each_device, FLAGS_GPS_FIX) == FLAG_GPS_FIX_3D) + { + ssd1306_print(6, 4, "3D/", 0); + } + else + { + ssd1306_print(6, 4, "2D/", 0); + } + + if (get_device_flags(current_each_device, FLAGS_PDOP) == FLAG_PDOP_GOOD) + { + ssd1306_print(6, 7, "HI", 0); + } + else + { + ssd1306_print(6, 7, "LO", 0); + } + } + + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + { + ssd1306_print(6, 11, "BAT", 0); + switch (get_device_flags(current_each_device, FLAGS_BATTERY)) + { + case FLAG_BATTERY_75_TO_100: + ssd1306_print(6, 15, "4/4", 0); + break; + + case FLAG_BATTERY_50_TO_75: + ssd1306_print(6, 15, "3/4", 0); + break; + + case FLAG_BATTERY_25_TO_50: + ssd1306_print(6, 15, "2/4", 0); + break; + + case FLAG_BATTERY_10_TO_25: + ssd1306_print(6, 15, "1/4", 0); + break; + + case FLAG_BATTERY_0_TO_10: + ssd1306_print(6, 15, "0/4", 0); + break; + } + } + + if (pp_dev_aux[current_each_device]->timeout_flag == 1) + { + ssd1306_print(7, 0, "TOC", 1); + } + else + { + ssd1306_print(7, 0, "TOC", 0); + } + convert_timeout(pp_dev_aux[current_each_device]->timeout, &buf[0]); + ssd1306_print(7, 4, &buf[0], 0); + + + + if (pp_dev_aux[current_each_device]->fence_flag) + { + ssd1306_print(7, 11, "FNC", 1); //print inverted + } + else + { + ssd1306_print(7, 11, "FNC", 0); + } + + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + { + if (get_device_flags(current_each_device, FLAGS_ALARM) == FLAG_ALARM_ON) + { + ssd1306_print(7, 15, "ALR", 1); //print inverted + } + else + { + ssd1306_print(7, 15, "ALR", 0); + } + } + + + + } + ssd1306_update(); +} + + + +void draw_each_device_submenu(void) +{ + #define EACH_DEV_SM_ROW (2) + #define EACH_DEV_SM_COL (1) + + ssd1306_clear(); + + ssd1306_print(0, EACH_DEV_SM_COL, "DEVICE", 0); + + ssd1306_print(0, EACH_DEV_SM_COL + 7, "#", 0); + itoa32(current_each_device, &buf[0]); + ssd1306_print(0, EACH_DEV_SM_COL + 8, &buf[0], 0); + + ssd1306_char_pos(0, EACH_DEV_SM_COL + 10, pp_gps_air[current_each_device]->device_id[0], 0); + ssd1306_char_pos(0, EACH_DEV_SM_COL + 11, pp_gps_air[current_each_device]->device_id[1], 0); + + ssd1306_print(EACH_DEV_SM_ROW, EACH_DEV_SM_COL, "Save", 0); + ssd1306_print(EACH_DEV_SM_ROW + 1, EACH_DEV_SM_COL, "Delete", 0); + ssd1306_print(EACH_DEV_SM_ROW + get_current_item(), EACH_DEV_SM_COL - 1, ">", 0); + + ssd1306_update(); +} + + + +void draw_delete_device(void) +{ + ssd1306_clear(); + ssd1306_print(0, 1, "Delete device", 0); + + ssd1306_print(0, 15, "#", 0); + itoa32(current_each_device, &buf[0]); + ssd1306_print(0, 16, &buf[0], 0); + + ssd1306_char_pos(0, 18, pp_gps_air[current_each_device]->device_id[0], 0); + ssd1306_char_pos(0, 19, pp_gps_air[current_each_device]->device_id[1], 0); + + ssd1306_print_next("?", 0); + + + if (current_each_device == device_number) + { + ssd1306_print(3, 1, "Can't del yourself", 0); + } + else + { + ssd1306_print(3, 1, "OK - delete", 0); + } + + ssd1306_print(4, 1, "ESC - cancel", 0); + + ssd1306_update(); +} + + + +void delete_device_ok(void) +{ + if (current_each_device != device_number) + { + pp_dev_aux[current_each_device]->exist_flag = 0; //delete device just by resetting exist flag + current_each_device = device_number; //also reset the current device + current_radar_device = 0; //reset current dev in radar menu + radar_list_hide[current_each_device] = 0;//reset hide flag + + reset_current_item_in_menu(M_EACH_DEVICE_SUBMENU); + current_menu = M_DEVICES; + draw_current_menu(); + } +} + + + +void draw_save_device(void) +{ + #define SAVE_DEVICE_ROW (2) + #define SAVE_DEVICE_COL (1) + + memcpy(point_to_save_name, point_to_save_default_name, sizeof(point_to_save_default_name)); //init default name here + + ssd1306_clear(); + + ssd1306_print(0, SAVE_DEVICE_COL, "Where to save", 0); + + ssd1306_print(0, SAVE_DEVICE_COL + 14, "#", 0); + itoa32(current_each_device, &buf[0]); + ssd1306_print(0, SAVE_DEVICE_COL + 15, &buf[0], 0); + + ssd1306_char_pos(0, SAVE_DEVICE_COL + 17, pp_gps_air[current_each_device]->device_id[0], 0); + ssd1306_char_pos(0, SAVE_DEVICE_COL + 18, pp_gps_air[current_each_device]->device_id[1], 0); + + ssd1306_print_next("?", 0); + + read_memory_slots(); + + uint8_t another_point_to_save_row = SAVE_DEVICE_ROW; + uint8_t points_enlisted_cntr = 0; + + for (uint8_t s = 1; s <= MEMORY_SLOTS_TOTAL; s++) + { + if (pp_memory_slot[s]->exist_flag == 0) + { + point_to_save_list[s] = points_enlisted_cntr++; //first nonexisting point will get index 0 + + if (current_slot_to_save == 0) //if for the first time + { + current_slot_to_save = s; + } + + //Slot name + ssd1306_print(another_point_to_save_row, SAVE_DEVICE_COL, pp_memory_slot[s]->slot_name, 0); + + another_point_to_save_row++; + } + } + + if (points_enlisted_cntr > 0) + { + ssd1306_print(SAVE_DEVICE_ROW + point_to_save_list[current_slot_to_save], SAVE_DEVICE_COL - 1, ">", 0); + } + else + { + ssd1306_print(SAVE_DEVICE_ROW, SAVE_DEVICE_COL, "no empty slots", 0); + current_slot_to_save = 0; + } + + ssd1306_update(); +} + + + +void draw_save_device_as(void) +{ + #define SAVE_DEV_AS_ROW (2) + #define SAVE_DEV_AS_COL (1) + #define SAVE_DEV_AS_PARAM_COL (11) + + ssd1306_clear(); + ssd1306_print(0, SAVE_DEV_AS_COL, "Set point name", 0); + + ssd1306_print(SAVE_DEV_AS_ROW, SAVE_DEV_AS_COL, "Name", 0); + ssd1306_print(SAVE_DEV_AS_ROW, SAVE_DEV_AS_PARAM_COL, point_to_save_name, 0); + ssd1306_print(SAVE_DEV_AS_ROW + 1, SAVE_DEV_AS_PARAM_COL + point_name_current_symbol, "^", 0); + ssd1306_print(SAVE_DEV_AS_ROW + 3, SAVE_DEV_AS_COL, "Long OK - save", 0); + ssd1306_update(); +} + + + +void draw_saved_popup(void) +{ + ssd1306_clear(); + ssd1306_print(0, 1, "Saved!", 0); + ssd1306_update(); +} + + + +//RADAR +void draw_radar(void) +{ + ssd1306_clear(); + ssd1306_bitmap(&radar_blank[0]); + + //My status row + uint8_t icon_col = LCD_LAST_COL; + + + //Battery + switch (get_device_flags(device_number, FLAGS_BATTERY)) + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_4OF4, 0); + break; + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_3OF4, 0); + break; + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_2OF4, 0); + break; + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_1OF4, 0); + break; + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_0OF4, 0); + break; + } + + + //Sattelites + if (p_gps_raw->time[0] == 0) //if no time received then no sattelites at all + { + ssd1306_char_pos(0, icon_col--, SYMB_NO_SATT, 0); + } + else + { + if (p_gps_num->mode == GPS_POSITION_3DFIX && p_gps_num->status == GPS_DATA_VALID) + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_3D, 0); //3D when data is valid + } + else if (p_gps_num->mode == GPS_POSITION_2DFIX && p_gps_num->status == GPS_DATA_VALID) + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_2D, 0); //2D when data is valid + } + else + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_1D, 0); //if not 2D or 3D then only time is avaliable + } + } + + //TRX + if (get_main_flags()->gps_sync) + { + ssd1306_char_pos(0, icon_col--, SYMB_ARROW_DOWN, 0); + ssd1306_char_pos(0, icon_col--, SYMB_ARROW_UP, 0); + } + + + + //Timeout + if (pp_dev_aux[device_number]->timeout_flag) + { + ssd1306_char_pos(0, icon_col--, SYMB_TIMEOUT, 0); + } + + //Alarm + if (get_device_flags(device_number, FLAGS_ALARM) == FLAG_ALARM_ON) + { + ssd1306_char_pos(0, icon_col--, SYMB_ALARM, 0); + } + + + + //COG + itoa32(pp_gps_air[device_number]->course.as_integer, &buf[0]); + ssd1306_print_viceversa(0, 7, &buf[0], 0); + + + + uint8_t another_radar_dev_row = ANOTHER_RADAR_DEVICE_START_ROW; + uint32_t max_distance = 0; + uint8_t devices_enlisted_cntr = 0; + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + if (dev != device_number) + { + if (pp_dev_aux[dev]->exist_flag == 1) + { + radar_list[dev] = devices_enlisted_cntr++; //first existing device will get index 0 + + if (current_radar_device == 0) //if for the first time + { + current_radar_device = dev; + } + + //Number + itoa32(dev, &buf[0]); + if (radar_list_hide[dev] == 1) + { + ssd1306_print(another_radar_dev_row, 9, &buf[0], 1); + } + else + { + ssd1306_print(another_radar_dev_row, 9, &buf[0], 0); + } + + //ID + ssd1306_char_pos(another_radar_dev_row, 11, pp_gps_air[dev]->device_id[0], 0); + ssd1306_char_pos(another_radar_dev_row, 12, pp_gps_air[dev]->device_id[1], 0); + + //Distance + if (pp_gps_rel[dev]->distance < 1000) //1-999 m + { + itoa32(pp_gps_rel[dev]->distance, &buf[0]); + ssd1306_print_viceversa(another_radar_dev_row, 16, &buf[0], 0); + } + else if (pp_gps_rel[dev]->distance < 10000) //1.0-9.9 km + { + tmpf = pp_gps_rel[dev]->distance / 1000.0; + ftoa32(tmpf, 1, &buf[0]); + ssd1306_print_viceversa(another_radar_dev_row, 16, &buf[0], 0); + } + else if (pp_gps_rel[dev]->distance < 100000) //10.-99. km + { + tmpf = pp_gps_rel[dev]->distance / 1000.0; + itoa32((uint32_t)tmpf, &buf[0]); + ssd1306_print_viceversa(another_radar_dev_row, 16, &buf[0], 0); + ssd1306_char_pos(another_radar_dev_row, 17, '.', 0); + } + else // >100 km + { + ssd1306_print(another_radar_dev_row, 14, "...", 0); + } + + //Search max distance + if (pp_gps_rel[dev]->distance > max_distance) + { + if (radar_list_hide[dev] == 0) + { + max_distance = pp_gps_rel[dev]->distance; //fix max distance only if device is not hided + } + } + + //Heading + itoa32(pp_gps_rel[dev]->heading, &buf[0]); + ssd1306_print_viceversa(another_radar_dev_row, 20, &buf[0], 0); + + + //Warning sign in case of timeout, alarm or fence + if (get_device_flags(dev, FLAGS_ALARM) || pp_dev_aux[dev]->timeout_flag || pp_dev_aux[dev]->fence_flag) + { + ssd1306_print_byte(another_radar_dev_row, 21, custom_exclam_mark, 2); + } + + another_radar_dev_row++; + } + else //if device is not exist + { + radar_list_hide[dev] = 0; //clear hide flag, so when device disappear, and appear again it will be not hided + } + + } + } + + + //Pointer and bottom row information bar + if (devices_enlisted_cntr > 0) + { + ssd1306_print(2 + radar_list[current_radar_device], 8, ">", 0); + + uint8_t icon_col = LCD_LAST_COL; + + if (pp_dev_aux[current_radar_device]->memory_point_flag == 0) //dont show battery icon for memory points + { + //Battery + switch (get_device_flags(current_radar_device, FLAGS_BATTERY)) + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_4OF4, 0); + break; + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_3OF4, 0); + break; + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_2OF4, 0); + break; + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_1OF4, 0); + break; + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_0OF4, 0); + break; + } + } + + + if (pp_dev_aux[current_radar_device]->memory_point_flag == 0) + { + //Timeout + if (pp_dev_aux[current_radar_device]->timeout_flag) + { + ssd1306_char_pos(7, icon_col--, SYMB_TIMEOUT, 0); + } + } + + + //Fence + if (pp_dev_aux[current_radar_device]->fence_flag) + { + ssd1306_char_pos(7, icon_col--, SYMB_FENCE, 0); + } + + + if (pp_dev_aux[current_radar_device]->memory_point_flag == 0) + { + //Alarm + if (get_device_flags(current_radar_device, FLAGS_ALARM) == FLAG_ALARM_ON) + { + ssd1306_char_pos(7, icon_col--, SYMB_ALARM, 0); + } + } + + + //if mem point then print it name + if (pp_dev_aux[current_radar_device]->memory_point_flag == 1) + { + ssd1306_print(7, 9, pp_dev_aux[current_radar_device]->point_name, 0); + } + + + } + else + { + current_radar_device = 0; + } + + + //Radar implementation is here + float mpd_ratio_f = 0.0; //meters per dot ratio + uint32_t mpd_ratio_i = 0; + + if (max_distance < r_circ_dots) + { + max_distance = r_circ_dots; + } + + mpd_ratio_f = (float)max_distance / (float)r_circ_dots; //calc ratio + mpd_ratio_i = (uint32_t)mpd_ratio_f; //extract int part + + mpd_ratio_f -= mpd_ratio_i; //extract frac part + + if (mpd_ratio_f > 0.001) //if frac part is non-zero, then inc ratio + { + mpd_ratio_i++; + } + + //print radar range + uint32_t radar_range = mpd_ratio_i * r_circ_dots; //i.e. radar screen radius + + if (radar_range < 10000) // 0...9999 meters, screen fits 4 characters max + { + itoa32(radar_range, &buf[0]); + ssd1306_print_viceversa(7, 7, &buf[0], 0); + } + else if (radar_range < 1000000) // 10000...999999 meters + { + itoa32((radar_range / 1000), &buf[0]); + ssd1306_char_pos(7, 7, 'k', 0); + ssd1306_print_viceversa(7, 6, &buf[0], 0); + } + else + { + ssd1306_print_viceversa(7, 7, "...", 0); + } + + + + //plot on radar + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + if (dev != device_number) + { + if (pp_dev_aux[dev]->exist_flag == 1) + { + if (radar_list_hide[dev] == 0) //if not hided + { + uint8_t sx1 = 0; //device coordinates on the screen + uint8_t sy1 = 0; + + double x1 = 0.0; //device coordinates relative from my position (0, 0) + double y1 = 0.0; + + x1 = -((pp_gps_rel[dev]->distance)/(double)mpd_ratio_i) * cos((pp_gps_rel[dev]->heading + 90) * deg_to_rad); + y1 = ((pp_gps_rel[dev]->distance)/(double)mpd_ratio_i) * sin((pp_gps_rel[dev]->heading + 90) * deg_to_rad); + + sx1 = sx0 + (int8_t)x1; + sy1 = sy0 - (int8_t)y1; //note: Y axis is inverted (counts from top to the bottom) + + + ssd1306_pixel(sx1, sy1+1, 1); //pixel cross + ssd1306_pixel(sx1+1, sy1, 1); + ssd1306_pixel(sx1, sy1-1, 1); + ssd1306_pixel(sx1-1, sy1, 1); + + //center pixel if device is selected + if (dev == current_radar_device) + { + ssd1306_pixel(sx1, sy1, 1); + } + } + } + } + } + + ssd1306_update(); +} + + + +//POINTS +void draw_points(void) +{ + #define POINTS_ROW (2) + #define POINTS_COL (1) + #define POINTS_NAME_COL (4) + #define POINTS_DATE_COL (10) + + + +#if 0 + + save_memory_point(1, "TEST1", 1); + +#endif + + read_memory_slots(); + + ssd1306_clear(); + ssd1306_print(0, POINTS_COL, "POINTS", 0); + + for (uint8_t s = 1; s <= MEMORY_SLOTS_TOTAL; s++) + { + ssd1306_print(POINTS_ROW + s - 1, POINTS_COL, pp_memory_slot[s]->slot_name, 0); //print slot name + + if (pp_memory_slot[s]->exist_flag == 1) + { + ssd1306_print(POINTS_ROW + s - 1, POINTS_NAME_COL, pp_memory_slot[s]->point_name, 0); //print point name + + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL, pp_memory_slot[s]->save_date[0], 0); //print point save date + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 1, pp_memory_slot[s]->save_date[1], 0); + ssd1306_print(POINTS_ROW + s - 1, POINTS_DATE_COL + 2, ".", 0); + + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 3, pp_memory_slot[s]->save_date[2], 0); + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 4, pp_memory_slot[s]->save_date[3], 0); + ssd1306_print(POINTS_ROW + s - 1, POINTS_DATE_COL + 5, ".", 0); + + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 6, pp_memory_slot[s]->save_date[4], 0); + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 7, pp_memory_slot[s]->save_date[5], 0); + } + else + { + ssd1306_print(POINTS_ROW + s - 1, POINTS_NAME_COL, "empty", 0); + } + } + + ssd1306_print(POINTS_ROW + current_slot_to_load - 1, POINTS_COL - 1, ">", 0); //print pointer + + ssd1306_update(); +} + + + +void draw_each_point(void) +{ + #define EACH_POINT_ROW (2) + #define EACH_POINT_COL (1) + + ssd1306_clear(); + + ssd1306_print(0, EACH_POINT_COL, "POINT ", 0); + ssd1306_print_next(pp_memory_slot[current_slot_to_load]->slot_name, 0); + + ssd1306_print(EACH_POINT_ROW, EACH_POINT_COL, "Load", 0); + ssd1306_print(EACH_POINT_ROW + 1, EACH_POINT_COL, "Delete", 0); + ssd1306_print(EACH_POINT_ROW + get_current_item(), EACH_POINT_COL - 1, ">", 0); + + ssd1306_update(); +} + + + +void draw_load_point(void) +{ + #define LOAD_POINT_ROW (2) + #define LOAD_POINT_COL (1) + + ssd1306_clear(); + + ssd1306_print(0, LOAD_POINT_COL, "Where to load ", 0); + ssd1306_print_next(pp_memory_slot[current_slot_to_load]->slot_name, 0); + ssd1306_print_next("?", 0); + + uint8_t another_device_to_load_row = LOAD_POINT_ROW; + uint8_t devices_enlisted_cntr = 0; + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + { + if (pp_dev_aux[dev]->exist_flag == 0) + { + device_to_load_list[dev] = devices_enlisted_cntr++; //first nonexisting device will get index 0 + + if (current_device_to_load == 0) //if for the first time + { + current_device_to_load = dev; + } + + //Device + ssd1306_print(another_device_to_load_row, LOAD_POINT_COL, "Device ", 0); + + //Number + itoa32(dev, &buf[0]); + ssd1306_print_next(&buf[0], 0); + + another_device_to_load_row++; + } + } + + if (devices_enlisted_cntr > 0) + { + ssd1306_print(LOAD_POINT_ROW + device_to_load_list[current_device_to_load], LOAD_POINT_COL - 1, ">", 0); + } + else + { + ssd1306_print(LOAD_POINT_ROW, LOAD_POINT_COL, "no empty devices", 0); + current_device_to_load = 0; + } + + ssd1306_update(); +} + + + +void draw_delete_point(void) +{ + ssd1306_clear(); + ssd1306_print(0, 1, "Delete point ", 0); + ssd1306_print_next(pp_memory_slot[current_slot_to_load]->slot_name, 0); + ssd1306_print_next("?", 0); + ssd1306_print(3, 1, "OK - delete", 0); + ssd1306_print(4, 1, "ESC - cancel", 0); + ssd1306_update(); +} + + + +//SETTINGS +void draw_settings(void) +{ + #define SETTINGS_ROW (2) + #define SETTINGS_COL (1) + + ssd1306_clear(); + ssd1306_print(0, SETTINGS_COL, "SETTINGS", 0); + ssd1306_print(SETTINGS_ROW, SETTINGS_COL, "Edit", 0); + ssd1306_print(SETTINGS_ROW + 1, SETTINGS_COL, "Restore", 0); + ssd1306_print(SETTINGS_ROW + 2, SETTINGS_COL, "Erase", 0); + ssd1306_print(SETTINGS_ROW + get_current_item(), SETTINGS_COL - 1, ">", 0); + ssd1306_update(); +} + + + +//INFO +void draw_info(void) +{ + ssd1306_clear(); + + ssd1306_bitmap(&info_blank[0]); + + ssd1306_print(0, 0, "LRNS", 0); + + ssd1306_print(2, 0, "HW/FW: ", 0); + ssd1306_print_next(HW_VERSION, 0); + ssd1306_print_next("/", 0); + ssd1306_print_next(FW_VERSION, 0); + + ssd1306_print(3, 0, __TIME__, 0); + ssd1306_print(4, 0, __DATE__, 0); + + ssd1306_print(7, 0, "(C)2021 Feruz Topalov", 0); + + ssd1306_update(); +} + + + +//EDIT SETTINGS +void draw_edit_settings(void) +{ + #define EDIT_SETTINGS_ROW (1) + #define EDIT_SETTINGS_COL (1) + #define EDIT_SETTINGS_PARAM_COL (15) + + ssd1306_clear(); + ssd1306_print(0, EDIT_SETTINGS_COL + 1, "EDIT SETTINGS", 0); + + ssd1306_print(EDIT_SETTINGS_ROW, EDIT_SETTINGS_COL, "Device number", 0); + itoa32(settings_copy.device_number, &buf[0]); + ssd1306_print(EDIT_SETTINGS_ROW, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + + ssd1306_print(EDIT_SETTINGS_ROW + 1, EDIT_SETTINGS_COL, "Device ID", 0); + buf[0] = settings_copy.device_id[0]; + buf[1] = settings_copy.device_id[1]; + buf[2] = 0; + ssd1306_print(EDIT_SETTINGS_ROW + 1, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + + ssd1306_print(EDIT_SETTINGS_ROW + 2, EDIT_SETTINGS_COL, "Freq channel", 0); + itoa32(settings_copy.freq_channel, &buf[0]); + ssd1306_print(EDIT_SETTINGS_ROW + 2, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + + ssd1306_print(EDIT_SETTINGS_ROW + 3, EDIT_SETTINGS_COL, "TX power", 0); + itoa32(p_get_tx_power_values[settings_copy.tx_power_opt], &buf[0]); + ssd1306_print(EDIT_SETTINGS_ROW + 3, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + ssd1306_print_next(" mW", 0); + + ssd1306_print(EDIT_SETTINGS_ROW + 4, EDIT_SETTINGS_COL, "Send interval", 0); + itoa32(p_send_interval_values[settings_copy.send_interval_opt], &buf[0]); + ssd1306_print(EDIT_SETTINGS_ROW + 4, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + ssd1306_print_next(" s", 0); + + ssd1306_print(EDIT_SETTINGS_ROW + 5, EDIT_SETTINGS_COL, "Timeout thr", 0); + itoa32(settings_copy.timeout_threshold.as_integer, &buf[0]); + ssd1306_print(EDIT_SETTINGS_ROW + 5, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + ssd1306_print_next(" s", 0); + + ssd1306_print(EDIT_SETTINGS_ROW + 6, EDIT_SETTINGS_COL, "Fence thr", 0); + itoa32(settings_copy.fence_threshold.as_integer, &buf[0]); + ssd1306_print(EDIT_SETTINGS_ROW + 6, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + ssd1306_print_next(" m", 0); + + ssd1306_print(EDIT_SETTINGS_ROW + get_current_item(), EDIT_SETTINGS_COL - 1, ">", 0); + ssd1306_update(); +} + + + +//SET DEV NUM +void draw_set_dev_num(void) +{ + #define SET_DEV_NUM_ROW (2) + #define SET_DEV_NUM_COL (1) + #define SET_DEV_NUM_PARAM_COL (15) + + ssd1306_clear(); + ssd1306_print(0, SET_DEV_NUM_COL, "SET DEV NUM", 0); + + ssd1306_print(SET_DEV_NUM_ROW, SET_DEV_NUM_COL, "Device number", 0); + itoa32(settings_copy.device_number, &buf[0]); + ssd1306_print(SET_DEV_NUM_ROW, SET_DEV_NUM_PARAM_COL, &buf[0], 0); + ssd1306_print(SET_DEV_NUM_ROW + 1, SET_DEV_NUM_PARAM_COL, "^", 0); + ssd1306_update(); +} + + + +//SET DEV ID +void draw_set_dev_id(void) +{ + #define SET_DEV_ID_ROW (2) + #define SET_DEV_ID_COL (1) + #define SET_DEV_ID_PARAM_COL (15) + + ssd1306_clear(); + ssd1306_print(0, SET_DEV_NUM_COL, "SET DEV ID", 0); + + ssd1306_print(SET_DEV_ID_ROW, SET_DEV_ID_COL, "Device ID", 0); + buf[0] = settings_copy.device_id[0]; + buf[1] = settings_copy.device_id[1]; + buf[2] = 0; + ssd1306_print(SET_DEV_ID_ROW, SET_DEV_ID_PARAM_COL, &buf[0], 0); + ssd1306_print(SET_DEV_ID_ROW + 1, SET_DEV_ID_PARAM_COL + device_id_current_symbol, "^", 0); + ssd1306_print(SET_DEV_ID_ROW + 3, SET_DEV_ID_COL, "Long OK - apply", 0); + ssd1306_update(); +} + + + +//SET FREQ CH +void draw_set_freq_ch(void) +{ + #define SET_FREQ_CH_ROW (2) + #define SET_FREQ_CH_COL (1) + #define SET_FREQ_CH_PARAM_COL (16) + + ssd1306_clear(); + ssd1306_print(0, SET_FREQ_CH_COL, "SET FREQ CH", 0); + + ssd1306_print(SET_FREQ_CH_ROW, SET_FREQ_CH_COL, "Freq channel", 0); + itoa32(settings_copy.freq_channel, &buf[0]); + ssd1306_print_viceversa(SET_FREQ_CH_ROW, SET_FREQ_CH_PARAM_COL, &buf[0], 0); + ssd1306_print(SET_FREQ_CH_ROW + 1, SET_FREQ_CH_PARAM_COL, "^", 0); + ssd1306_update(); +} + + + +//SET TX POW +void draw_set_tx_pow(void) +{ + #define SET_TX_POW_ROW (2) + #define SET_TX_POW_COL (1) + #define SET_TX_POW_PARAM_COL (15) + + ssd1306_clear(); + ssd1306_print(0, SET_TX_POW_COL, "SET TX POW", 0); + + ssd1306_print(SET_TX_POW_ROW, SET_TX_POW_COL, "TX power", 0); + itoa32(p_get_tx_power_values[settings_copy.tx_power_opt], &buf[0]); + ssd1306_print(SET_TX_POW_ROW, SET_TX_POW_PARAM_COL, &buf[0], 0); + ssd1306_print_next(" mW", 0); + ssd1306_print(SET_TX_POW_ROW + 1, SET_TX_POW_PARAM_COL, "^", 0); + ssd1306_update(); +} + + + +//SET SEND INTRVL +void draw_set_send_intvl(void) +{ + #define SET_SEND_INTVL_ROW (2) + #define SET_SEND_INTVL_COL (1) + #define SET_SEND_INTVL_PARAM_COL (16) + + ssd1306_clear(); + ssd1306_print(0, SET_SEND_INTVL_COL, "SET SEND INTVL", 0); + + ssd1306_print(SET_SEND_INTVL_ROW, SET_SEND_INTVL_COL, "Send interval", 0); + itoa32(p_send_interval_values[settings_copy.send_interval_opt], &buf[0]); + ssd1306_print(SET_SEND_INTVL_ROW, SET_SEND_INTVL_PARAM_COL, &buf[0], 0); + ssd1306_print_next(" s", 0); + ssd1306_print(SET_SEND_INTVL_ROW + 1, SET_SEND_INTVL_PARAM_COL, "^", 0); + ssd1306_update(); +} + + + +//SET TIMEOUT THR +void draw_set_to_thr(void) +{ + #define SET_TO_THR_ROW (2) + #define SET_TO_THR_COL (1) + #define SET_TO_THR_PARAM_COL (14) + + ssd1306_clear(); + ssd1306_print(0, SET_TO_THR_COL, "SET TO THR", 0); + + ssd1306_print(SET_TO_THR_ROW, SET_TO_THR_COL, "Timeout thr", 0); + itoa32(settings_copy.timeout_threshold.as_integer, &buf[0]); + ssd1306_print(SET_TO_THR_ROW, SET_TO_THR_PARAM_COL, &buf[0], 0); + ssd1306_print_next(" s", 0); + ssd1306_print(SET_TO_THR_ROW + 1, SET_TO_THR_PARAM_COL, "^", 0); + ssd1306_update(); +} + + + +//SET TIMEOUT THR +void draw_set_fnc_thr(void) +{ + #define SET_FNC_THR_ROW (2) + #define SET_FNC_THR_COL (1) + #define SET_FNC_THR_PARAM_COL (14) + + ssd1306_clear(); + ssd1306_print(0, SET_FNC_THR_COL, "SET FNC THR", 0); + + ssd1306_print(SET_FNC_THR_ROW, SET_FNC_THR_COL, "Fence thr", 0); + itoa32(settings_copy.fence_threshold.as_integer, &buf[0]); + ssd1306_print(SET_FNC_THR_ROW, SET_FNC_THR_PARAM_COL, &buf[0], 0); + ssd1306_print_next(" m", 0); + ssd1306_print(SET_FNC_THR_ROW + 1, SET_FNC_THR_PARAM_COL, "^", 0); + ssd1306_update(); +} + + + +//CONFIRM SETTINGS SAVE +void draw_confirm_settings_save(void) +{ + if (flag_settings_changed) + { + ssd1306_clear(); + ssd1306_print(0, 1, "Settings changed", 0); + ssd1306_print(3, 1, "OK - save & restart", 0); + ssd1306_print(4, 1, "ESC - cancel changes", 0); + ssd1306_update(); + } + else + { + current_menu = M_SETTINGS; + draw_current_menu(); + } +} + + + +//RESTORE DEFAULTS +void draw_restore_defaults(void) +{ + ssd1306_clear(); + ssd1306_print(0, 1, "Restore defaults?", 0); + ssd1306_print(3, 1, "OK - restore & reset", 0); + ssd1306_print(4, 1, "ESC - cancel", 0); + ssd1306_update(); +} + + + +//ERASE ALL +void draw_erase_all(void) +{ + ssd1306_clear(); + ssd1306_print(0, 1, "Erase all EEPROM?", 0); + ssd1306_print(3, 1, "OK - erase & reset", 0); + ssd1306_print(4, 1, "ESC - cancel", 0); + ssd1306_update(); +} + + + +void devices_ok(void) +{ + if (pp_dev_aux[current_each_device]->exist_flag == 0) + { + each_device_up(); + } + + current_menu = M_EACH_DEVICE; + draw_current_menu(); +} + + + +void each_device_up(void) +{ + do + { + if (current_each_device == DEVICE_NUMBER_FIRST) + { + current_each_device = DEVICE_NUMBER_LAST; + } + else + { + current_each_device--; + } + } + while (pp_dev_aux[current_each_device]->exist_flag == 0); + + draw_current_menu(); +} + + + +void each_device_down(void) +{ + do + { + if (current_each_device == DEVICE_NUMBER_LAST) + { + current_each_device = DEVICE_NUMBER_FIRST; + } + else + { + current_each_device++; + } + } + while (pp_dev_aux[current_each_device]->exist_flag == 0); + + draw_current_menu(); +} + + + +void each_device_ok(void) +{ + current_menu = M_EACH_DEVICE_SUBMENU; + draw_current_menu(); +} + + + +void save_device_up(void) +{ + if (current_slot_to_save != 0) + { + do + { + if (current_slot_to_save == MEMORY_SLOT_FIRST) + { + current_slot_to_save = MEMORY_SLOT_LAST; + } + else + { + current_slot_to_save--; + } + } + while (pp_memory_slot[current_slot_to_save]->exist_flag == 1); + + draw_current_menu(); + } +} + + + +void save_device_down(void) +{ + if (current_slot_to_save != 0) + { + do + { + if (current_slot_to_save == MEMORY_SLOT_LAST) + { + current_slot_to_save = MEMORY_SLOT_FIRST; + } + else + { + current_slot_to_save++; + } + } + while (pp_memory_slot[current_slot_to_save]->exist_flag == 1); + + draw_current_menu(); + } +} + + + +void save_device_ok(void) +{ + if (current_slot_to_save != 0) + { + current_menu = M_SAVE_DEVICE_AS; + draw_current_menu(); + } +} + + + +void save_device_esc(void) +{ + current_slot_to_save = 0; + current_menu = M_EACH_DEVICE_SUBMENU; + draw_current_menu(); +} + + + +void save_device_as_up(void) +{ + if (point_to_save_name[point_name_current_symbol] == POINT_NAME_LAST_SYMBOL) + { + point_to_save_name[point_name_current_symbol] = POINT_NAME_FIRST_SYMBOL; + } + else + { + point_to_save_name[point_name_current_symbol]++; + } + + draw_current_menu(); +} + + + +void save_device_as_down(void) +{ + if (point_to_save_name[point_name_current_symbol] == POINT_NAME_FIRST_SYMBOL) + { + point_to_save_name[point_name_current_symbol] = POINT_NAME_LAST_SYMBOL; + } + else + { + point_to_save_name[point_name_current_symbol]--; + } + + draw_current_menu(); +} + + + +void save_device_as_ok(void) +{ + if (++point_name_current_symbol == MEMORY_POINT_NAME_LENGTH) + { + point_name_current_symbol = 0; + } + + draw_current_menu(); +} + + + +void save_device_as_ok_long(void) +{ + save_memory_point(current_each_device, &point_to_save_name[0], current_slot_to_save); + + current_each_device = device_number; + current_slot_to_save = 0; + point_name_current_symbol = 0; + + current_menu = M_SAVED_POPUP; + draw_current_menu(); +} + + + +void save_device_as_esc(void) +{ + point_name_current_symbol = 0; + current_menu = M_SAVE_DEVICE; + draw_current_menu(); +} + + + +void saved_popup_esc(void) +{ + current_each_device = device_number; + current_slot_to_save = 0; + point_name_current_symbol = 0; + + current_menu = M_DEVICES; + draw_current_menu(); +} + + + +void radar_up(void) +{ + if (current_radar_device != 0) + { + do + { + do + { + if (current_radar_device == DEVICE_NUMBER_FIRST) + { + current_radar_device = DEVICE_NUMBER_LAST; + } + else + { + current_radar_device--; + } + } + while (pp_dev_aux[current_radar_device]->exist_flag == 0); + } + while (current_radar_device == device_number); + + draw_current_menu(); + } +} + + + +void radar_down(void) +{ + if (current_radar_device != 0) + { + do + { + do + { + if (current_radar_device == DEVICE_NUMBER_LAST) + { + current_radar_device = DEVICE_NUMBER_FIRST; + } + else + { + current_radar_device++; + } + } + while (pp_dev_aux[current_radar_device]->exist_flag == 0); + } + while (current_radar_device == device_number); + + draw_current_menu(); + } +} + + + +void radar_ok(void) +{ + if (current_radar_device != 0) + { + radar_list_hide[current_radar_device] ^= 1; //Invert hide flag + + draw_current_menu(); + } +} + + + +void points_up(void) +{ + if (current_slot_to_load == MEMORY_SLOT_FIRST) + { + current_slot_to_load = MEMORY_SLOT_LAST; + } + else + { + current_slot_to_load--; + } + + draw_current_menu(); +} + + + +void points_down(void) +{ + if (current_slot_to_load == MEMORY_SLOT_LAST) + { + current_slot_to_load = MEMORY_SLOT_FIRST; + } + else + { + current_slot_to_load++; + } + + draw_current_menu(); +} + + + +void points_ok(void) +{ + if (pp_memory_slot[current_slot_to_load]->exist_flag == 1) + { + current_menu = M_EACH_POINT; + draw_current_menu(); + } +} + + + +void points_esc(void) +{ + current_slot_to_load = MEMORY_SLOT_FIRST; + current_menu = M_MAIN; + draw_current_menu(); +} + + + +void load_point_up(void) +{ + if (current_device_to_load != 0) + { + do + { + do + { + if (current_device_to_load == DEVICE_NUMBER_FIRST) + { + current_device_to_load = DEVICE_NUMBER_LAST; + } + else + { + current_device_to_load--; + } + } + while (pp_dev_aux[current_device_to_load]->exist_flag == 1); + } + while (current_device_to_load == device_number); + + draw_current_menu(); + } +} + + + +void load_point_down(void) +{ + if (current_device_to_load != 0) + { + do + { + do + { + if (current_device_to_load == DEVICE_NUMBER_LAST) + { + current_device_to_load = DEVICE_NUMBER_FIRST; + } + else + { + current_device_to_load++; + } + } + while (pp_dev_aux[current_device_to_load]->exist_flag == 1); + } + while (current_device_to_load == device_number); + + draw_current_menu(); + } +} + + + +void load_point_ok(void) +{ + if (current_device_to_load != 0) + { + load_memory_point(current_device_to_load, current_slot_to_load); + + current_slot_to_load = MEMORY_SLOT_FIRST; + current_device_to_load = 0; + current_menu = M_MAIN; + draw_current_menu(); + } +} + + + +void load_point_esc(void) +{ + current_device_to_load = 0; + current_menu = M_EACH_POINT; + draw_current_menu(); +} + + + +void delete_point_ok(void) +{ + delete_memory_point(current_slot_to_load); + + reset_current_item_in_menu(M_EACH_POINT); + current_slot_to_load = MEMORY_SLOT_FIRST; + current_menu = M_POINTS; + draw_current_menu(); +} + + + +void set_dev_num_up(void) +{ + if (settings_copy.device_number == DEVICE_NUMBER_LAST) + { + settings_copy.device_number = DEVICE_NUMBER_FIRST; + } + else + { + settings_copy.device_number++; + } + + draw_current_menu(); +} + + + +void set_dev_num_down(void) +{ + if (settings_copy.device_number == DEVICE_NUMBER_FIRST) + { + settings_copy.device_number = DEVICE_NUMBER_LAST; + } + else + { + settings_copy.device_number--; + } + + draw_current_menu(); +} + + + +void set_dev_num_ok(void) +{ + if (settings_copy.device_number != device_number) + { + flag_settings_changed = 1; + } + + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_dev_num_esc(void) +{ + settings_copy.device_number = device_number; //exit no save, reset value + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void confirm_settings_save_ok(void) +{ + settings_save(&settings_copy); + NVIC_SystemReset(); +} + + + +void set_dev_id_up(void) +{ + if (settings_copy.device_id[device_id_current_symbol] == DEVICE_ID_LAST_SYMBOL) + { + settings_copy.device_id[device_id_current_symbol] = DEVICE_ID_FIRST_SYMBOL; + } + else + { + settings_copy.device_id[device_id_current_symbol]++; + } + + draw_current_menu(); +} + + + +void set_dev_id_down(void) +{ + if (settings_copy.device_id[device_id_current_symbol] == DEVICE_ID_FIRST_SYMBOL) + { + settings_copy.device_id[device_id_current_symbol] = DEVICE_ID_LAST_SYMBOL; + } + else + { + settings_copy.device_id[device_id_current_symbol]--; + } + + draw_current_menu(); +} + + + +void set_dev_id_ok(void) +{ + if (++device_id_current_symbol == DEVICE_ID_LEN) + { + device_id_current_symbol = 0; + } + + draw_current_menu(); +} + + + +void set_dev_id_ok_long(void) +{ + for (uint8_t i = 0; i < DEVICE_ID_LEN; i++) + { + if (settings_copy.device_id[i] != p_settings->device_id[i]) + { + flag_settings_changed = 1; + break; + } + } + + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_dev_id_esc(void) +{ + for (uint8_t i = 0; i < DEVICE_ID_LEN; i++) + { + settings_copy.device_id[i] = p_settings->device_id[i]; //exit no save, reset value + } + device_id_current_symbol = 0; + + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_freq_ch_up(void) +{ + if (settings_copy.freq_channel == FREQ_CHANNEL_LAST) + { + settings_copy.freq_channel = FREQ_CHANNEL_FIRST; + } + else + { + settings_copy.freq_channel++; + } + + draw_current_menu(); +} + + + +void set_freq_ch_down(void) +{ + if (settings_copy.freq_channel == FREQ_CHANNEL_FIRST) + { + settings_copy.freq_channel = FREQ_CHANNEL_LAST; + } + else + { + settings_copy.freq_channel--; + } + + draw_current_menu(); +} + + + +void set_freq_ch_ok(void) +{ + if (settings_copy.freq_channel != p_settings->freq_channel) + { + flag_settings_changed = 1; + } + + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_freq_ch_esc(void) +{ + settings_copy.freq_channel = p_settings->freq_channel; //exit no save, reset value + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_tx_pow_up(void) +{ + if (settings_copy.tx_power_opt == TX_POWER_LAST_OPTION) + { + settings_copy.tx_power_opt = TX_POWER_FIRST_OPTION; + } + else + { + settings_copy.tx_power_opt++; + } + + draw_current_menu(); +} + + + +void set_tx_pow_down(void) +{ + if (settings_copy.tx_power_opt == TX_POWER_FIRST_OPTION) + { + settings_copy.tx_power_opt = TX_POWER_LAST_OPTION; + } + else + { + settings_copy.tx_power_opt--; + } + + draw_current_menu(); +} + + + +void set_tx_pow_ok(void) +{ + if (settings_copy.tx_power_opt != p_settings->tx_power_opt) + { + flag_settings_changed = 1; + } + + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_tx_pow_esc(void) +{ + settings_copy.tx_power_opt = p_settings->tx_power_opt; //exit no save, reset value + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_send_intvl_up(void) +{ + if (settings_copy.send_interval_opt == SEND_INTERVAL_LAST_OPTION) + { + settings_copy.send_interval_opt = SEND_INTERVAL_FIRST_OPTION; + } + else + { + settings_copy.send_interval_opt++; + } + + draw_current_menu(); +} + + + +void set_send_intvl_down(void) +{ + if (settings_copy.send_interval_opt == SEND_INTERVAL_FIRST_OPTION) + { + settings_copy.send_interval_opt = SEND_INTERVAL_LAST_OPTION; + } + else + { + settings_copy.send_interval_opt--; + } + + draw_current_menu(); +} + + + +void set_send_intvl_ok(void) +{ + if (settings_copy.send_interval_opt != p_settings->send_interval_opt) + { + flag_settings_changed = 1; + } + + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_send_intvl_esc(void) +{ + settings_copy.send_interval_opt = p_settings->send_interval_opt; //exit no save, reset value + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_to_thr_up(void) +{ + #define TIMEOUT_THRESHOLD_MAX (3600) + #define TIMEOUT_THRESHOLD_STEP (10) + + if (settings_copy.timeout_threshold.as_integer < TIMEOUT_THRESHOLD_MAX) + { + settings_copy.timeout_threshold.as_integer += TIMEOUT_THRESHOLD_STEP; + } + + draw_current_menu(); +} + + + +void set_to_thr_down(void) +{ + #define TIMEOUT_THRESHOLD_MIN (0) + + if (settings_copy.timeout_threshold.as_integer > TIMEOUT_THRESHOLD_MIN) + { + settings_copy.timeout_threshold.as_integer -= TIMEOUT_THRESHOLD_STEP; + } + + draw_current_menu(); +} + + + +void set_to_thr_ok(void) +{ + if (settings_copy.timeout_threshold.as_integer != p_settings->timeout_threshold.as_integer) + { + flag_settings_changed = 1; + } + + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_to_thr_esc(void) +{ + settings_copy.timeout_threshold.as_integer = p_settings->timeout_threshold.as_integer; //exit no save, reset value + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_fnc_thr_up(void) +{ + #define FENCE_THRESHOLD_MAX (3600) + #define FENCE_THRESHOLD_STEP (10) + + if (settings_copy.fence_threshold.as_integer < FENCE_THRESHOLD_MAX) + { + settings_copy.fence_threshold.as_integer += FENCE_THRESHOLD_STEP; + } + + draw_current_menu(); +} + + + +void set_fnc_thr_down(void) +{ + #define FENCE_THRESHOLD_MIN (0) + + if (settings_copy.fence_threshold.as_integer > FENCE_THRESHOLD_MIN) + { + settings_copy.fence_threshold.as_integer -= FENCE_THRESHOLD_STEP; + } + + draw_current_menu(); +} + + + +void set_fnc_thr_ok(void) +{ + if (settings_copy.fence_threshold.as_integer != p_settings->fence_threshold.as_integer) + { + flag_settings_changed = 1; + } + + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void set_fnc_thr_esc(void) +{ + settings_copy.fence_threshold.as_integer = p_settings->fence_threshold.as_integer; //exit no save, reset value + current_menu = M_EDIT_SETTINGS; + draw_current_menu(); +} + + + +void confirm_settings_save_esc(void) +{ + settings_copy = *p_settings; //reset to no changes state + flag_settings_changed = 0; //clear flag + current_menu = M_SETTINGS; + draw_current_menu(); +} + + + +void restore_defaults_ok(void) +{ + settings_save_default(); + NVIC_SystemReset(); +} + + + +void erase_all_ok(void) +{ + ssd1306_clear(); + ssd1306_print(0, 1, "WAIT...", 0); + ssd1306_update(); + m24c64_erase_all(); + NVIC_SystemReset(); +} diff --git a/Firmware/CubeIDE/Code/src/points.c b/Firmware/CubeIDE/Code/src/points.c new file mode 100644 index 0000000..6dfa710 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/points.c @@ -0,0 +1,227 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: points.c +*/ + +#include +#include "stm32f10x.h" +#include "points.h" +#include "m24c64.h" +#include "settings.h" +#include "lrns.h" +#include "gps.h" +#include "service.h" +#include "main.h" + + + +//positions: +#define MEMORY_POINT_EXIST_FLAG_POS (0) + +#define MEMORY_POINT_NAME_POS (1) + +#define MEMORY_POINT_DAY_POS (6) +#define MEMORY_POINT_MONTH_POS (8) +#define MEMORY_POINT_YEAR_POS (10) + +#define MEMORY_POINT_LATITUDE_POS (12) +#define MEMORY_POINT_LONGITUDE_POS (16) +#define MEMORY_POINT_ALTITUDE_POS (20) + + + +//default values: +#define POINT_EXIST_FLAG_DEFAULT (0xAA) + + + +#define MEMORY_SLOT_1_NAME ("S1") +#define MEMORY_SLOT_2_NAME ("S2") +#define MEMORY_SLOT_3_NAME ("S3") +#define MEMORY_SLOT_4_NAME ("S4") +#define MEMORY_SLOT_5_NAME ("S5") + +#define MEMORY_SLOT_NAMES { "0", \ + MEMORY_SLOT_1_NAME, \ + MEMORY_SLOT_2_NAME, \ + MEMORY_SLOT_3_NAME, \ + MEMORY_SLOT_4_NAME, \ + MEMORY_SLOT_5_NAME } + + + +void clear_point_buffer(void); + + + +struct memory_slot_struct memory_slot[MEMORY_SLOTS_TOTAL + 1]; //index 0 is invalid and not used; slots start from 1 to MEMORY_SLOTS_TOTAL +struct memory_slot_struct *p_memory_slot[MEMORY_SLOTS_TOTAL + 1]; + +uint8_t point_buffer[M24C64_PAGE_SIZE]; +struct gps_raw_struct *p_gps_raw; +struct gps_air_struct **pp_gps_air; +struct dev_aux_struct **pp_dev_aux; + +char *memory_slot_names[MEMORY_SLOTS_TOTAL + 1] = MEMORY_SLOT_NAMES; + + + +struct memory_slot_struct **get_memory_slot(void) +{ + for (uint8_t slot = 1; slot <= MEMORY_SLOTS_TOTAL; slot++) + { + p_memory_slot[slot] = &memory_slot[slot]; + } + + return &p_memory_slot[0]; +} + + + +void init_points(void) +{ + p_gps_raw = get_gps_raw(); + pp_gps_air = get_gps_air(); + pp_dev_aux = get_dev_aux(); + + for (uint8_t slot = 1; slot <= MEMORY_SLOTS_TOTAL; slot++) + { + memory_slot[slot].slot_name[0] = memory_slot_names[slot][0]; //init slot names + memory_slot[slot].slot_name[1] = memory_slot_names[slot][1]; + memory_slot[slot].slot_name[2] = 0; + } +} + + + +void read_memory_slots(void) +{ + for (uint8_t slot = 1; slot <= MEMORY_SLOTS_TOTAL; slot++) + { + + clear_point_buffer(); + m24c64_read_page(&point_buffer[0], slot); + + if (point_buffer[MEMORY_POINT_EXIST_FLAG_POS] == POINT_EXIST_FLAG_DEFAULT) + { + memory_slot[slot].exist_flag = 1; + + memory_slot[slot].point_name[0] = point_buffer[MEMORY_POINT_NAME_POS]; + memory_slot[slot].point_name[1] = point_buffer[MEMORY_POINT_NAME_POS + 1]; + memory_slot[slot].point_name[2] = point_buffer[MEMORY_POINT_NAME_POS + 2]; + memory_slot[slot].point_name[3] = point_buffer[MEMORY_POINT_NAME_POS + 3]; + memory_slot[slot].point_name[4] = point_buffer[MEMORY_POINT_NAME_POS + 4]; + memory_slot[slot].point_name[5] = 0; + + memory_slot[slot].save_date[0] = point_buffer[MEMORY_POINT_DAY_POS]; + memory_slot[slot].save_date[1] = point_buffer[MEMORY_POINT_DAY_POS + 1]; + memory_slot[slot].save_date[2] = point_buffer[MEMORY_POINT_MONTH_POS]; + memory_slot[slot].save_date[3] = point_buffer[MEMORY_POINT_MONTH_POS + 1]; + memory_slot[slot].save_date[4] = point_buffer[MEMORY_POINT_YEAR_POS]; + memory_slot[slot].save_date[5] = point_buffer[MEMORY_POINT_YEAR_POS + 1]; + } + else + { + memory_slot[slot].exist_flag = 0; + } + } +} + + + +//Save selected device in a slot +void save_memory_point(uint8_t dev_num, char *point_name, uint8_t slot_num) +{ + clear_point_buffer(); + + point_buffer[MEMORY_POINT_EXIST_FLAG_POS] = POINT_EXIST_FLAG_DEFAULT; + + point_buffer[MEMORY_POINT_NAME_POS] = point_name[0]; + point_buffer[MEMORY_POINT_NAME_POS + 1] = point_name[1]; + point_buffer[MEMORY_POINT_NAME_POS + 2] = point_name[2]; + point_buffer[MEMORY_POINT_NAME_POS + 3] = point_name[3]; + point_buffer[MEMORY_POINT_NAME_POS + 4] = point_name[4]; + + point_buffer[MEMORY_POINT_DAY_POS] = p_gps_raw->date[0]; //save in char format for easy print in the menu + point_buffer[MEMORY_POINT_DAY_POS + 1] = p_gps_raw->date[1]; + + point_buffer[MEMORY_POINT_MONTH_POS] = p_gps_raw->date[2]; + point_buffer[MEMORY_POINT_MONTH_POS + 1] = p_gps_raw->date[3]; + + point_buffer[MEMORY_POINT_YEAR_POS] = p_gps_raw->date[4]; + point_buffer[MEMORY_POINT_YEAR_POS + 1] = p_gps_raw->date[5]; + + point_buffer[MEMORY_POINT_LATITUDE_POS] = pp_gps_air[dev_num]->latitude.as_array[0]; + point_buffer[MEMORY_POINT_LATITUDE_POS + 1] = pp_gps_air[dev_num]->latitude.as_array[1]; + point_buffer[MEMORY_POINT_LATITUDE_POS + 2] = pp_gps_air[dev_num]->latitude.as_array[2]; + point_buffer[MEMORY_POINT_LATITUDE_POS + 3] = pp_gps_air[dev_num]->latitude.as_array[3]; + + point_buffer[MEMORY_POINT_LONGITUDE_POS] = pp_gps_air[dev_num]->longitude.as_array[0]; + point_buffer[MEMORY_POINT_LONGITUDE_POS + 1] = pp_gps_air[dev_num]->longitude.as_array[1]; + point_buffer[MEMORY_POINT_LONGITUDE_POS + 2] = pp_gps_air[dev_num]->longitude.as_array[2]; + point_buffer[MEMORY_POINT_LONGITUDE_POS + 3] = pp_gps_air[dev_num]->longitude.as_array[3]; + + point_buffer[MEMORY_POINT_ALTITUDE_POS] = pp_gps_air[dev_num]->altitude.as_array[0]; + point_buffer[MEMORY_POINT_ALTITUDE_POS + 1] = pp_gps_air[dev_num]->altitude.as_array[1]; + + m24c64_write_page(&point_buffer[0], slot_num); +} + + + +void load_memory_point(uint8_t dev_num, uint8_t slot_num) +{ + clear_point_buffer(); + + m24c64_read_page(&point_buffer[0], slot_num); + + memset(pp_gps_air[dev_num], 0, sizeof(*(pp_gps_air[dev_num]))); + memset(pp_dev_aux[dev_num], 0, sizeof(*(pp_dev_aux[dev_num]))); + + pp_dev_aux[dev_num]->exist_flag = 1; + pp_dev_aux[dev_num]->memory_point_flag = 1; + pp_dev_aux[dev_num]->timestamp = get_uptime(); + + for (uint8_t c = 0; c < MEMORY_POINT_NAME_LENGTH; c++) + { + pp_dev_aux[dev_num]->point_name[c] = memory_slot[slot_num].point_name[c]; + } + + pp_gps_air[dev_num]->device_id[0] = memory_slot[slot_num].slot_name[0]; + pp_gps_air[dev_num]->device_id[1] = memory_slot[slot_num].slot_name[1]; + + pp_gps_air[dev_num]->latitude.as_array[0] = point_buffer[MEMORY_POINT_LATITUDE_POS]; + pp_gps_air[dev_num]->latitude.as_array[1] = point_buffer[MEMORY_POINT_LATITUDE_POS + 1]; + pp_gps_air[dev_num]->latitude.as_array[2] = point_buffer[MEMORY_POINT_LATITUDE_POS + 2]; + pp_gps_air[dev_num]->latitude.as_array[3] = point_buffer[MEMORY_POINT_LATITUDE_POS + 3]; + + pp_gps_air[dev_num]->longitude.as_array[0] = point_buffer[MEMORY_POINT_LONGITUDE_POS]; + pp_gps_air[dev_num]->longitude.as_array[1] = point_buffer[MEMORY_POINT_LONGITUDE_POS + 1]; + pp_gps_air[dev_num]->longitude.as_array[2] = point_buffer[MEMORY_POINT_LONGITUDE_POS + 2]; + pp_gps_air[dev_num]->longitude.as_array[3] = point_buffer[MEMORY_POINT_LONGITUDE_POS + 3]; + + pp_gps_air[dev_num]->altitude.as_array[0] = point_buffer[MEMORY_POINT_ALTITUDE_POS]; + pp_gps_air[dev_num]->altitude.as_array[1] = point_buffer[MEMORY_POINT_ALTITUDE_POS + 1]; +} + + + +void delete_memory_point(uint8_t slot_num) +{ + clear_point_buffer(); + m24c64_write_page(&point_buffer[0], slot_num); +} + + + +void clear_point_buffer(void) +{ + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + { + point_buffer[i] = M24C64_EMPTY_CELL_VALUE; + } +} diff --git a/Firmware/CubeIDE/Code/src/service.c b/Firmware/CubeIDE/Code/src/service.c new file mode 100644 index 0000000..9033f0e --- /dev/null +++ b/Firmware/CubeIDE/Code/src/service.c @@ -0,0 +1,366 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: service.c +*/ + +#include +#include "stm32f10x.h" +#include "service.h" + + + +//Convert timeout in seconds to timeout in "XXdXXhXXmXXs" +void convert_timeout(uint32_t timeout_val, char *buffer) +{ + uint32_t sec = 0; + uint32_t min = 0; + uint32_t hour = 0; + uint32_t day = 0; + char buf[3]; + + + if (timeout_val >= 60) + { + min = timeout_val / 60; + sec = timeout_val % 60; + + if (min >= 60) + { + hour = min / 60; + min = min % 60; + + if (hour >= 24) + { + day = hour / 24; + hour = hour % 24; + } + } + } + else + { + sec = timeout_val; + } + + if (day) + { + //XXdXXh + itoa32(day, &buf[0]); + if (day > 9) + { + buffer[0] = buf[0]; + buffer[1] = buf[1]; + buffer[2] = 'd'; + } + else + { + buffer[0] = '0'; + buffer[1] = buf[0]; + buffer[2] = 'd'; + } + + itoa32(hour, &buf[0]); + if (hour > 9) + { + buffer[3] = buf[0]; + buffer[4] = buf[1]; + buffer[5] = 'h'; + } + else + { + buffer[3] = '0'; + buffer[4] = buf[0]; + buffer[5] = 'h'; + } + } + else if (hour) + { + //XXhXXm + itoa32(hour, &buf[0]); + if (hour > 9) + { + buffer[0] = buf[0]; + buffer[1] = buf[1]; + buffer[2] = 'h'; + } + else + { + buffer[0] = '0'; + buffer[1] = buf[0]; + buffer[2] = 'h'; + } + + itoa32(min, &buf[0]); + if (min > 9) + { + buffer[3] = buf[0]; + buffer[4] = buf[1]; + buffer[5] = 'm'; + } + else + { + buffer[3] = '0'; + buffer[4] = buf[0]; + buffer[5] = 'm'; + } + } + else + { + //XXmXXs + itoa32(min, &buf[0]); + if (min > 9) + { + buffer[0] = buf[0]; + buffer[1] = buf[1]; + buffer[2] = 'm'; + } + else + { + buffer[0] = '0'; + buffer[1] = buf[0]; + buffer[2] = 'm'; + } + + itoa32(sec, &buf[0]); + if (sec > 9) + { + buffer[3] = buf[0]; + buffer[4] = buf[1]; + buffer[5] = 's'; + } + else + { + buffer[3] = '0'; + buffer[4] = buf[0]; + buffer[5] = 's'; + } + } + + buffer[6] = 0; //string end +} + + + +//Simple delay in cycles +void delay_cyc(uint32_t cycles) +{ + while (cycles) + { + cycles--; + } +} + + + +//Copy string +void copy_string(char *from, char *to) +{ + while (*from) + { + *to++ = *from++; + } + *to = 0; //end terminator +} + + + +//Converts string to float +float atof32(char *input) +{ + uint8_t i = 0; + int32_t sign = 1; + float power = 1.0; + float result = 0.0; + + if(input[0] == 0) + { + return 0.0; + } + + if(input[i] == '-') + { + sign = -1; + i++; + } + + while(input[i] != '.') + { + result = result * 10.0 + (input[i] - '0'); + i++; + } + + i++; + + while(input[i] != 0) + { + result = result * 10.0 + (input[i] - '0'); + power *= 10.0; + i++; + } + + return (sign * result / power); +} + + + +//Converts float to string +void ftoa32(float value, uint8_t precision, char *buffer) +{ + uint8_t i = 0; + uint32_t mod = 0; + float pow = 1.0; + char sgn = 0; + float value_copy; + + if((value == 0.0) || (value == -0.0)) + { + buffer[0] = '0'; + buffer[1] = 0; + return; + } + + if(value < 0) + { + sgn = '-'; + value *= -1.0; + } + + value_copy = value; + + for(uint8_t p = 0; p < precision; p++) + { + pow = pow * 10.0; + } + + value = value * pow; + uint32_t ipart = value; + + buffer[i++] = 0; + + do + { + mod = ipart % 10; + ipart /= 10; + buffer[i++] = mod + '0'; + } + while(ipart > 0); + + if (value_copy < 1.0) + { + for(uint8_t p = 0; p < precision; p++) + { + buffer[i] = '0'; + i++; + } + } + + if(sgn == '-') + { + buffer[i] = sgn; + } + else + { + i--; + } + + for(uint8_t n = i + 1; n > precision + 1; n--) + { + buffer[n] = buffer[n - 1]; + } + buffer[precision + 1] = '.'; + i++; + + char c; + for(uint8_t j = 0; j < i; j++, i--) + { + c = buffer[j]; + buffer[j] = buffer[i]; + buffer[i] = c; + } +} + + + +//Converts string to integer +int32_t atoi32(char *input) +{ + uint8_t i = 0; + int32_t sign = 1; + int32_t result = 0; + + if(input[0] == 0) + { + return 0; + } + + if((input[0] == '0') && (input[1] == 0)) + { + return 0; + } + + if(input[i] == '-') + { + sign = -1; + i++; + } + + while(input[i] != 0) + { + result = result * 10 + (input[i] - '0'); + i++; + } + + return result * sign; +} + + + +//Converts integer to string +void itoa32(int32_t value, char *buffer) +{ + uint8_t i = 0; + uint8_t mod = 0; + char sgn = 0; + + if(value == 0) + { + buffer[0] = '0'; + buffer[1] = 0; + return; + } + + if(value < 0) + { + sgn = '-'; + value *= -1; + } + + buffer[i++] = 0; + + while(value > 0) + { + mod = value % 10; + value /= 10; + buffer[i++] = mod + '0'; + } + + if(sgn == '-') + { + buffer[i] = sgn; + } + else + { + i--; + } + + char c; + for(uint8_t j = 0; j < i; j++, i--) + { + c = buffer[j]; + buffer[j] = buffer[i]; + buffer[i] = c; + } +} diff --git a/Firmware/CubeIDE/Code/src/settings.c b/Firmware/CubeIDE/Code/src/settings.c new file mode 100644 index 0000000..fd07d65 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/settings.c @@ -0,0 +1,174 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: m24c64.c +*/ + +#include "stm32f10x.h" +#include "main.h" +#include "settings.h" +#include "m24c64.h" +#include "si4463.h" + + + +#define SEND_INTERVAL_1S_VALUE (1) +#define SEND_INTERVAL_5S_VALUE (5) +#define SEND_INTERVAL_10S_VALUE (10) +#define SEND_INTERVAL_30S_VALUE (30) +#define SEND_INTERVAL_60S_VALUE (60) + +#define SEND_INTERVAL_VALUES_ARRAY { SEND_INTERVAL_1S_VALUE, \ + SEND_INTERVAL_5S_VALUE, \ + SEND_INTERVAL_10S_VALUE, \ + SEND_INTERVAL_30S_VALUE, \ + SEND_INTERVAL_60S_VALUE } + + + +#define TX_POWER_10MILLIW_VALUE (10) +#define TX_POWER_25MILLIW_VALUE (25) +#define TX_POWER_40MILLIW_VALUE (40) +#define TX_POWER_100MILLIW_VALUE (100) + +#define TX_POWER_VALUES_ARRAY { TX_POWER_10MILLIW_VALUE, \ + TX_POWER_25MILLIW_VALUE, \ + TX_POWER_40MILLIW_VALUE, \ + TX_POWER_100MILLIW_VALUE } + + + +#define EEPROM_SETTINGS_PAGE_ADDRESS (0) + + + +//positions: +#define SETTINGS_INIT_FLAG_POS (0) +#define SETTINGS_DEVICE_NUMBER_POS (1) +#define SETTINGS_DEVICE_ID_POS (2) +#define SETTINGS_FREQ_CHANNEL_POS (4) +#define SETTINGS_TX_POWER_POS (5) +#define SETTINGS_SEND_INTERVAL_POS (6) +#define SETTINGS_TIMEOUT_THRESHOLD_POS (7) +#define SETTINGS_FENCE_THRESHOLD_POS (9) + +//default values: +#define SETTINGS_INIT_FLAG_DEFAULT (0xAA) +#define SETTINGS_DEVICE_NUMBER_DEFAULT (1) +#define SETTINGS_DEVICE_ID_0_DEFAULT ('I') +#define SETTINGS_DEVICE_ID_1_DEFAULT ('D') +#define SETTINGS_FREQ_CHANNEL_DEFAULT (1) //base freq is 433.050 and freq step is 25kHz, so CH0 - 433.050 (not valid, not used); CH1 - 433.075 (first LPD channel) +#define SETTINGS_TX_POWER_DEFAULT (TX_POWER_10MILLIW_SETTING) +#define SETTINGS_SEND_INTERVAL_DEFAULT (SEND_INTERVAL_1S_SETTING) +#define SETTINGS_TIMEOUT_THRESHOLD_DEFAULT (60) +#define SETTINGS_FENCE_THRESHOLD_DEFAULT (100) + + + +uint8_t settings_array[M24C64_PAGE_SIZE]; +struct settings_struct settings; +uint8_t send_interval_values[] = SEND_INTERVAL_VALUES_ARRAY; +uint8_t tx_power_values[] = TX_POWER_VALUES_ARRAY; + + + +uint8_t *get_send_interval_values(void) +{ + return &send_interval_values[0]; +} + + + +uint8_t *get_tx_power_values(void) +{ + return &tx_power_values[0]; +} + + + +struct settings_struct *get_settings(void) +{ + return &settings; +} + + + +void settings_load(void) +{ + uint16_t init_flag_addr = EEPROM_SETTINGS_PAGE_ADDRESS * M24C64_PAGE_SIZE + SETTINGS_INIT_FLAG_POS; + + if (m24c64_read_byte(init_flag_addr) != SETTINGS_INIT_FLAG_DEFAULT) //if first power-up or EEPROM had been erased + { + settings_save_default(); + } + + //read from EEPROM + m24c64_read_page(&settings_array[0], EEPROM_SETTINGS_PAGE_ADDRESS); + + //load settings to struct + settings.device_number = settings_array[SETTINGS_DEVICE_NUMBER_POS]; + settings.device_id[0] = settings_array[SETTINGS_DEVICE_ID_POS]; + settings.device_id[1] = settings_array[SETTINGS_DEVICE_ID_POS + 1]; + settings.freq_channel = settings_array[SETTINGS_FREQ_CHANNEL_POS]; + settings.tx_power_opt = settings_array[SETTINGS_TX_POWER_POS]; + settings.send_interval_opt = settings_array[SETTINGS_SEND_INTERVAL_POS]; + settings.timeout_threshold.as_array[0] = settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS]; + settings.timeout_threshold.as_array[1] = settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS + 1]; + settings.fence_threshold.as_array[0] = settings_array[SETTINGS_FENCE_THRESHOLD_POS]; + settings.fence_threshold.as_array[1] = settings_array[SETTINGS_FENCE_THRESHOLD_POS + 1]; +} + + + +void settings_save_default(void) +{ + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + { + settings_array[i] = M24C64_EMPTY_CELL_VALUE; //clear array + } + + //assign default values + settings_array[SETTINGS_INIT_FLAG_POS] = SETTINGS_INIT_FLAG_DEFAULT; + settings_array[SETTINGS_DEVICE_NUMBER_POS] = SETTINGS_DEVICE_NUMBER_DEFAULT; + settings_array[SETTINGS_DEVICE_ID_POS] = SETTINGS_DEVICE_ID_0_DEFAULT; + settings_array[SETTINGS_DEVICE_ID_POS + 1] = SETTINGS_DEVICE_ID_1_DEFAULT; + settings_array[SETTINGS_FREQ_CHANNEL_POS] = SETTINGS_FREQ_CHANNEL_DEFAULT; + settings_array[SETTINGS_TX_POWER_POS] = SETTINGS_TX_POWER_DEFAULT; + settings_array[SETTINGS_SEND_INTERVAL_POS] = SETTINGS_SEND_INTERVAL_DEFAULT; + settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS] = (uint8_t)((uint8_t)0xFF & (uint16_t)SETTINGS_TIMEOUT_THRESHOLD_DEFAULT); //note: little-endian assumed + settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS + 1]= (uint8_t)((uint8_t)0xFF & ((uint16_t)SETTINGS_TIMEOUT_THRESHOLD_DEFAULT >> 8)); + settings_array[SETTINGS_FENCE_THRESHOLD_POS] = (uint8_t)((uint8_t)0xFF & (uint16_t)SETTINGS_FENCE_THRESHOLD_DEFAULT); //note: little-endian assumed + settings_array[SETTINGS_FENCE_THRESHOLD_POS + 1] = (uint8_t)((uint8_t)0xFF & ((uint16_t)SETTINGS_FENCE_THRESHOLD_DEFAULT >> 8)); + + //write to EEPROM + m24c64_write_page(&settings_array[0], EEPROM_SETTINGS_PAGE_ADDRESS); +} + + + +void settings_save(struct settings_struct *p_settings) +{ + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + { + settings_array[i] = M24C64_EMPTY_CELL_VALUE; //clear array + } + + //assign values + settings_array[SETTINGS_INIT_FLAG_POS] = SETTINGS_INIT_FLAG_DEFAULT; + settings_array[SETTINGS_DEVICE_NUMBER_POS] = p_settings->device_number; + settings_array[SETTINGS_DEVICE_ID_POS] = p_settings->device_id[0]; + settings_array[SETTINGS_DEVICE_ID_POS + 1] = p_settings->device_id[1]; + settings_array[SETTINGS_FREQ_CHANNEL_POS] = p_settings->freq_channel; + settings_array[SETTINGS_TX_POWER_POS] = p_settings->tx_power_opt; + settings_array[SETTINGS_SEND_INTERVAL_POS] = p_settings->send_interval_opt; + settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS] = p_settings->timeout_threshold.as_array[0]; + settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS + 1]= p_settings->timeout_threshold.as_array[1]; + settings_array[SETTINGS_FENCE_THRESHOLD_POS] = p_settings->fence_threshold.as_array[0]; + settings_array[SETTINGS_FENCE_THRESHOLD_POS + 1] = p_settings->fence_threshold.as_array[1]; + + //write to EEPROM + m24c64_write_page(&settings_array[0], EEPROM_SETTINGS_PAGE_ADDRESS); +} diff --git a/Firmware/CubeIDE/Code/src/si4463.c b/Firmware/CubeIDE/Code/src/si4463.c new file mode 100644 index 0000000..11a9c7d --- /dev/null +++ b/Firmware/CubeIDE/Code/src/si4463.c @@ -0,0 +1,275 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: si4463.c +*/ + +#include "stm32f10x.h" +#include "si4463.h" +#include "radio_config_Si4463.h" +#include "gpio.h" +#include "spi.h" +#include "service.h" +#include "main.h" +#include "settings.h" + + + +void si4463_wait_cts(void); +void si4463_set_packet_len(uint8_t packet_len); +void si4463_set_tx_power(uint8_t tx_pow_reg_val); + + + +#define SI4463_BYTE_DUMMY (0x00) +#define SI4463_CMD_FIFO_INFO (0x15) +#define SI4463_CMD_WRITE_TX_FIFO (0x66) +#define SI4463_CMD_READ_RX_FIFO (0x77) +#define SI4463_CMD_START_TX (0x31) +#define SI4463_CMD_START_RX (0x32) +#define SI4463_CMD_CHANGE_STATE (0x34) +#define SI4463_CMD_GET_PH_STATUS (0x21) +#define SI4463_CMD_READ_CMD_BUF (0x44) +#define SI4463_CMD_SET_PROPERTY (0x11) + +#define SI4463_FIFO_INFO_TX_BIT (0x01) +#define SI4463_FIFO_INFO_RX_BIT (0x02) +#define SI4463_PH_PEND_CRC_ERROR_BIT (0x08) +#define SI4463_PH_PEND_PACKET_RX_BIT (0x10) + +#define SI4463_NOCHANGE_STATE (0x00) +#define SI4463_SLEEP_STATE (0x01) +#define SI4463_READY_STATE (0x03) + +#define SI4463_PKT_FIELD_1_LENGTH_GROUP_ID (0x12) +#define SI4463_PKT_FIELD_1_LENGTH_NUM_PROPS (0x02) +#define SI4463_PKT_FIELD_1_LENGTH_START_PROP (0x0D) + +#define SI4463_PA_PWR_LVL_GROUP_ID (0x22) +#define SI4463_PA_PWR_LVL_NUM_PROPS (0x01) +#define SI4463_PA_PWR_LVL_START_PROP (0x01) + +#define TX_POWER_10MILLIW_REGISTER_VALUE (20) //see datasheet graph +#define TX_POWER_25MILLIW_REGISTER_VALUE (30) +#define TX_POWER_40MILLIW_REGISTER_VALUE (40) +#define TX_POWER_100MILLIW_REGISTER_VALUE (127) + +#define TX_POWER_REGISTER_VALUES_ARRAY { TX_POWER_10MILLIW_REGISTER_VALUE, \ + TX_POWER_25MILLIW_REGISTER_VALUE, \ + TX_POWER_40MILLIW_REGISTER_VALUE, \ + TX_POWER_100MILLIW_REGISTER_VALUE } + +#define AIR_PACKET_LEN (17) //bytes amount to tx/rx over air; does not include two bytes of CRC (refer to "radio_config_Si4463.h") + + + +uint8_t air_packet_tx[AIR_PACKET_LEN]; +uint8_t air_packet_rx[AIR_PACKET_LEN]; +struct settings_struct *p_settings; +uint8_t tx_power_register_values[] = TX_POWER_REGISTER_VALUES_ARRAY; + + + +//SI4463 Init +void si4463_init(void) +{ + cs_si4463_inactive(); //set pins initial state + sdn_si4463_inactive(); + delay_cyc(1000000); + + sdn_si4463_active(); //reset the chip + delay_cyc(1000000); + sdn_si4463_inactive(); + + uint8_t init_arr[] = RADIO_CONFIGURATION_DATA_ARRAY; //array with init data, generated by WDS software + uint8_t *p_init_arr = &init_arr[0]; //pointer to the array + + //Send all commands while pointer not equal 0x00 (0x00 presented in the end of the configuration array) + while(*p_init_arr != 0x00) + { + uint8_t len = *p_init_arr; //command len (first byte of the each line in configuration array) + p_init_arr++; //move pointer to the first data byte (which is next after the command len) + + si4463_wait_cts(); //check cts before any command + cs_si4463_active(); + for(uint8_t i = 0; i < len; i++) + { + spi1_trx(*p_init_arr); //send command byte + p_init_arr++; //move pointer to the next byte in command + } + cs_si4463_inactive(); + } + + //Set len of the packet + si4463_set_packet_len(AIR_PACKET_LEN); + + //Get current settings + p_settings = get_settings(); + + //Set TX power + si4463_set_tx_power(tx_power_register_values[p_settings->tx_power_opt]); +} + + + +//Wait for hardware CTS pin +void si4463_wait_cts(void) +{ + while(!(GPIOA->IDR & GPIO_IDR_IDR12)){} //while GPIO1 = 0 +} + + + +//Set air packet length +void si4463_set_packet_len(uint8_t packet_len) +{ + si4463_wait_cts(); + cs_si4463_active(); + spi1_trx(SI4463_CMD_SET_PROPERTY); + spi1_trx(SI4463_PKT_FIELD_1_LENGTH_GROUP_ID); + spi1_trx(SI4463_PKT_FIELD_1_LENGTH_NUM_PROPS); + spi1_trx(SI4463_PKT_FIELD_1_LENGTH_START_PROP); + spi1_trx(0x00); //packet len high byte + spi1_trx(packet_len); //packet len low byte + cs_si4463_inactive(); +} + + + +void si4463_set_tx_power(uint8_t tx_pow_reg_val) +{ + si4463_wait_cts(); + cs_si4463_active(); + spi1_trx(SI4463_CMD_SET_PROPERTY); + spi1_trx(SI4463_PA_PWR_LVL_GROUP_ID); + spi1_trx(SI4463_PA_PWR_LVL_NUM_PROPS); + spi1_trx(SI4463_PA_PWR_LVL_START_PROP); + spi1_trx(tx_pow_reg_val); + cs_si4463_inactive(); +} + + + +//SI4463 TX packet +void si4463_tx_packet(void) +{ + //reset TX FIFO + si4463_wait_cts(); + cs_si4463_active(); + spi1_trx(SI4463_CMD_FIFO_INFO); + spi1_trx(SI4463_FIFO_INFO_TX_BIT); + cs_si4463_inactive(); + + //fill TX FIFO buffer + si4463_wait_cts(); + cs_si4463_active(); + spi1_trx(SI4463_CMD_WRITE_TX_FIFO); + for (uint8_t i = 0; i < AIR_PACKET_LEN; i++) + { + spi1_trx(air_packet_tx[i]); + } + cs_si4463_inactive(); + + //start TX + si4463_wait_cts(); + cs_si4463_active(); + spi1_trx(SI4463_CMD_START_TX); + spi1_trx(p_settings->freq_channel); //frequency channel + spi1_trx(SI4463_SLEEP_STATE << 4); //return to sleep state, send FIFO content, start TX immediately + spi1_trx(0x00); //the number of data bytes to be transmitted + spi1_trx(0x00); //is specified by the value(s) of the PKT_FIELD_X_LENGTH properties + cs_si4463_inactive(); +} + + + +//SI4463 start packet RX +void si4463_start_rx(void) +{ + si4463_wait_cts(); + cs_si4463_active(); + spi1_trx(SI4463_CMD_START_RX); + spi1_trx(p_settings->freq_channel); //frequency channel + spi1_trx(0x00); //start RX immediately + spi1_trx(0x00); //RX packet len is specified + spi1_trx(0x00); //in packet handler configuration + spi1_trx(SI4463_SLEEP_STATE); //if RX timeout then go to sleep (after RX_PREAMBLE_TIMEOUT) + spi1_trx(SI4463_SLEEP_STATE); //if RX valid then go to sleep + spi1_trx(SI4463_SLEEP_STATE); //if RX invalid then go to sleep + cs_si4463_inactive(); +} + + + +//SI4463 get received packet +uint8_t si4463_get_rx_packet(void) +{ + uint8_t ph_pending = 0; + + //send get PH status command + si4463_wait_cts(); + cs_si4463_active(); + spi1_trx(SI4463_CMD_GET_PH_STATUS); + spi1_trx(SI4463_BYTE_DUMMY); //also clear all pending interrupts + cs_si4463_inactive(); + + //retrieve response + si4463_wait_cts(); + cs_si4463_active(); + spi1_trx(SI4463_CMD_READ_CMD_BUF); + spi1_trx(SI4463_BYTE_DUMMY); //skip CTS byte + ph_pending = spi1_trx(SI4463_BYTE_DUMMY); + cs_si4463_inactive(); + + if (ph_pending & SI4463_PH_PEND_CRC_ERROR_BIT) + { + si4463_wait_cts(); //clear RX FIFO content + cs_si4463_active(); + spi1_trx(SI4463_CMD_FIFO_INFO); + spi1_trx(SI4463_FIFO_INFO_RX_BIT); + cs_si4463_inactive(); + + si4463_wait_cts(); //workaround if received packet has CRC error (see si4463 revB1 errata) + cs_si4463_active(); + spi1_trx(SI4463_CMD_CHANGE_STATE); + spi1_trx(SI4463_SLEEP_STATE); + cs_si4463_inactive(); + + return 0; + } + else if (ph_pending & SI4463_PH_PEND_PACKET_RX_BIT) + { + //read RX FIFO buffer + si4463_wait_cts(); + cs_si4463_active(); + spi1_trx(SI4463_CMD_READ_RX_FIFO); + for (uint8_t i = 0; i < AIR_PACKET_LEN; i++) + { + air_packet_rx[i] = spi1_trx(SI4463_BYTE_DUMMY); + } + cs_si4463_inactive(); + + return 1; + } + else + { + return 0; + } +} + + + +uint8_t *get_air_packet_tx(void) +{ + return &air_packet_tx[0]; +} + + + +uint8_t *get_air_packet_rx(void) +{ + return &air_packet_rx[0]; +} diff --git a/Firmware/CubeIDE/Code/src/spi.c b/Firmware/CubeIDE/Code/src/spi.c new file mode 100644 index 0000000..ef1796a --- /dev/null +++ b/Firmware/CubeIDE/Code/src/spi.c @@ -0,0 +1,68 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: spi.c +*/ + +#include "stm32f10x.h" +#include "spi.h" + + + +//Init SPI1 +void spi1_init(void) +{ + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; //enable clock spi1 + RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; //enable alternate function clock + AFIO->MAPR |= AFIO_MAPR_SPI1_REMAP; //remap spi + AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_JTAGDISABLE; //disable JTAG + SPI1->CR1 &= ~SPI_CR1_BR; //clock/2 + SPI1->CR1 |= SPI_CR1_SSM; + SPI1->CR1 |= SPI_CR1_SSI; + SPI1->CR1 |= SPI_CR1_MSTR; //master mode + SPI1->CR1 &= ~SPI_CR1_CPOL; //SCK = 0 in IDLE + SPI1->CR1 &= ~SPI_CR1_CPHA; //first rising edge capture + SPI1->CR1 |= SPI_CR1_SPE; //enable spi +} + + + +//Init SPI2 +void spi2_init(void) +{ + RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; //enable clock spi2 + SPI2->CR1 &= ~SPI_CR1_BR; //clock/2 + SPI2->CR1 |= SPI_CR1_SSM; + SPI2->CR1 |= SPI_CR1_SSI; + SPI2->CR1 |= SPI_CR1_MSTR; //master mode + SPI2->CR1 &= ~SPI_CR1_CPOL; //SCK = 0 in IDLE + SPI2->CR1 &= ~SPI_CR1_CPHA; //first rising edge capture + SPI2->CR1 |= SPI_CR1_SPE; //enable spi +} + + + +//TRX one byte via SPI1 +uint8_t spi1_trx(uint8_t send_data) +{ + while(!(SPI1->SR & SPI_SR_TXE)){} //while TXE bit = 0 + SPI1->DR = send_data; + + while(!(SPI1->SR & SPI_SR_RXNE)){} //while RXNE = 0 + return SPI1->DR; +} + + + +//TRX one byte via SPI2 +uint8_t spi2_trx(uint8_t send_data) +{ + while (!(SPI2->SR & SPI_SR_TXE)){} //while TXE bit = 0 + SPI2->DR = send_data; + + while (!(SPI2->SR & SPI_SR_RXNE)){} //while RXNE = 0 + return SPI2->DR; +} diff --git a/Firmware/CubeIDE/Code/src/ssd1306.c b/Firmware/CubeIDE/Code/src/ssd1306.c new file mode 100644 index 0000000..25ae97a --- /dev/null +++ b/Firmware/CubeIDE/Code/src/ssd1306.c @@ -0,0 +1,236 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: ssd1306.c +*/ + +#include "stm32f10x.h" +#include "ssd1306.h" +#include "ssd1306_font6x8.h" +#include "gpio.h" +#include "spi.h" +#include "service.h" + + + +#define LCD_SIZE_BYTES (1024) +#define LCD_SIZE_X (128) +#define LCD_SIZE_Y (64) +#define FONT_SIZE_X (6) +#define FONT_SIZE_Y (8) + + + +uint8_t screen_buf[LCD_SIZE_BYTES]; //public array 128x64 pixels +uint16_t buf_pos = 0; //public var 0 - 1023 + + + +//SSD1306 init sequence (first byte in line = amount of config bytes in line) +const uint8_t ssd1306_conf[] = +{ + 0x02, 0x20, 0x00, /* horizontal adressing */ \ + 0x02, 0xA1, 0xC8, /* invert orientation */ \ + 0x03, 0x8D, 0x14, 0xAF, /* enable charge pump and display */ \ + 0x00 /* end of the sequence */ +}; + + + +//SSD1306 Init +void ssd1306_init(void) +{ + cs_ssd1306_inactive(); //ports init state + res_ssd1306_inactive(); + ssd1306_command_mode(); + delay_cyc(100000); + + res_ssd1306_active(); //reset ssd1306 + delay_cyc(100000); + res_ssd1306_inactive(); + delay_cyc(100000); + + uint8_t i = 0; + uint8_t len = 0; + while (ssd1306_conf[i] != 0x00) + { + len = ssd1306_conf[i++]; + + cs_ssd1306_active(); + while (len--) + { + spi2_trx(ssd1306_conf[i++]); + } + cs_ssd1306_inactive(); + } + + ssd1306_clear(); + ssd1306_update(); +} + + + +//Update screen with buffer content +void ssd1306_update(void) +{ + ssd1306_data_mode(); + cs_ssd1306_active(); + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + { + spi2_trx(screen_buf[i]); + } + cs_ssd1306_inactive(); +} + + + +//Fill all screen pixels +void ssd1306_fill(void) +{ + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + { + screen_buf[i] = 0xFF; + } +} + + + +//Clear all screen pixels +void ssd1306_clear(void) +{ + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + { + screen_buf[i] = 0x00; + } +} + + + +//Clear, Set or Reset any pixel on the screen (x 0-127, y 0-63) +void ssd1306_pixel(uint8_t x, uint8_t y, int8_t action) +{ + switch (action) + { + case 0: //clear pixel + screen_buf[x + (y / 8) * LCD_SIZE_X] &= ~(1 << (y % 8)); + break; + case 1: //set pixel + screen_buf[x + (y / 8) * LCD_SIZE_X] |= 1 << (y % 8); + break; + default: //invert pixel + screen_buf[x + (y / 8) * LCD_SIZE_X] ^= 1 << (y % 8); + break; + } +} + + + +//Set character position on screen (rows 0-7, cols 0-20) +void ssd1306_pos(uint8_t row, uint8_t col) +{ + buf_pos = (row * 21 + col) * FONT_SIZE_X + 2 * row; //+2 bytes, because 128 - 21 * 6 = 2 +} + + + +//Put one char in buffer in position, defined previously via ssd1306_pos() +void ssd1306_char(char chr, uint8_t inv) +{ + if (inv) + { + inv = 0xFF; + } + else + { + inv = 0x00; + } + + for (uint8_t i = 0; i < FONT_SIZE_X - 1; i++) + { + screen_buf[buf_pos++] = font[(uint8_t)chr][i] ^ inv; + } + screen_buf[buf_pos++] = 0x00 ^ inv; //intercharacter space +} + + + +//Put one char in defined pos +void ssd1306_char_pos(uint8_t row, uint8_t col, char chr, uint8_t inv) +{ + ssd1306_pos(row, col); + ssd1306_char(chr, inv); +} + + + +//Print string on screen (with position) +void ssd1306_print(uint8_t row, uint8_t col, char *p_str, uint8_t inv) +{ + ssd1306_pos(row, col); + + while (*p_str) + { + ssd1306_char(*p_str++, inv); + } +} + + + +//Print string on screen (with position) in viceversa direction (decrease collumn) +void ssd1306_print_viceversa(uint8_t row, uint8_t col, char *p_str, uint8_t inv) +{ + uint8_t symb_cntr = 0; + + ssd1306_pos(row, col); + + while (*p_str) + { + p_str++; + symb_cntr++; + } + + while (symb_cntr) + { + symb_cntr--; + ssd1306_char(*--p_str, inv); + buf_pos -= 2 * FONT_SIZE_X; //minus two characters position + } +} + + + +//Print string on screen +void ssd1306_print_next(char *p_str, uint8_t inv) +{ + while (*p_str) + { + ssd1306_char(*p_str++, inv); + } +} + + + +//Show bitmap +void ssd1306_bitmap(const uint8_t arr[]) +{ + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + { + screen_buf[i] = arr[i]; + } +} + + + +//Print byte on screen (debug function) +void ssd1306_print_byte(uint8_t row, uint8_t col, uint8_t *p_byte, uint8_t amount) +{ + ssd1306_pos(row, col); + + while (amount--) + { + screen_buf[buf_pos++] = *p_byte++; + } +} diff --git a/Firmware/CubeIDE/Code/src/ssd1306_bitmaps.c b/Firmware/CubeIDE/Code/src/ssd1306_bitmaps.c new file mode 100644 index 0000000..3a8a997 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/ssd1306_bitmaps.c @@ -0,0 +1,538 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: ssd1306_bitmaps.c +*/ + +#include "stm32f10x.h" + + + +const uint8_t startup_screen[1024] = +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0xFF, + 0x89, 0x9D, 0x81, 0xC3, 0x00, 0x00, 0x81, 0xFF, + 0x81, 0x80, 0xE0, 0x00, 0x81, 0xFF, 0x89, 0x9D, + 0x81, 0xC3, 0x00, 0x00, 0x81, 0xFF, 0x91, 0x11, + 0x0E, 0x00, 0x81, 0xFF, 0x89, 0x08, 0x89, 0xFF, + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0xC0, 0x60, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x60, 0x30, 0x10, 0x18, 0x08, 0x08, 0x08, + 0x08, 0x08, 0x18, 0x10, 0x30, 0x60, 0x40, 0x60, + 0x20, 0x20, 0x20, 0x20, 0x60, 0xC0, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, + 0x0F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, + 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x0F, 0x18, 0x30, 0x40, 0xC0, 0x80, 0x80, 0x80, + 0x80, 0xC0, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0xC0, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0x60, 0x38, + 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x0C, 0x06, 0x03, 0x03, 0x06, 0x3C, 0xE0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x06, 0x04, + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xB0, + 0x90, 0x70, 0x10, 0x10, 0x10, 0x10, 0x10, 0x30, + 0x20, 0x30, 0x10, 0x18, 0x08, 0x0E, 0x03, 0x80, + 0xC0, 0x60, 0x30, 0x1C, 0x07, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + + +const uint8_t devices_blank[1024] = +{ 0x7F, 0x6B, 0x41, 0x6B, 0x41, 0x6B, 0x7F, 0x00, + 0x00, 0x00, 0x00, 0x7F, 0x5D, 0x5D, 0x41, 0x5D, + 0x5D, 0x7F, 0x41, 0x5D, 0x5D, 0x5D, 0x63, 0x7F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x51, 0x55, + 0x55, 0x55, 0x45, 0x7F, 0x41, 0x5D, 0x5D, 0x5D, + 0x41, 0x7F, 0x41, 0x5D, 0x5D, 0x55, 0x45, 0x7F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x41, 0x5D, + 0x5D, 0x5D, 0x5D, 0x7F, 0x41, 0x5D, 0x5D, 0x5D, + 0x41, 0x7F, 0x41, 0x5D, 0x5D, 0x55, 0x45, 0x7F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x43, 0x75, + 0x75, 0x75, 0x43, 0x7F, 0x43, 0x75, 0x75, 0x75, + 0x43, 0x7F, 0x41, 0x5F, 0x5F, 0x5F, 0x5F, 0x7F, + 0x7D, 0x7D, 0x41, 0x7D, 0x7D, 0x7F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7F, 0x6B, 0x41, 0x6B, 0x41, 0x6B, 0x7F, 0x00, + 0x00, 0x00, 0x00, 0x7F, 0x5D, 0x5D, 0x41, 0x5D, + 0x5D, 0x7F, 0x41, 0x5D, 0x5D, 0x5D, 0x63, 0x7F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x41, 0x5D, + 0x5D, 0x5D, 0x63, 0x7F, 0x51, 0x55, 0x55, 0x55, + 0x45, 0x7F, 0x7D, 0x7D, 0x41, 0x7D, 0x7D, 0x7F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x41, 0x55, + 0x55, 0x55, 0x6B, 0x7F, 0x41, 0x6D, 0x6D, 0x6D, + 0x53, 0x7F, 0x41, 0x5D, 0x5D, 0x55, 0x45, 0x7F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x41, 0x5D, + 0x5D, 0x5D, 0x63, 0x7F, 0x43, 0x75, 0x75, 0x75, + 0x43, 0x7F, 0x41, 0x5F, 0x5F, 0x5F, 0x5F, 0x7F, + 0x7D, 0x7D, 0x41, 0x7D, 0x7D, 0x7F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + + +const uint8_t radar_blank[1024] = +{ 0x00, 0x00, 0x7F, 0x41, 0x5D, 0x5D, 0x5D, 0x5D, + 0x7F, 0x41, 0x5D, 0x5D, 0x5D, 0x41, 0x7F, 0x41, + 0x5D, 0x5D, 0x55, 0x45, 0x7F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xFE, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x6B, 0x41, + 0x6B, 0x41, 0x6B, 0x7F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x7F, 0x5D, 0x5D, 0x41, 0x5D, 0x5D, 0x7F, + 0x41, 0x5D, 0x5D, 0x5D, 0x63, 0x7F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x7F, 0x41, 0x5D, 0x5D, 0x5D, + 0x63, 0x7F, 0x51, 0x55, 0x55, 0x55, 0x45, 0x7F, + 0x7D, 0x7D, 0x41, 0x7D, 0x7D, 0x7F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x7F, 0x41, 0x55, 0x55, 0x55, + 0x6B, 0x7F, 0x41, 0x6D, 0x6D, 0x6D, 0x53, 0x7F, + 0x41, 0x5D, 0x5D, 0x55, 0x45, 0x7F, 0x00, 0x00, + 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x3F, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3F, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x7F, 0x41, 0x6D, 0x6D, 0x6D, 0x53, + 0x7F, 0x41, 0x7B, 0x77, 0x6F, 0x41, 0x7F, 0x41, + 0x5D, 0x5D, 0x55, 0x45, 0x7F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + + +const uint8_t info_blank[1024] = +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, + 0x30, 0x18, 0x0C, 0x04, 0x04, 0x04, 0x04, 0x04, + 0x0C, 0x06, 0x02, 0x03, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x03, 0x02, 0x06, 0x0C, 0x08, 0x0C, 0x04, + 0x04, 0x04, 0x04, 0x0C, 0x18, 0x30, 0x60, 0xC0, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xE1, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x03, 0x06, 0x08, 0x18, 0x10, 0x10, 0x10, 0x90, + 0xD8, 0x7C, 0x70, 0xC0, 0x80, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xF0, 0x70, 0xD8, 0x90, 0x90, + 0x10, 0x10, 0x10, 0x10, 0x18, 0x0C, 0x07, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, + 0x00, 0x00, 0x00, 0x00, 0xC7, 0x7C, 0x00, 0x00, + 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x36, 0x32, + 0x2E, 0x22, 0x22, 0x22, 0x22, 0x22, 0x26, 0x24, + 0x26, 0x22, 0x23, 0x21, 0x21, 0x20, 0x30, 0x18, + 0x0C, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; diff --git a/Firmware/CubeIDE/Code/src/timer.c b/Firmware/CubeIDE/Code/src/timer.c new file mode 100644 index 0000000..42b4780 --- /dev/null +++ b/Firmware/CubeIDE/Code/src/timer.c @@ -0,0 +1,166 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: timer.c +*/ + +#include "stm32f10x.h" +#include "timer.h" +#include "gpio.h" + + + +void systick_init(void); +void timer1_init(void); +void timer2_init(void); +void timer2_start(void); +void timer3_init(void); +void timer3_start(void); + + + +uint8_t beep_mute = 0; + + + +//Init all timers together +void timers_init(void) +{ + systick_init(); + timer1_init(); + timer2_init(); + timer3_init(); +} + + + +void make_a_beep(void) +{ + led_board_on(); + timer2_start(); //in order to switch off led_board + + if (beep_mute == 0) + { + timer3_start(); + } +} + + + +void toggle_mute(void) +{ + beep_mute ^= (uint8_t)1; +} + + + +uint8_t get_mute_flag(void) +{ + return beep_mute; +} + + + +//SysTick timer init (tick every 1s to count uptime) +void systick_init(void) +{ + SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk; //clock source = AHB/8 = 72MHz/8 = 9MHz + SysTick->LOAD = (uint32_t)8999999; //9000000Hz-1 + SysTick->VAL = 0; //reset counter value + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; //enable interrupt + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; //enable counter +} + + + +//Timer1 init (time slot counter) +void timer1_init(void) +{ + RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; //enable timer 1 clock + TIM1->PSC = (uint16_t)35999; // 72MHz/(35999+1)=2kHz + TIM1->ARR = (uint16_t)199; // 2kHz/(199+1)=10Hz(100ms) + TIM1->CR1 |= TIM_CR1_URS; //only overflow generates interrupt + TIM1->EGR = TIM_EGR_UG; //software update generation + TIM1->SR &= ~TIM_SR_UIF; //clear update interrupt + TIM1->DIER |= TIM_DIER_UIE; //update interrupt enable + + NVIC_EnableIRQ(TIM1_UP_IRQn); //enable interrupt +} + + + +//Timer1 start +void timer1_start(void) +{ + TIM1->CR1 |= TIM_CR1_CEN; //enable counter +} + + + +//Timer1 stop and reload +void timer1_stop_reload(void) +{ + TIM1->CR1 &= ~TIM_CR1_CEN; //disable counter + TIM1->EGR = TIM_EGR_UG; //software update generation +} + + + +//Timer 2 init (gating timer, the length of the "beep") +void timer2_init(void) +{ + RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; //enable timer clock + TIM2->PSC = (uint16_t)35999; //72MHz/(35999+1)=2kHz + TIM2->ARR = (uint16_t)199; //2kHz/(199+1)=10Hz(100ms) + TIM2->EGR = TIM_EGR_UG; //software update generation + TIM2->DIER |= TIM_DIER_UIE; //update interrupt enable + + NVIC_EnableIRQ(TIM2_IRQn); +} + + + +void timer2_stop(void) +{ + TIM2->CR1 &= ~TIM_CR1_CEN; //stop gating timer +} + + + +void timer2_start(void) +{ + TIM2->CR1 |= TIM_CR1_CEN; //start gating timer +} + + + +//Timer 3 init (pwm timer, the frequency of the "beep") +void timer3_init(void) +{ + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; //enable timer clock + TIM3->PSC = (uint16_t)8999; //72MHz/(8999+1)=8kHz + TIM3->ARR = (uint16_t)3; //8kHz/(3+1)=2kHz + TIM3->CCR2 = (uint16_t)2; //duty cycle 2/(3+1)=0.5 + TIM3->CCMR1 |= TIM_CCMR1_OC2M_2; //PWM mode 2 + TIM3->CCMR1 |= TIM_CCMR1_OC2M_1; + TIM3->CCMR1 |= TIM_CCMR1_OC2M_0; + TIM3->CCER |= TIM_CCER_CC2E; //CH2 output enable +} + + + +void timer3_stop(void) +{ + TIM3->CR1 &= ~TIM_CR1_CEN; //disable PWM timer + TIM3->CNT = 0; //force output low +} + + + +void timer3_start(void) +{ + TIM3->CR1 |= TIM_CR1_CEN; //enable PWM timer +} diff --git a/Firmware/CubeIDE/Code/src/uart.c b/Firmware/CubeIDE/Code/src/uart.c new file mode 100644 index 0000000..3f5412b --- /dev/null +++ b/Firmware/CubeIDE/Code/src/uart.c @@ -0,0 +1,87 @@ +/* + ELEPH - Local Relative Navigation System + + Copyright (C) 2021 Feruz Topalov + Released under the GNU General Public License v3.0 + + file: uart.c +*/ + +#include "stm32f10x.h" +#include "main.h" +#include "uart.h" +#include "gps.h" + + + +char uart_buffer[UART_BUF_LEN]; +char *backup_buf; + + + +//UART Init +void uart_dma_init(void) +{ + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; //ENABLE usart clock + + USART1->BRR = 0x1D4C; //9600 bod + USART1->CR1 |= USART_CR1_TE; //enable tx + USART1->CR1 |= USART_CR1_RE; //enable rx + USART1->CR1 |= USART_CR1_UE; //uart enable + + USART1->CR3 |= USART_CR3_DMAR; //enable DMA mode USART + RCC->AHBENR |= RCC_AHBENR_DMA1EN; //enable dma1 clock + + DMA1_Channel5->CPAR = (uint32_t)(&(USART1->DR)); //transfer source + DMA1_Channel5->CMAR = (uint32_t)(&uart_buffer[0]); //transfer destination + DMA1_Channel5->CNDTR = UART_BUF_LEN; //bytes amount to receive + + DMA1_Channel5->CCR |= DMA_CCR5_MINC; //enable memory increment + DMA1_Channel5->CCR |= DMA_CCR5_TCIE; //enable transfer complete interrupt + DMA1_Channel5->CCR |= DMA_CCR5_EN; //enable channel + + NVIC_EnableIRQ(DMA1_Channel5_IRQn); //enable interrupts + DMA1->IFCR = DMA_IFCR_CGIF5; //clear all interrupt flags for DMA channel 5 + + backup_buf = get_nmea_buf(); +} + + + +//Stop UART DMA +void uart_dma_stop(void) +{ + DMA1_Channel5->CCR &= ~DMA_CCR5_EN; //disable channel +} + + + +//Restart UART DMA +void uart_dma_restart(void) +{ + DMA1_Channel5->CNDTR = UART_BUF_LEN; //reload bytes amount to receive + DMA1_Channel5->CCR |= DMA_CCR5_EN; //enable channel +} + + + +//Backup uart buffer and then clear it +void backup_and_clear_uart_buffer(void) +{ + for (uint16_t i = 0; i < UART_BUF_LEN; i++) //copy received data to buffer and clear uart_buffer + { + backup_buf[i] = uart_buffer[i]; + uart_buffer[i] = 0; + } +} + + + +//UART Tx one byte +void uart_tx(uint8_t data) +{ + while (!(USART1->SR & USART_SR_TXE)) //wait for transmit register empty + { + } + USART1->DR = data; //transmit data +} diff --git a/Firmware/CubeIDE/Debug/CMSIS/src/core_cm3.d b/Firmware/CubeIDE/Debug/CMSIS/src/core_cm3.d new file mode 100644 index 0000000..38bfc72 --- /dev/null +++ b/Firmware/CubeIDE/Debug/CMSIS/src/core_cm3.d @@ -0,0 +1 @@ +CMSIS/src/core_cm3.o: ../CMSIS/src/core_cm3.c diff --git a/Firmware/CubeIDE/Debug/CMSIS/src/core_cm3.o b/Firmware/CubeIDE/Debug/CMSIS/src/core_cm3.o new file mode 100644 index 0000000..5886b62 Binary files /dev/null and b/Firmware/CubeIDE/Debug/CMSIS/src/core_cm3.o differ diff --git a/Firmware/CubeIDE/Debug/CMSIS/src/core_cm3.su b/Firmware/CubeIDE/Debug/CMSIS/src/core_cm3.su new file mode 100644 index 0000000..afa05be --- /dev/null +++ b/Firmware/CubeIDE/Debug/CMSIS/src/core_cm3.su @@ -0,0 +1,22 @@ +core_cm3.c:443:10:__get_PSP 0 static,ignoring_inline_asm +core_cm3.c:462:6:__set_PSP 0 static,ignoring_inline_asm +core_cm3.c:477:10:__get_MSP 0 static,ignoring_inline_asm +core_cm3.c:496:6:__set_MSP 0 static,ignoring_inline_asm +core_cm3.c:509:10:__get_BASEPRI 16 static,ignoring_inline_asm +core_cm3.c:524:6:__set_BASEPRI 16 static,ignoring_inline_asm +core_cm3.c:536:10:__get_PRIMASK 16 static,ignoring_inline_asm +core_cm3.c:551:6:__set_PRIMASK 16 static,ignoring_inline_asm +core_cm3.c:563:10:__get_FAULTMASK 16 static,ignoring_inline_asm +core_cm3.c:578:6:__set_FAULTMASK 16 static,ignoring_inline_asm +core_cm3.c:590:10:__get_CONTROL 16 static,ignoring_inline_asm +core_cm3.c:605:6:__set_CONTROL 16 static,ignoring_inline_asm +core_cm3.c:619:10:__REV 24 static,ignoring_inline_asm +core_cm3.c:635:10:__REV16 24 static,ignoring_inline_asm +core_cm3.c:651:9:__REVSH 24 static,ignoring_inline_asm +core_cm3.c:667:10:__RBIT 24 static,ignoring_inline_asm +core_cm3.c:683:9:__LDREXB 24 static,ignoring_inline_asm +core_cm3.c:699:10:__LDREXH 24 static,ignoring_inline_asm +core_cm3.c:715:10:__LDREXW 24 static,ignoring_inline_asm +core_cm3.c:732:10:__STREXB 24 static,ignoring_inline_asm +core_cm3.c:749:10:__STREXH 24 static,ignoring_inline_asm +core_cm3.c:766:10:__STREXW 24 static,ignoring_inline_asm diff --git a/Firmware/CubeIDE/Debug/CMSIS/src/subdir.mk b/Firmware/CubeIDE/Debug/CMSIS/src/subdir.mk new file mode 100644 index 0000000..b789a2b --- /dev/null +++ b/Firmware/CubeIDE/Debug/CMSIS/src/subdir.mk @@ -0,0 +1,24 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../CMSIS/src/core_cm3.c \ +../CMSIS/src/system_stm32f10x.c + +OBJS += \ +./CMSIS/src/core_cm3.o \ +./CMSIS/src/system_stm32f10x.o + +C_DEPS += \ +./CMSIS/src/core_cm3.d \ +./CMSIS/src/system_stm32f10x.d + + +# Each subdirectory must supply rules for building sources it contributes +CMSIS/src/core_cm3.o: ../CMSIS/src/core_cm3.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"CMSIS/src/core_cm3.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +CMSIS/src/system_stm32f10x.o: ../CMSIS/src/system_stm32f10x.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"CMSIS/src/system_stm32f10x.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Firmware/CubeIDE/Debug/CMSIS/src/system_stm32f10x.d b/Firmware/CubeIDE/Debug/CMSIS/src/system_stm32f10x.d new file mode 100644 index 0000000..cf8778a --- /dev/null +++ b/Firmware/CubeIDE/Debug/CMSIS/src/system_stm32f10x.d @@ -0,0 +1,10 @@ +CMSIS/src/system_stm32f10x.o: ../CMSIS/src/system_stm32f10x.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: diff --git a/Firmware/CubeIDE/Debug/CMSIS/src/system_stm32f10x.o b/Firmware/CubeIDE/Debug/CMSIS/src/system_stm32f10x.o new file mode 100644 index 0000000..f733b30 Binary files /dev/null and b/Firmware/CubeIDE/Debug/CMSIS/src/system_stm32f10x.o differ diff --git a/Firmware/CubeIDE/Debug/CMSIS/src/system_stm32f10x.su b/Firmware/CubeIDE/Debug/CMSIS/src/system_stm32f10x.su new file mode 100644 index 0000000..530fcf2 --- /dev/null +++ b/Firmware/CubeIDE/Debug/CMSIS/src/system_stm32f10x.su @@ -0,0 +1,4 @@ +system_stm32f10x.c:212:6:SystemInit 8 static +system_stm32f10x.c:306:6:SystemCoreClockUpdate 24 static +system_stm32f10x.c:419:13:SetSysClock 8 static +system_stm32f10x.c:987:13:SetSysClockTo72 16 static diff --git a/Firmware/CubeIDE/Debug/Code/src/adc.d b/Firmware/CubeIDE/Debug/Code/src/adc.d new file mode 100644 index 0000000..4146eed --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/adc.d @@ -0,0 +1,28 @@ +Code/src/adc.o: ../Code/src/adc.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/adc.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/adc.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/adc.o b/Firmware/CubeIDE/Debug/Code/src/adc.o new file mode 100644 index 0000000..601fc3b Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/adc.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/adc.su b/Firmware/CubeIDE/Debug/Code/src/adc.su new file mode 100644 index 0000000..574ea65 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/adc.su @@ -0,0 +1,3 @@ +adc.c:37:6:adc_init 8 static +adc.c:72:9:adc_get_bat_voltage 8 static +adc.c:123:7:get_bat_voltage 4 static diff --git a/Firmware/CubeIDE/Debug/Code/src/buttons.d b/Firmware/CubeIDE/Debug/Code/src/buttons.d new file mode 100644 index 0000000..0d236ff --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/buttons.d @@ -0,0 +1,13 @@ +Code/src/buttons.o: ../Code/src/buttons.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/buttons.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/buttons.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/buttons.o b/Firmware/CubeIDE/Debug/Code/src/buttons.o new file mode 100644 index 0000000..3d8741e Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/buttons.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/buttons.su b/Firmware/CubeIDE/Debug/Code/src/buttons.su new file mode 100644 index 0000000..9f3bbd1 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/buttons.su @@ -0,0 +1 @@ +buttons.c:79:9:scan_buttons 16 static diff --git a/Firmware/CubeIDE/Debug/Code/src/gpio.d b/Firmware/CubeIDE/Debug/Code/src/gpio.d new file mode 100644 index 0000000..111f830 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/gpio.d @@ -0,0 +1,13 @@ +Code/src/gpio.o: ../Code/src/gpio.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/gpio.o b/Firmware/CubeIDE/Debug/Code/src/gpio.o new file mode 100644 index 0000000..dbdb106 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/gpio.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/gpio.su b/Firmware/CubeIDE/Debug/Code/src/gpio.su new file mode 100644 index 0000000..330e841 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/gpio.su @@ -0,0 +1,21 @@ +core_cm3.h:1502:22:NVIC_EnableIRQ 16 static +gpio.c:16:6:gpio_init 8 static +gpio.c:170:6:ext_int_init 8 static +gpio.c:192:6:led_red_on 4 static +gpio.c:200:6:led_red_off 4 static +gpio.c:208:6:led_green_on 4 static +gpio.c:216:6:led_green_off 4 static +gpio.c:224:6:led_board_on 4 static +gpio.c:232:6:led_board_off 4 static +gpio.c:240:6:sdn_si4463_active 4 static +gpio.c:248:6:sdn_si4463_inactive 4 static +gpio.c:256:6:cs_si4463_active 4 static +gpio.c:264:6:cs_si4463_inactive 4 static +gpio.c:272:6:res_ssd1306_active 4 static +gpio.c:280:6:res_ssd1306_inactive 4 static +gpio.c:288:6:ssd1306_data_mode 4 static +gpio.c:296:6:ssd1306_command_mode 4 static +gpio.c:304:6:cs_ssd1306_active 4 static +gpio.c:312:6:cs_ssd1306_inactive 4 static +gpio.c:320:6:bat_mon_on 4 static +gpio.c:328:6:bat_mon_off 4 static diff --git a/Firmware/CubeIDE/Debug/Code/src/gps.d b/Firmware/CubeIDE/Debug/Code/src/gps.d new file mode 100644 index 0000000..b730579 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/gps.d @@ -0,0 +1,31 @@ +Code/src/gps.o: ../Code/src/gps.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/uart.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/uart.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/gps.o b/Firmware/CubeIDE/Debug/Code/src/gps.o new file mode 100644 index 0000000..7c72b42 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/gps.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/gps.su b/Firmware/CubeIDE/Debug/Code/src/gps.su new file mode 100644 index 0000000..4543d0c --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/gps.su @@ -0,0 +1,11 @@ +gps.c:50:9:parse_gps 8 static +gps.c:68:6:gps_raw_convert_to_numerical 16 static +gps.c:181:9:parse_RMC 16 static +gps.c:251:9:parse_GGA 16 static +gps.c:300:9:parse_GSA 16 static +gps.c:349:9:parse_GSV 16 static +gps.c:395:9:nmea_checksum 24 static +gps.c:437:9:get_gps_status 4 static +gps.c:444:7:get_nmea_buf 4 static +gps.c:451:24:get_gps_raw 4 static +gps.c:458:24:get_gps_num 4 static diff --git a/Firmware/CubeIDE/Debug/Code/src/i2c.d b/Firmware/CubeIDE/Debug/Code/src/i2c.d new file mode 100644 index 0000000..fe1a302 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/i2c.d @@ -0,0 +1,16 @@ +Code/src/i2c.o: ../Code/src/i2c.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/i2c.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/i2c.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/i2c.o b/Firmware/CubeIDE/Debug/Code/src/i2c.o new file mode 100644 index 0000000..a5b78b9 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/i2c.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/i2c.su b/Firmware/CubeIDE/Debug/Code/src/i2c.su new file mode 100644 index 0000000..46568f2 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/i2c.su @@ -0,0 +1 @@ +i2c.c:20:6:i2c_init 4 static diff --git a/Firmware/CubeIDE/Debug/Code/src/lrns.d b/Firmware/CubeIDE/Debug/Code/src/lrns.d new file mode 100644 index 0000000..37d5d39 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/lrns.d @@ -0,0 +1,34 @@ +Code/src/lrns.o: ../Code/src/lrns.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/lrns.o b/Firmware/CubeIDE/Debug/Code/src/lrns.o new file mode 100644 index 0000000..014ac05 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/lrns.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/lrns.su b/Firmware/CubeIDE/Debug/Code/src/lrns.su new file mode 100644 index 0000000..151acd5 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/lrns.su @@ -0,0 +1,15 @@ +lrns.c:80:6:init_lrns 16 static +lrns.c:109:6:set_device_flags 24 static +lrns.c:145:9:get_device_flags 24 static +lrns.c:179:9:check_alarms 16 static +lrns.c:205:6:calc_timeout 24 static +lrns.c:219:9:check_timeout 16 static +lrns.c:254:9:check_fence 16 static +lrns.c:286:6:process_all_devices 16 static +lrns.c:300:6:gps_air_update_my_data 24 static +lrns.c:343:6:fill_air_packet_with_struct_data 4 static +lrns.c:367:9:fill_struct_with_air_packet_data 24 static +lrns.c:399:6:calc_relative_position 88 static +lrns.c:459:25:get_gps_air 16 static +lrns.c:471:25:get_gps_rel 16 static +lrns.c:483:25:get_dev_aux 16 static diff --git a/Firmware/CubeIDE/Debug/Code/src/m24c64.d b/Firmware/CubeIDE/Debug/Code/src/m24c64.d new file mode 100644 index 0000000..871755b --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/m24c64.d @@ -0,0 +1,16 @@ +Code/src/m24c64.o: ../Code/src/m24c64.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/i2c.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/i2c.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/m24c64.o b/Firmware/CubeIDE/Debug/Code/src/m24c64.o new file mode 100644 index 0000000..f564523 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/m24c64.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/m24c64.su b/Firmware/CubeIDE/Debug/Code/src/m24c64.su new file mode 100644 index 0000000..974c064 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/m24c64.su @@ -0,0 +1,7 @@ +m24c64.c:26:9:m24c64_poll 16 static +m24c64.c:86:9:m24c64_read_byte 24 static +m24c64.c:171:6:m24c64_write_byte 24 static +m24c64.c:226:6:m24c64_read_page 24 static +m24c64.c:317:6:m24c64_write_page 24 static +m24c64.c:376:6:m24c64_erase_page 56 static +m24c64.c:390:6:m24c64_erase_all 16 static diff --git a/Firmware/CubeIDE/Debug/Code/src/main.d b/Firmware/CubeIDE/Debug/Code/src/main.d new file mode 100644 index 0000000..48df56a --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/main.d @@ -0,0 +1,64 @@ +Code/src/main.o: ../Code/src/main.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/spi.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/uart.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/timer.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/i2c.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/buttons.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/menu.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/adc.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306_bitmaps.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/spi.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/uart.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/timer.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/i2c.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/buttons.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/menu.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/adc.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306_bitmaps.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/main.o b/Firmware/CubeIDE/Debug/Code/src/main.o new file mode 100644 index 0000000..368d72e Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/main.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/main.su b/Firmware/CubeIDE/Debug/Code/src/main.su new file mode 100644 index 0000000..81228ee --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/main.su @@ -0,0 +1,10 @@ +core_cm3.h:1204:22:__enable_irq 4 static,ignoring_inline_asm +main.c:50:5:main 16 static +main.c:160:6:DMA1_Channel5_IRQHandler 8 static +main.c:177:6:EXTI15_10_IRQHandler 8 static +main.c:221:6:EXTI9_5_IRQHandler 4 static +main.c:265:6:TIM1_UP_IRQHandler 8 static +main.c:302:6:SysTick_Handler 8 static +main.c:315:6:TIM2_IRQHandler 8 static +main.c:326:10:get_uptime 4 static +main.c:333:27:get_main_flags 4 static diff --git a/Firmware/CubeIDE/Debug/Code/src/menu.d b/Firmware/CubeIDE/Debug/Code/src/menu.d new file mode 100644 index 0000000..6e780db --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/menu.d @@ -0,0 +1,55 @@ +Code/src/menu.o: ../Code/src/menu.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/menu.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/buttons.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306_bitmaps.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/adc.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/timer.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/menu.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/buttons.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306_bitmaps.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/adc.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/timer.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/menu.o b/Firmware/CubeIDE/Debug/Code/src/menu.o new file mode 100644 index 0000000..96830df Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/menu.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/menu.su b/Firmware/CubeIDE/Debug/Code/src/menu.su new file mode 100644 index 0000000..6b30c39 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/menu.su @@ -0,0 +1,100 @@ +core_cm3.h:1215:22:__DSB 4 static,ignoring_inline_asm +core_cm3.h:1719:22:NVIC_SystemReset 8 static +menu.c:503:6:init_menu 8 static +menu.c:530:6:change_menu 24 static +menu.c:581:6:toggle_alarm 8 static +menu.c:599:6:scroll_up 16 static +menu.c:619:6:scroll_down 16 static +menu.c:639:6:switch_forward 16 static +menu.c:656:6:switch_backward 16 static +menu.c:673:9:get_current_item 16 static +menu.c:688:9:get_last_item 16 static +menu.c:703:6:set_current_item 24 static +menu.c:718:6:reset_current_item_in_menu 24 static +menu.c:733:6:draw_current_menu 16 static +menu.c:748:6:draw_main 8 static +menu.c:774:6:draw_devices 24 static +menu.c:1027:6:draw_each_device 24 static +menu.c:1455:6:draw_each_device_submenu 8 static +menu.c:1480:6:draw_delete_device 8 static +menu.c:1511:6:delete_device_ok 8 static +menu.c:1528:6:draw_save_device 16 static +menu.c:1586:6:draw_save_device_as 8 static +menu.c:1604:6:draw_saved_popup 8 static +menu.c:1614:6:draw_radar 80 static +menu.c:1944:6:draw_points 16 static +menu.c:1996:6:draw_each_point 8 static +menu.c:2015:6:draw_load_point 16 static +menu.c:2066:6:draw_delete_point 8 static +menu.c:2080:6:draw_settings 8 static +menu.c:2097:6:draw_info 8 static +menu.c:2121:6:draw_edit_settings 8 static +menu.c:2171:6:draw_set_dev_num 8 static +menu.c:2190:6:draw_set_dev_id 8 static +menu.c:2212:6:draw_set_freq_ch 8 static +menu.c:2231:6:draw_set_tx_pow 8 static +menu.c:2251:6:draw_set_send_intvl 8 static +menu.c:2271:6:draw_set_to_thr 8 static +menu.c:2291:6:draw_set_fnc_thr 8 static +menu.c:2311:6:draw_confirm_settings_save 8 static +menu.c:2331:6:draw_restore_defaults 8 static +menu.c:2343:6:draw_erase_all 8 static +menu.c:2354:6:devices_ok 8 static +menu.c:2367:6:each_device_up 8 static +menu.c:2387:6:each_device_down 8 static +menu.c:2407:6:each_device_ok 8 static +menu.c:2415:6:save_device_up 8 static +menu.c:2438:6:save_device_down 8 static +menu.c:2461:6:save_device_ok 8 static +menu.c:2472:6:save_device_esc 8 static +menu.c:2481:6:save_device_as_up 8 static +menu.c:2497:6:save_device_as_down 8 static +menu.c:2513:6:save_device_as_ok 8 static +menu.c:2525:6:save_device_as_ok_long 8 static +menu.c:2539:6:save_device_as_esc 8 static +menu.c:2548:6:saved_popup_esc 8 static +menu.c:2560:6:radar_up 8 static +menu.c:2587:6:radar_down 8 static +menu.c:2614:6:radar_ok 8 static +menu.c:2626:6:points_up 8 static +menu.c:2642:6:points_down 8 static +menu.c:2658:6:points_ok 8 static +menu.c:2669:6:points_esc 8 static +menu.c:2678:6:load_point_up 8 static +menu.c:2705:6:load_point_down 8 static +menu.c:2732:6:load_point_ok 8 static +menu.c:2747:6:load_point_esc 8 static +menu.c:2756:6:delete_point_ok 8 static +menu.c:2768:6:set_dev_num_up 8 static +menu.c:2784:6:set_dev_num_down 8 static +menu.c:2800:6:set_dev_num_ok 8 static +menu.c:2813:6:set_dev_num_esc 8 static +menu.c:2822:6:confirm_settings_save_ok 8 static +menu.c:2830:6:set_dev_id_up 8 static +menu.c:2846:6:set_dev_id_down 8 static +menu.c:2862:6:set_dev_id_ok 8 static +menu.c:2874:6:set_dev_id_ok_long 16 static +menu.c:2891:6:set_dev_id_esc 16 static +menu.c:2905:6:set_freq_ch_up 8 static +menu.c:2921:6:set_freq_ch_down 8 static +menu.c:2937:6:set_freq_ch_ok 8 static +menu.c:2950:6:set_freq_ch_esc 8 static +menu.c:2959:6:set_tx_pow_up 8 static +menu.c:2975:6:set_tx_pow_down 8 static +menu.c:2991:6:set_tx_pow_ok 8 static +menu.c:3004:6:set_tx_pow_esc 8 static +menu.c:3013:6:set_send_intvl_up 8 static +menu.c:3029:6:set_send_intvl_down 8 static +menu.c:3045:6:set_send_intvl_ok 8 static +menu.c:3058:6:set_send_intvl_esc 8 static +menu.c:3067:6:set_to_thr_up 8 static +menu.c:3082:6:set_to_thr_down 8 static +menu.c:3096:6:set_to_thr_ok 8 static +menu.c:3109:6:set_to_thr_esc 8 static +menu.c:3118:6:set_fnc_thr_up 8 static +menu.c:3133:6:set_fnc_thr_down 8 static +menu.c:3147:6:set_fnc_thr_ok 8 static +menu.c:3160:6:set_fnc_thr_esc 8 static +menu.c:3169:6:confirm_settings_save_esc 8 static +menu.c:3179:6:restore_defaults_ok 8 static +menu.c:3187:6:erase_all_ok 8 static diff --git a/Firmware/CubeIDE/Debug/Code/src/points.d b/Firmware/CubeIDE/Debug/Code/src/points.d new file mode 100644 index 0000000..f816e0a --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/points.d @@ -0,0 +1,31 @@ +Code/src/points.o: ../Code/src/points.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/points.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/lrns.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/points.o b/Firmware/CubeIDE/Debug/Code/src/points.o new file mode 100644 index 0000000..4baa080 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/points.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/points.su b/Firmware/CubeIDE/Debug/Code/src/points.su new file mode 100644 index 0000000..27a662d --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/points.su @@ -0,0 +1,7 @@ +points.c:73:29:get_memory_slot 16 static +points.c:85:6:init_points 16 static +points.c:101:6:read_memory_slots 16 static +points.c:137:6:save_memory_point 16 static +points.c:176:6:load_memory_point 32 static +points.c:213:6:delete_memory_point 16 static +points.c:221:6:clear_point_buffer 16 static diff --git a/Firmware/CubeIDE/Debug/Code/src/service.d b/Firmware/CubeIDE/Debug/Code/src/service.d new file mode 100644 index 0000000..b2fb4ad --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/service.d @@ -0,0 +1,13 @@ +Code/src/service.o: ../Code/src/service.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/service.o b/Firmware/CubeIDE/Debug/Code/src/service.o new file mode 100644 index 0000000..66a4558 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/service.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/service.su b/Firmware/CubeIDE/Debug/Code/src/service.su new file mode 100644 index 0000000..e9ddaee --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/service.su @@ -0,0 +1,7 @@ +service.c:17:6:convert_timeout 40 static +service.c:148:6:delay_cyc 16 static +service.c:159:6:copy_string 16 static +service.c:171:7:atof32 40 static +service.c:210:6:ftoa32 64 static +service.c:288:9:atoi32 32 static +service.c:322:6:itoa32 24 static diff --git a/Firmware/CubeIDE/Debug/Code/src/settings.d b/Firmware/CubeIDE/Debug/Code/src/settings.d new file mode 100644 index 0000000..3d63cff --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/settings.d @@ -0,0 +1,22 @@ +Code/src/settings.o: ../Code/src/settings.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/m24c64.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/settings.o b/Firmware/CubeIDE/Debug/Code/src/settings.o new file mode 100644 index 0000000..11167e9 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/settings.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/settings.su b/Firmware/CubeIDE/Debug/Code/src/settings.su new file mode 100644 index 0000000..1be685c --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/settings.su @@ -0,0 +1,6 @@ +settings.c:78:10:get_send_interval_values 4 static +settings.c:85:10:get_tx_power_values 4 static +settings.c:92:25:get_settings 4 static +settings.c:99:6:settings_load 16 static +settings.c:126:6:settings_save_default 16 static +settings.c:152:6:settings_save 24 static diff --git a/Firmware/CubeIDE/Debug/Code/src/si4463.d b/Firmware/CubeIDE/Debug/Code/src/si4463.d new file mode 100644 index 0000000..662eb30 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/si4463.d @@ -0,0 +1,31 @@ +Code/src/si4463.o: ../Code/src/si4463.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/radio_config_Si4463.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/spi.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/si4463.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/radio_config_Si4463.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/spi.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/settings.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/si4463.o b/Firmware/CubeIDE/Debug/Code/src/si4463.o new file mode 100644 index 0000000..1e677ec Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/si4463.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/si4463.su b/Firmware/CubeIDE/Debug/Code/src/si4463.su new file mode 100644 index 0000000..174c3eb --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/si4463.su @@ -0,0 +1,9 @@ +si4463.c:77:6:si4463_init 384 static +si4463.c:119:6:si4463_wait_cts 4 static +si4463.c:127:6:si4463_set_packet_len 16 static +si4463.c:142:6:si4463_set_tx_power 16 static +si4463.c:157:6:si4463_tx_packet 16 static +si4463.c:190:6:si4463_start_rx 8 static +si4463.c:208:9:si4463_get_rx_packet 24 static +si4463.c:265:10:get_air_packet_tx 4 static +si4463.c:272:10:get_air_packet_rx 4 static diff --git a/Firmware/CubeIDE/Debug/Code/src/spi.d b/Firmware/CubeIDE/Debug/Code/src/spi.d new file mode 100644 index 0000000..053ba59 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/spi.d @@ -0,0 +1,13 @@ +Code/src/spi.o: ../Code/src/spi.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/spi.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/spi.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/spi.o b/Firmware/CubeIDE/Debug/Code/src/spi.o new file mode 100644 index 0000000..d60ae34 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/spi.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/spi.su b/Firmware/CubeIDE/Debug/Code/src/spi.su new file mode 100644 index 0000000..42ce144 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/spi.su @@ -0,0 +1,4 @@ +spi.c:16:6:spi1_init 4 static +spi.c:34:6:spi2_init 4 static +spi.c:49:9:spi1_trx 16 static +spi.c:61:9:spi2_trx 16 static diff --git a/Firmware/CubeIDE/Debug/Code/src/ssd1306.d b/Firmware/CubeIDE/Debug/Code/src/ssd1306.d new file mode 100644 index 0000000..782baf7 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/ssd1306.d @@ -0,0 +1,25 @@ +Code/src/ssd1306.o: ../Code/src/ssd1306.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306_font6x8.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/spi.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/ssd1306_font6x8.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/spi.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/service.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/ssd1306.o b/Firmware/CubeIDE/Debug/Code/src/ssd1306.o new file mode 100644 index 0000000..6d3aeae Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/ssd1306.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/ssd1306.su b/Firmware/CubeIDE/Debug/Code/src/ssd1306.su new file mode 100644 index 0000000..ab5ffea --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/ssd1306.su @@ -0,0 +1,13 @@ +ssd1306.c:44:6:ssd1306_init 16 static +ssd1306.c:77:6:ssd1306_update 16 static +ssd1306.c:91:6:ssd1306_fill 16 static +ssd1306.c:102:6:ssd1306_clear 16 static +ssd1306.c:113:6:ssd1306_pixel 16 static +ssd1306.c:132:6:ssd1306_pos 16 static +ssd1306.c:140:6:ssd1306_char 24 static +ssd1306.c:161:6:ssd1306_char_pos 24 static +ssd1306.c:170:6:ssd1306_print 16 static +ssd1306.c:183:6:ssd1306_print_viceversa 24 static +ssd1306.c:206:6:ssd1306_print_next 16 static +ssd1306.c:217:6:ssd1306_bitmap 24 static +ssd1306.c:228:6:ssd1306_print_byte 16 static diff --git a/Firmware/CubeIDE/Debug/Code/src/ssd1306_bitmaps.d b/Firmware/CubeIDE/Debug/Code/src/ssd1306_bitmaps.d new file mode 100644 index 0000000..88fd744 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/ssd1306_bitmaps.d @@ -0,0 +1,10 @@ +Code/src/ssd1306_bitmaps.o: ../Code/src/ssd1306_bitmaps.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/ssd1306_bitmaps.o b/Firmware/CubeIDE/Debug/Code/src/ssd1306_bitmaps.o new file mode 100644 index 0000000..52925e4 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/ssd1306_bitmaps.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/ssd1306_bitmaps.su b/Firmware/CubeIDE/Debug/Code/src/ssd1306_bitmaps.su new file mode 100644 index 0000000..e69de29 diff --git a/Firmware/CubeIDE/Debug/Code/src/subdir.mk b/Firmware/CubeIDE/Debug/Code/src/subdir.mk new file mode 100644 index 0000000..5b3e081 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/subdir.mk @@ -0,0 +1,104 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Code/src/adc.c \ +../Code/src/buttons.c \ +../Code/src/gpio.c \ +../Code/src/gps.c \ +../Code/src/i2c.c \ +../Code/src/lrns.c \ +../Code/src/m24c64.c \ +../Code/src/main.c \ +../Code/src/menu.c \ +../Code/src/points.c \ +../Code/src/service.c \ +../Code/src/settings.c \ +../Code/src/si4463.c \ +../Code/src/spi.c \ +../Code/src/ssd1306.c \ +../Code/src/ssd1306_bitmaps.c \ +../Code/src/timer.c \ +../Code/src/uart.c + +OBJS += \ +./Code/src/adc.o \ +./Code/src/buttons.o \ +./Code/src/gpio.o \ +./Code/src/gps.o \ +./Code/src/i2c.o \ +./Code/src/lrns.o \ +./Code/src/m24c64.o \ +./Code/src/main.o \ +./Code/src/menu.o \ +./Code/src/points.o \ +./Code/src/service.o \ +./Code/src/settings.o \ +./Code/src/si4463.o \ +./Code/src/spi.o \ +./Code/src/ssd1306.o \ +./Code/src/ssd1306_bitmaps.o \ +./Code/src/timer.o \ +./Code/src/uart.o + +C_DEPS += \ +./Code/src/adc.d \ +./Code/src/buttons.d \ +./Code/src/gpio.d \ +./Code/src/gps.d \ +./Code/src/i2c.d \ +./Code/src/lrns.d \ +./Code/src/m24c64.d \ +./Code/src/main.d \ +./Code/src/menu.d \ +./Code/src/points.d \ +./Code/src/service.d \ +./Code/src/settings.d \ +./Code/src/si4463.d \ +./Code/src/spi.d \ +./Code/src/ssd1306.d \ +./Code/src/ssd1306_bitmaps.d \ +./Code/src/timer.d \ +./Code/src/uart.d + + +# Each subdirectory must supply rules for building sources it contributes +Code/src/adc.o: ../Code/src/adc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/adc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/buttons.o: ../Code/src/buttons.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/buttons.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/gpio.o: ../Code/src/gpio.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/gpio.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/gps.o: ../Code/src/gps.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/gps.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/i2c.o: ../Code/src/i2c.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/i2c.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/lrns.o: ../Code/src/lrns.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/lrns.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/m24c64.o: ../Code/src/m24c64.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/m24c64.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/main.o: ../Code/src/main.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/main.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/menu.o: ../Code/src/menu.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/menu.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/points.o: ../Code/src/points.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/points.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/service.o: ../Code/src/service.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/service.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/settings.o: ../Code/src/settings.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/settings.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/si4463.o: ../Code/src/si4463.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/si4463.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/spi.o: ../Code/src/spi.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/spi.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/ssd1306.o: ../Code/src/ssd1306.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/ssd1306.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/ssd1306_bitmaps.o: ../Code/src/ssd1306_bitmaps.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/ssd1306_bitmaps.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/timer.o: ../Code/src/timer.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/timer.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Code/src/uart.o: ../Code/src/uart.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DSTM32 -DSTM32F1 -DSTM32F103C8Tx -DDEBUG -c -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc" -I"D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Code/src/uart.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Firmware/CubeIDE/Debug/Code/src/timer.d b/Firmware/CubeIDE/Debug/Code/src/timer.d new file mode 100644 index 0000000..41206f2 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/timer.d @@ -0,0 +1,16 @@ +Code/src/timer.o: ../Code/src/timer.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/timer.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/timer.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gpio.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/timer.o b/Firmware/CubeIDE/Debug/Code/src/timer.o new file mode 100644 index 0000000..93d1e7e Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/timer.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/timer.su b/Firmware/CubeIDE/Debug/Code/src/timer.su new file mode 100644 index 0000000..478acdc --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/timer.su @@ -0,0 +1,15 @@ +core_cm3.h:1502:22:NVIC_EnableIRQ 16 static +timer.c:30:6:timers_init 8 static +timer.c:40:6:make_a_beep 8 static +timer.c:53:6:toggle_mute 4 static +timer.c:60:9:get_mute_flag 4 static +timer.c:68:6:systick_init 4 static +timer.c:80:6:timer1_init 8 static +timer.c:96:6:timer1_start 4 static +timer.c:104:6:timer1_stop_reload 4 static +timer.c:113:6:timer2_init 8 static +timer.c:126:6:timer2_stop 4 static +timer.c:133:6:timer2_start 4 static +timer.c:141:6:timer3_init 4 static +timer.c:155:6:timer3_stop 4 static +timer.c:163:6:timer3_start 4 static diff --git a/Firmware/CubeIDE/Debug/Code/src/uart.d b/Firmware/CubeIDE/Debug/Code/src/uart.d new file mode 100644 index 0000000..0fa45d7 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/uart.d @@ -0,0 +1,19 @@ +Code/src/uart.o: ../Code/src/uart.c \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/uart.h \ + D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/core_cm3.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/CMSIS/inc/system_stm32f10x.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/main.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/uart.h: + +D:/Projects/ARM/!ELEPH/eleph/Firmware/CubeIDE/Code/inc/gps.h: diff --git a/Firmware/CubeIDE/Debug/Code/src/uart.o b/Firmware/CubeIDE/Debug/Code/src/uart.o new file mode 100644 index 0000000..90f4e34 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Code/src/uart.o differ diff --git a/Firmware/CubeIDE/Debug/Code/src/uart.su b/Firmware/CubeIDE/Debug/Code/src/uart.su new file mode 100644 index 0000000..d3aff5d --- /dev/null +++ b/Firmware/CubeIDE/Debug/Code/src/uart.su @@ -0,0 +1,6 @@ +core_cm3.h:1502:22:NVIC_EnableIRQ 16 static +uart.c:23:6:uart_dma_init 8 static +uart.c:52:6:uart_dma_stop 4 static +uart.c:60:6:uart_dma_restart 4 static +uart.c:69:6:backup_and_clear_uart_buffer 16 static +uart.c:81:6:uart_tx 16 static diff --git a/Firmware/CubeIDE/Debug/Eleph.bin b/Firmware/CubeIDE/Debug/Eleph.bin new file mode 100644 index 0000000..2cc6d95 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Eleph.bin differ diff --git a/Firmware/CubeIDE/Debug/Eleph.elf b/Firmware/CubeIDE/Debug/Eleph.elf new file mode 100644 index 0000000..3266249 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Eleph.elf differ diff --git a/Firmware/CubeIDE/Debug/Eleph.hex b/Firmware/CubeIDE/Debug/Eleph.hex new file mode 100644 index 0000000..eb81fcb --- /dev/null +++ b/Firmware/CubeIDE/Debug/Eleph.hex @@ -0,0 +1,3726 @@ +:020000040800F2 +:1000000000500020BD9800080D9900080D990008C7 +:100010000D9900080D9900080D99000800000000D6 +:100020000000000000000000000000000D99000822 +:100030000D990008000000000D990008953D00088A +:100040000D9900080D9900080D9900080D990008F8 +:100050000D9900080D9900080D9900080D990008E8 +:100060000D9900080D9900080D9900080D990008D8 +:100070000D9900080D9900080D990008F93B00083A +:100080000D9900080D9900080D9900080D990008B8 +:100090000D9900080D9900080D990008ED3C000825 +:1000A0000D9900080D3D00080D9900080D990008F4 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+:10E7A800000000000000304300000000000030C3FB +:04E7B80055010008FF +:04E7BC00310100081F +:10E7C00010101010100000000101010101000000F4 +:10E7D0000101010101000000D8C90008DCC90008DE +:10E7E0000100040400010B00010E000210000600ED +:10E7F00000000101005F0000BCCD0008C0CD000892 +:10E80000C4CD0008C8CD0008CCCD0008D0CD00088C +:10E8100001050A1E3C0000000A192864141E287F06 +:10E820006400002000000000000000000000000064 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:08E8800000000000010000008F +:04000005080098BD9A +:00000001FF diff --git a/Firmware/CubeIDE/Debug/Eleph.list b/Firmware/CubeIDE/Debug/Eleph.list new file mode 100644 index 0000000..405b6cb --- /dev/null +++ b/Firmware/CubeIDE/Debug/Eleph.list @@ -0,0 +1,27518 @@ + +Eleph.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 00000130 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000c8a4 08000130 08000130 00010130 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00001de0 0800c9d8 0800c9d8 0001c9d8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 0800e7b8 0800e7b8 000200c8 2**0 + CONTENTS + 4 .ARM 00000000 0800e7b8 0800e7b8 000200c8 2**0 + CONTENTS + 5 .preinit_array 00000000 0800e7b8 0800e7b8 000200c8 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800e7b8 0800e7b8 0001e7b8 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 0800e7bc 0800e7bc 0001e7bc 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 000000c8 20000000 0800e7c0 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00001070 200000c8 0800e888 000200c8 2**3 + ALLOC + 10 ._user_heap_stack 00000600 20001138 0800e888 00021138 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 000200c8 2**0 + CONTENTS, READONLY + 12 .debug_info 00009eaf 00000000 00000000 000200f1 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_abbrev 00001ef7 00000000 00000000 00029fa0 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_aranges 00000970 00000000 00000000 0002be98 2**3 + CONTENTS, READONLY, DEBUGGING + 15 .debug_ranges 00000830 00000000 00000000 0002c808 2**3 + CONTENTS, READONLY, DEBUGGING + 16 .debug_macro 0000a8fa 00000000 00000000 0002d038 2**0 + CONTENTS, READONLY, DEBUGGING + 17 .debug_line 00007a9b 00000000 00000000 00037932 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .debug_str 0003a7d5 00000000 00000000 0003f3cd 2**0 + CONTENTS, READONLY, DEBUGGING + 19 .comment 0000007b 00000000 00000000 00079ba2 2**0 + CONTENTS, READONLY + 20 .debug_frame 0000299c 00000000 00000000 00079c20 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +08000130 <__do_global_dtors_aux>: + 8000130: b510 push {r4, lr} + 8000132: 4c05 ldr r4, [pc, #20] ; (8000148 <__do_global_dtors_aux+0x18>) + 8000134: 7823 ldrb r3, [r4, #0] + 8000136: b933 cbnz r3, 8000146 <__do_global_dtors_aux+0x16> + 8000138: 4b04 ldr r3, [pc, #16] ; (800014c <__do_global_dtors_aux+0x1c>) + 800013a: b113 cbz r3, 8000142 <__do_global_dtors_aux+0x12> + 800013c: 4804 ldr r0, [pc, #16] ; (8000150 <__do_global_dtors_aux+0x20>) + 800013e: f3af 8000 nop.w + 8000142: 2301 movs r3, #1 + 8000144: 7023 strb r3, [r4, #0] + 8000146: bd10 pop {r4, pc} + 8000148: 200000c8 .word 0x200000c8 + 800014c: 00000000 .word 0x00000000 + 8000150: 0800c9bc .word 0x0800c9bc + +08000154 : + 8000154: b508 push {r3, lr} + 8000156: 4b03 ldr r3, [pc, #12] ; (8000164 ) + 8000158: b11b cbz r3, 8000162 + 800015a: 4903 ldr r1, [pc, #12] ; (8000168 ) + 800015c: 4803 ldr r0, [pc, #12] ; (800016c ) + 800015e: f3af 8000 nop.w + 8000162: bd08 pop {r3, pc} + 8000164: 00000000 .word 0x00000000 + 8000168: 200000cc .word 0x200000cc + 800016c: 0800c9bc .word 0x0800c9bc + +08000170 <__aeabi_drsub>: + 8000170: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 + 8000174: e002 b.n 800017c <__adddf3> + 8000176: bf00 nop + +08000178 <__aeabi_dsub>: + 8000178: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 + +0800017c <__adddf3>: + 800017c: b530 push {r4, r5, lr} + 800017e: ea4f 0441 mov.w r4, r1, lsl #1 + 8000182: ea4f 0543 mov.w r5, r3, lsl #1 + 8000186: ea94 0f05 teq r4, r5 + 800018a: bf08 it eq + 800018c: ea90 0f02 teqeq r0, r2 + 8000190: bf1f itttt ne + 8000192: ea54 0c00 orrsne.w ip, r4, r0 + 8000196: ea55 0c02 orrsne.w ip, r5, r2 + 800019a: ea7f 5c64 mvnsne.w ip, r4, asr #21 + 800019e: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 80001a2: f000 80e2 beq.w 800036a <__adddf3+0x1ee> + 80001a6: ea4f 5454 mov.w r4, r4, lsr #21 + 80001aa: ebd4 5555 rsbs r5, r4, r5, lsr #21 + 80001ae: bfb8 it lt + 80001b0: 426d neglt r5, r5 + 80001b2: dd0c ble.n 80001ce <__adddf3+0x52> + 80001b4: 442c add r4, r5 + 80001b6: ea80 0202 eor.w r2, r0, r2 + 80001ba: ea81 0303 eor.w r3, r1, r3 + 80001be: ea82 0000 eor.w r0, r2, r0 + 80001c2: ea83 0101 eor.w r1, r3, r1 + 80001c6: ea80 0202 eor.w r2, r0, r2 + 80001ca: ea81 0303 eor.w r3, r1, r3 + 80001ce: 2d36 cmp r5, #54 ; 0x36 + 80001d0: bf88 it hi + 80001d2: bd30 pophi {r4, r5, pc} + 80001d4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 80001d8: ea4f 3101 mov.w r1, r1, lsl #12 + 80001dc: f44f 1c80 mov.w ip, #1048576 ; 0x100000 + 80001e0: ea4c 3111 orr.w r1, ip, r1, lsr #12 + 80001e4: d002 beq.n 80001ec <__adddf3+0x70> + 80001e6: 4240 negs r0, r0 + 80001e8: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 80001ec: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 + 80001f0: ea4f 3303 mov.w r3, r3, lsl #12 + 80001f4: ea4c 3313 orr.w r3, ip, r3, lsr #12 + 80001f8: d002 beq.n 8000200 <__adddf3+0x84> + 80001fa: 4252 negs r2, r2 + 80001fc: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 8000200: ea94 0f05 teq r4, r5 + 8000204: f000 80a7 beq.w 8000356 <__adddf3+0x1da> + 8000208: f1a4 0401 sub.w r4, r4, #1 + 800020c: f1d5 0e20 rsbs lr, r5, #32 + 8000210: db0d blt.n 800022e <__adddf3+0xb2> + 8000212: fa02 fc0e lsl.w ip, r2, lr + 8000216: fa22 f205 lsr.w r2, r2, r5 + 800021a: 1880 adds r0, r0, r2 + 800021c: f141 0100 adc.w r1, r1, #0 + 8000220: fa03 f20e lsl.w r2, r3, lr + 8000224: 1880 adds r0, r0, r2 + 8000226: fa43 f305 asr.w r3, r3, r5 + 800022a: 4159 adcs r1, r3 + 800022c: e00e b.n 800024c <__adddf3+0xd0> + 800022e: f1a5 0520 sub.w r5, r5, #32 + 8000232: f10e 0e20 add.w lr, lr, #32 + 8000236: 2a01 cmp r2, #1 + 8000238: fa03 fc0e lsl.w ip, r3, lr + 800023c: bf28 it cs + 800023e: f04c 0c02 orrcs.w ip, ip, #2 + 8000242: fa43 f305 asr.w r3, r3, r5 + 8000246: 18c0 adds r0, r0, r3 + 8000248: eb51 71e3 adcs.w r1, r1, r3, asr #31 + 800024c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000250: d507 bpl.n 8000262 <__adddf3+0xe6> + 8000252: f04f 0e00 mov.w lr, #0 + 8000256: f1dc 0c00 rsbs ip, ip, #0 + 800025a: eb7e 0000 sbcs.w r0, lr, r0 + 800025e: eb6e 0101 sbc.w r1, lr, r1 + 8000262: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 + 8000266: d31b bcc.n 80002a0 <__adddf3+0x124> + 8000268: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 + 800026c: d30c bcc.n 8000288 <__adddf3+0x10c> + 800026e: 0849 lsrs r1, r1, #1 + 8000270: ea5f 0030 movs.w r0, r0, rrx + 8000274: ea4f 0c3c mov.w ip, ip, rrx + 8000278: f104 0401 add.w r4, r4, #1 + 800027c: ea4f 5244 mov.w r2, r4, lsl #21 + 8000280: f512 0f80 cmn.w r2, #4194304 ; 0x400000 + 8000284: f080 809a bcs.w 80003bc <__adddf3+0x240> + 8000288: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 + 800028c: bf08 it eq + 800028e: ea5f 0c50 movseq.w ip, r0, lsr #1 + 8000292: f150 0000 adcs.w r0, r0, #0 + 8000296: eb41 5104 adc.w r1, r1, r4, lsl #20 + 800029a: ea41 0105 orr.w r1, r1, r5 + 800029e: bd30 pop {r4, r5, pc} + 80002a0: ea5f 0c4c movs.w ip, ip, lsl #1 + 80002a4: 4140 adcs r0, r0 + 80002a6: eb41 0101 adc.w r1, r1, r1 + 80002aa: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 80002ae: f1a4 0401 sub.w r4, r4, #1 + 80002b2: d1e9 bne.n 8000288 <__adddf3+0x10c> + 80002b4: f091 0f00 teq r1, #0 + 80002b8: bf04 itt eq + 80002ba: 4601 moveq r1, r0 + 80002bc: 2000 moveq r0, #0 + 80002be: fab1 f381 clz r3, r1 + 80002c2: bf08 it eq + 80002c4: 3320 addeq r3, #32 + 80002c6: f1a3 030b sub.w r3, r3, #11 + 80002ca: f1b3 0220 subs.w r2, r3, #32 + 80002ce: da0c bge.n 80002ea <__adddf3+0x16e> + 80002d0: 320c adds r2, #12 + 80002d2: dd08 ble.n 80002e6 <__adddf3+0x16a> + 80002d4: f102 0c14 add.w ip, r2, #20 + 80002d8: f1c2 020c rsb r2, r2, #12 + 80002dc: fa01 f00c lsl.w r0, r1, ip + 80002e0: fa21 f102 lsr.w r1, r1, r2 + 80002e4: e00c b.n 8000300 <__adddf3+0x184> + 80002e6: f102 0214 add.w r2, r2, #20 + 80002ea: bfd8 it le + 80002ec: f1c2 0c20 rsble ip, r2, #32 + 80002f0: fa01 f102 lsl.w r1, r1, r2 + 80002f4: fa20 fc0c lsr.w ip, r0, ip + 80002f8: bfdc itt le + 80002fa: ea41 010c orrle.w r1, r1, ip + 80002fe: 4090 lslle r0, r2 + 8000300: 1ae4 subs r4, r4, r3 + 8000302: bfa2 ittt ge + 8000304: eb01 5104 addge.w r1, r1, r4, lsl #20 + 8000308: 4329 orrge r1, r5 + 800030a: bd30 popge {r4, r5, pc} + 800030c: ea6f 0404 mvn.w r4, r4 + 8000310: 3c1f subs r4, #31 + 8000312: da1c bge.n 800034e <__adddf3+0x1d2> + 8000314: 340c adds r4, #12 + 8000316: dc0e bgt.n 8000336 <__adddf3+0x1ba> + 8000318: f104 0414 add.w r4, r4, #20 + 800031c: f1c4 0220 rsb r2, r4, #32 + 8000320: fa20 f004 lsr.w r0, r0, r4 + 8000324: fa01 f302 lsl.w r3, r1, r2 + 8000328: ea40 0003 orr.w r0, r0, r3 + 800032c: fa21 f304 lsr.w r3, r1, r4 + 8000330: ea45 0103 orr.w r1, r5, r3 + 8000334: bd30 pop {r4, r5, pc} + 8000336: f1c4 040c rsb r4, r4, #12 + 800033a: f1c4 0220 rsb r2, r4, #32 + 800033e: fa20 f002 lsr.w r0, r0, r2 + 8000342: fa01 f304 lsl.w r3, r1, r4 + 8000346: ea40 0003 orr.w r0, r0, r3 + 800034a: 4629 mov r1, r5 + 800034c: bd30 pop {r4, r5, pc} + 800034e: fa21 f004 lsr.w r0, r1, r4 + 8000352: 4629 mov r1, r5 + 8000354: bd30 pop {r4, r5, pc} + 8000356: f094 0f00 teq r4, #0 + 800035a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 + 800035e: bf06 itte eq + 8000360: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 + 8000364: 3401 addeq r4, #1 + 8000366: 3d01 subne r5, #1 + 8000368: e74e b.n 8000208 <__adddf3+0x8c> + 800036a: ea7f 5c64 mvns.w ip, r4, asr #21 + 800036e: bf18 it ne + 8000370: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 8000374: d029 beq.n 80003ca <__adddf3+0x24e> + 8000376: ea94 0f05 teq r4, r5 + 800037a: bf08 it eq + 800037c: ea90 0f02 teqeq r0, r2 + 8000380: d005 beq.n 800038e <__adddf3+0x212> + 8000382: ea54 0c00 orrs.w ip, r4, r0 + 8000386: bf04 itt eq + 8000388: 4619 moveq r1, r3 + 800038a: 4610 moveq r0, r2 + 800038c: bd30 pop {r4, r5, pc} + 800038e: ea91 0f03 teq r1, r3 + 8000392: bf1e ittt ne + 8000394: 2100 movne r1, #0 + 8000396: 2000 movne r0, #0 + 8000398: bd30 popne {r4, r5, pc} + 800039a: ea5f 5c54 movs.w ip, r4, lsr #21 + 800039e: d105 bne.n 80003ac <__adddf3+0x230> + 80003a0: 0040 lsls r0, r0, #1 + 80003a2: 4149 adcs r1, r1 + 80003a4: bf28 it cs + 80003a6: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 + 80003aa: bd30 pop {r4, r5, pc} + 80003ac: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 + 80003b0: bf3c itt cc + 80003b2: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 + 80003b6: bd30 popcc {r4, r5, pc} + 80003b8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 80003bc: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 + 80003c0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 80003c4: f04f 0000 mov.w r0, #0 + 80003c8: bd30 pop {r4, r5, pc} + 80003ca: ea7f 5c64 mvns.w ip, r4, asr #21 + 80003ce: bf1a itte ne + 80003d0: 4619 movne r1, r3 + 80003d2: 4610 movne r0, r2 + 80003d4: ea7f 5c65 mvnseq.w ip, r5, asr #21 + 80003d8: bf1c itt ne + 80003da: 460b movne r3, r1 + 80003dc: 4602 movne r2, r0 + 80003de: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 80003e2: bf06 itte eq + 80003e4: ea52 3503 orrseq.w r5, r2, r3, lsl #12 + 80003e8: ea91 0f03 teqeq r1, r3 + 80003ec: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 + 80003f0: bd30 pop {r4, r5, pc} + 80003f2: bf00 nop + +080003f4 <__aeabi_ui2d>: + 80003f4: f090 0f00 teq r0, #0 + 80003f8: bf04 itt eq + 80003fa: 2100 moveq r1, #0 + 80003fc: 4770 bxeq lr + 80003fe: b530 push {r4, r5, lr} + 8000400: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000404: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000408: f04f 0500 mov.w r5, #0 + 800040c: f04f 0100 mov.w r1, #0 + 8000410: e750 b.n 80002b4 <__adddf3+0x138> + 8000412: bf00 nop + +08000414 <__aeabi_i2d>: + 8000414: f090 0f00 teq r0, #0 + 8000418: bf04 itt eq + 800041a: 2100 moveq r1, #0 + 800041c: 4770 bxeq lr + 800041e: b530 push {r4, r5, lr} + 8000420: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000424: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000428: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 + 800042c: bf48 it mi + 800042e: 4240 negmi r0, r0 + 8000430: f04f 0100 mov.w r1, #0 + 8000434: e73e b.n 80002b4 <__adddf3+0x138> + 8000436: bf00 nop + +08000438 <__aeabi_f2d>: + 8000438: 0042 lsls r2, r0, #1 + 800043a: ea4f 01e2 mov.w r1, r2, asr #3 + 800043e: ea4f 0131 mov.w r1, r1, rrx + 8000442: ea4f 7002 mov.w r0, r2, lsl #28 + 8000446: bf1f itttt ne + 8000448: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 + 800044c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 + 8000450: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 + 8000454: 4770 bxne lr + 8000456: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 + 800045a: bf08 it eq + 800045c: 4770 bxeq lr + 800045e: f093 4f7f teq r3, #4278190080 ; 0xff000000 + 8000462: bf04 itt eq + 8000464: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 + 8000468: 4770 bxeq lr + 800046a: b530 push {r4, r5, lr} + 800046c: f44f 7460 mov.w r4, #896 ; 0x380 + 8000470: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000474: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8000478: e71c b.n 80002b4 <__adddf3+0x138> + 800047a: bf00 nop + +0800047c <__aeabi_ul2d>: + 800047c: ea50 0201 orrs.w r2, r0, r1 + 8000480: bf08 it eq + 8000482: 4770 bxeq lr + 8000484: b530 push {r4, r5, lr} + 8000486: f04f 0500 mov.w r5, #0 + 800048a: e00a b.n 80004a2 <__aeabi_l2d+0x16> + +0800048c <__aeabi_l2d>: + 800048c: ea50 0201 orrs.w r2, r0, r1 + 8000490: bf08 it eq + 8000492: 4770 bxeq lr + 8000494: b530 push {r4, r5, lr} + 8000496: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 + 800049a: d502 bpl.n 80004a2 <__aeabi_l2d+0x16> + 800049c: 4240 negs r0, r0 + 800049e: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 80004a2: f44f 6480 mov.w r4, #1024 ; 0x400 + 80004a6: f104 0432 add.w r4, r4, #50 ; 0x32 + 80004aa: ea5f 5c91 movs.w ip, r1, lsr #22 + 80004ae: f43f aed8 beq.w 8000262 <__adddf3+0xe6> + 80004b2: f04f 0203 mov.w r2, #3 + 80004b6: ea5f 0cdc movs.w ip, ip, lsr #3 + 80004ba: bf18 it ne + 80004bc: 3203 addne r2, #3 + 80004be: ea5f 0cdc movs.w ip, ip, lsr #3 + 80004c2: bf18 it ne + 80004c4: 3203 addne r2, #3 + 80004c6: eb02 02dc add.w r2, r2, ip, lsr #3 + 80004ca: f1c2 0320 rsb r3, r2, #32 + 80004ce: fa00 fc03 lsl.w ip, r0, r3 + 80004d2: fa20 f002 lsr.w r0, r0, r2 + 80004d6: fa01 fe03 lsl.w lr, r1, r3 + 80004da: ea40 000e orr.w r0, r0, lr + 80004de: fa21 f102 lsr.w r1, r1, r2 + 80004e2: 4414 add r4, r2 + 80004e4: e6bd b.n 8000262 <__adddf3+0xe6> + 80004e6: bf00 nop + +080004e8 <__aeabi_dmul>: + 80004e8: b570 push {r4, r5, r6, lr} + 80004ea: f04f 0cff mov.w ip, #255 ; 0xff + 80004ee: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 80004f2: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 80004f6: bf1d ittte ne + 80004f8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 80004fc: ea94 0f0c teqne r4, ip + 8000500: ea95 0f0c teqne r5, ip + 8000504: f000 f8de bleq 80006c4 <__aeabi_dmul+0x1dc> + 8000508: 442c add r4, r5 + 800050a: ea81 0603 eor.w r6, r1, r3 + 800050e: ea21 514c bic.w r1, r1, ip, lsl #21 + 8000512: ea23 534c bic.w r3, r3, ip, lsl #21 + 8000516: ea50 3501 orrs.w r5, r0, r1, lsl #12 + 800051a: bf18 it ne + 800051c: ea52 3503 orrsne.w r5, r2, r3, lsl #12 + 8000520: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000524: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8000528: d038 beq.n 800059c <__aeabi_dmul+0xb4> + 800052a: fba0 ce02 umull ip, lr, r0, r2 + 800052e: f04f 0500 mov.w r5, #0 + 8000532: fbe1 e502 umlal lr, r5, r1, r2 + 8000536: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 + 800053a: fbe0 e503 umlal lr, r5, r0, r3 + 800053e: f04f 0600 mov.w r6, #0 + 8000542: fbe1 5603 umlal r5, r6, r1, r3 + 8000546: f09c 0f00 teq ip, #0 + 800054a: bf18 it ne + 800054c: f04e 0e01 orrne.w lr, lr, #1 + 8000550: f1a4 04ff sub.w r4, r4, #255 ; 0xff + 8000554: f5b6 7f00 cmp.w r6, #512 ; 0x200 + 8000558: f564 7440 sbc.w r4, r4, #768 ; 0x300 + 800055c: d204 bcs.n 8000568 <__aeabi_dmul+0x80> + 800055e: ea5f 0e4e movs.w lr, lr, lsl #1 + 8000562: 416d adcs r5, r5 + 8000564: eb46 0606 adc.w r6, r6, r6 + 8000568: ea42 21c6 orr.w r1, r2, r6, lsl #11 + 800056c: ea41 5155 orr.w r1, r1, r5, lsr #21 + 8000570: ea4f 20c5 mov.w r0, r5, lsl #11 + 8000574: ea40 505e orr.w r0, r0, lr, lsr #21 + 8000578: ea4f 2ece mov.w lr, lr, lsl #11 + 800057c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 8000580: bf88 it hi + 8000582: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 8000586: d81e bhi.n 80005c6 <__aeabi_dmul+0xde> + 8000588: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 + 800058c: bf08 it eq + 800058e: ea5f 0e50 movseq.w lr, r0, lsr #1 + 8000592: f150 0000 adcs.w r0, r0, #0 + 8000596: eb41 5104 adc.w r1, r1, r4, lsl #20 + 800059a: bd70 pop {r4, r5, r6, pc} + 800059c: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 + 80005a0: ea46 0101 orr.w r1, r6, r1 + 80005a4: ea40 0002 orr.w r0, r0, r2 + 80005a8: ea81 0103 eor.w r1, r1, r3 + 80005ac: ebb4 045c subs.w r4, r4, ip, lsr #1 + 80005b0: bfc2 ittt gt + 80005b2: ebd4 050c rsbsgt r5, r4, ip + 80005b6: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 80005ba: bd70 popgt {r4, r5, r6, pc} + 80005bc: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 80005c0: f04f 0e00 mov.w lr, #0 + 80005c4: 3c01 subs r4, #1 + 80005c6: f300 80ab bgt.w 8000720 <__aeabi_dmul+0x238> + 80005ca: f114 0f36 cmn.w r4, #54 ; 0x36 + 80005ce: bfde ittt le + 80005d0: 2000 movle r0, #0 + 80005d2: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 + 80005d6: bd70 pople {r4, r5, r6, pc} + 80005d8: f1c4 0400 rsb r4, r4, #0 + 80005dc: 3c20 subs r4, #32 + 80005de: da35 bge.n 800064c <__aeabi_dmul+0x164> + 80005e0: 340c adds r4, #12 + 80005e2: dc1b bgt.n 800061c <__aeabi_dmul+0x134> + 80005e4: f104 0414 add.w r4, r4, #20 + 80005e8: f1c4 0520 rsb r5, r4, #32 + 80005ec: fa00 f305 lsl.w r3, r0, r5 + 80005f0: fa20 f004 lsr.w r0, r0, r4 + 80005f4: fa01 f205 lsl.w r2, r1, r5 + 80005f8: ea40 0002 orr.w r0, r0, r2 + 80005fc: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 + 8000600: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8000604: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 8000608: fa21 f604 lsr.w r6, r1, r4 + 800060c: eb42 0106 adc.w r1, r2, r6 + 8000610: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000614: bf08 it eq + 8000616: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800061a: bd70 pop {r4, r5, r6, pc} + 800061c: f1c4 040c rsb r4, r4, #12 + 8000620: f1c4 0520 rsb r5, r4, #32 + 8000624: fa00 f304 lsl.w r3, r0, r4 + 8000628: fa20 f005 lsr.w r0, r0, r5 + 800062c: fa01 f204 lsl.w r2, r1, r4 + 8000630: ea40 0002 orr.w r0, r0, r2 + 8000634: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000638: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 800063c: f141 0100 adc.w r1, r1, #0 + 8000640: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000644: bf08 it eq + 8000646: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800064a: bd70 pop {r4, r5, r6, pc} + 800064c: f1c4 0520 rsb r5, r4, #32 + 8000650: fa00 f205 lsl.w r2, r0, r5 + 8000654: ea4e 0e02 orr.w lr, lr, r2 + 8000658: fa20 f304 lsr.w r3, r0, r4 + 800065c: fa01 f205 lsl.w r2, r1, r5 + 8000660: ea43 0302 orr.w r3, r3, r2 + 8000664: fa21 f004 lsr.w r0, r1, r4 + 8000668: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 800066c: fa21 f204 lsr.w r2, r1, r4 + 8000670: ea20 0002 bic.w r0, r0, r2 + 8000674: eb00 70d3 add.w r0, r0, r3, lsr #31 + 8000678: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 800067c: bf08 it eq + 800067e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 8000682: bd70 pop {r4, r5, r6, pc} + 8000684: f094 0f00 teq r4, #0 + 8000688: d10f bne.n 80006aa <__aeabi_dmul+0x1c2> + 800068a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 + 800068e: 0040 lsls r0, r0, #1 + 8000690: eb41 0101 adc.w r1, r1, r1 + 8000694: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000698: bf08 it eq + 800069a: 3c01 subeq r4, #1 + 800069c: d0f7 beq.n 800068e <__aeabi_dmul+0x1a6> + 800069e: ea41 0106 orr.w r1, r1, r6 + 80006a2: f095 0f00 teq r5, #0 + 80006a6: bf18 it ne + 80006a8: 4770 bxne lr + 80006aa: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 + 80006ae: 0052 lsls r2, r2, #1 + 80006b0: eb43 0303 adc.w r3, r3, r3 + 80006b4: f413 1f80 tst.w r3, #1048576 ; 0x100000 + 80006b8: bf08 it eq + 80006ba: 3d01 subeq r5, #1 + 80006bc: d0f7 beq.n 80006ae <__aeabi_dmul+0x1c6> + 80006be: ea43 0306 orr.w r3, r3, r6 + 80006c2: 4770 bx lr + 80006c4: ea94 0f0c teq r4, ip + 80006c8: ea0c 5513 and.w r5, ip, r3, lsr #20 + 80006cc: bf18 it ne + 80006ce: ea95 0f0c teqne r5, ip + 80006d2: d00c beq.n 80006ee <__aeabi_dmul+0x206> + 80006d4: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80006d8: bf18 it ne + 80006da: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80006de: d1d1 bne.n 8000684 <__aeabi_dmul+0x19c> + 80006e0: ea81 0103 eor.w r1, r1, r3 + 80006e4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 80006e8: f04f 0000 mov.w r0, #0 + 80006ec: bd70 pop {r4, r5, r6, pc} + 80006ee: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80006f2: bf06 itte eq + 80006f4: 4610 moveq r0, r2 + 80006f6: 4619 moveq r1, r3 + 80006f8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80006fc: d019 beq.n 8000732 <__aeabi_dmul+0x24a> + 80006fe: ea94 0f0c teq r4, ip + 8000702: d102 bne.n 800070a <__aeabi_dmul+0x222> + 8000704: ea50 3601 orrs.w r6, r0, r1, lsl #12 + 8000708: d113 bne.n 8000732 <__aeabi_dmul+0x24a> + 800070a: ea95 0f0c teq r5, ip + 800070e: d105 bne.n 800071c <__aeabi_dmul+0x234> + 8000710: ea52 3603 orrs.w r6, r2, r3, lsl #12 + 8000714: bf1c itt ne + 8000716: 4610 movne r0, r2 + 8000718: 4619 movne r1, r3 + 800071a: d10a bne.n 8000732 <__aeabi_dmul+0x24a> + 800071c: ea81 0103 eor.w r1, r1, r3 + 8000720: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000724: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000728: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 800072c: f04f 0000 mov.w r0, #0 + 8000730: bd70 pop {r4, r5, r6, pc} + 8000732: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000736: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 + 800073a: bd70 pop {r4, r5, r6, pc} + +0800073c <__aeabi_ddiv>: + 800073c: b570 push {r4, r5, r6, lr} + 800073e: f04f 0cff mov.w ip, #255 ; 0xff + 8000742: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 8000746: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 800074a: bf1d ittte ne + 800074c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 8000750: ea94 0f0c teqne r4, ip + 8000754: ea95 0f0c teqne r5, ip + 8000758: f000 f8a7 bleq 80008aa <__aeabi_ddiv+0x16e> + 800075c: eba4 0405 sub.w r4, r4, r5 + 8000760: ea81 0e03 eor.w lr, r1, r3 + 8000764: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 8000768: ea4f 3101 mov.w r1, r1, lsl #12 + 800076c: f000 8088 beq.w 8000880 <__aeabi_ddiv+0x144> + 8000770: ea4f 3303 mov.w r3, r3, lsl #12 + 8000774: f04f 5580 mov.w r5, #268435456 ; 0x10000000 + 8000778: ea45 1313 orr.w r3, r5, r3, lsr #4 + 800077c: ea43 6312 orr.w r3, r3, r2, lsr #24 + 8000780: ea4f 2202 mov.w r2, r2, lsl #8 + 8000784: ea45 1511 orr.w r5, r5, r1, lsr #4 + 8000788: ea45 6510 orr.w r5, r5, r0, lsr #24 + 800078c: ea4f 2600 mov.w r6, r0, lsl #8 + 8000790: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 + 8000794: 429d cmp r5, r3 + 8000796: bf08 it eq + 8000798: 4296 cmpeq r6, r2 + 800079a: f144 04fd adc.w r4, r4, #253 ; 0xfd + 800079e: f504 7440 add.w r4, r4, #768 ; 0x300 + 80007a2: d202 bcs.n 80007aa <__aeabi_ddiv+0x6e> + 80007a4: 085b lsrs r3, r3, #1 + 80007a6: ea4f 0232 mov.w r2, r2, rrx + 80007aa: 1ab6 subs r6, r6, r2 + 80007ac: eb65 0503 sbc.w r5, r5, r3 + 80007b0: 085b lsrs r3, r3, #1 + 80007b2: ea4f 0232 mov.w r2, r2, rrx + 80007b6: f44f 1080 mov.w r0, #1048576 ; 0x100000 + 80007ba: f44f 2c00 mov.w ip, #524288 ; 0x80000 + 80007be: ebb6 0e02 subs.w lr, r6, r2 + 80007c2: eb75 0e03 sbcs.w lr, r5, r3 + 80007c6: bf22 ittt cs + 80007c8: 1ab6 subcs r6, r6, r2 + 80007ca: 4675 movcs r5, lr + 80007cc: ea40 000c orrcs.w r0, r0, ip + 80007d0: 085b lsrs r3, r3, #1 + 80007d2: ea4f 0232 mov.w r2, r2, rrx + 80007d6: ebb6 0e02 subs.w lr, r6, r2 + 80007da: eb75 0e03 sbcs.w lr, r5, r3 + 80007de: bf22 ittt cs + 80007e0: 1ab6 subcs r6, r6, r2 + 80007e2: 4675 movcs r5, lr + 80007e4: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 80007e8: 085b lsrs r3, r3, #1 + 80007ea: ea4f 0232 mov.w r2, r2, rrx + 80007ee: ebb6 0e02 subs.w lr, r6, r2 + 80007f2: eb75 0e03 sbcs.w lr, r5, r3 + 80007f6: bf22 ittt cs + 80007f8: 1ab6 subcs r6, r6, r2 + 80007fa: 4675 movcs r5, lr + 80007fc: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 8000800: 085b lsrs r3, r3, #1 + 8000802: ea4f 0232 mov.w r2, r2, rrx + 8000806: ebb6 0e02 subs.w lr, r6, r2 + 800080a: eb75 0e03 sbcs.w lr, r5, r3 + 800080e: bf22 ittt cs + 8000810: 1ab6 subcs r6, r6, r2 + 8000812: 4675 movcs r5, lr + 8000814: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 8000818: ea55 0e06 orrs.w lr, r5, r6 + 800081c: d018 beq.n 8000850 <__aeabi_ddiv+0x114> + 800081e: ea4f 1505 mov.w r5, r5, lsl #4 + 8000822: ea45 7516 orr.w r5, r5, r6, lsr #28 + 8000826: ea4f 1606 mov.w r6, r6, lsl #4 + 800082a: ea4f 03c3 mov.w r3, r3, lsl #3 + 800082e: ea43 7352 orr.w r3, r3, r2, lsr #29 + 8000832: ea4f 02c2 mov.w r2, r2, lsl #3 + 8000836: ea5f 1c1c movs.w ip, ip, lsr #4 + 800083a: d1c0 bne.n 80007be <__aeabi_ddiv+0x82> + 800083c: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000840: d10b bne.n 800085a <__aeabi_ddiv+0x11e> + 8000842: ea41 0100 orr.w r1, r1, r0 + 8000846: f04f 0000 mov.w r0, #0 + 800084a: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 + 800084e: e7b6 b.n 80007be <__aeabi_ddiv+0x82> + 8000850: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000854: bf04 itt eq + 8000856: 4301 orreq r1, r0 + 8000858: 2000 moveq r0, #0 + 800085a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 800085e: bf88 it hi + 8000860: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 8000864: f63f aeaf bhi.w 80005c6 <__aeabi_dmul+0xde> + 8000868: ebb5 0c03 subs.w ip, r5, r3 + 800086c: bf04 itt eq + 800086e: ebb6 0c02 subseq.w ip, r6, r2 + 8000872: ea5f 0c50 movseq.w ip, r0, lsr #1 + 8000876: f150 0000 adcs.w r0, r0, #0 + 800087a: eb41 5104 adc.w r1, r1, r4, lsl #20 + 800087e: bd70 pop {r4, r5, r6, pc} + 8000880: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 + 8000884: ea4e 3111 orr.w r1, lr, r1, lsr #12 + 8000888: eb14 045c adds.w r4, r4, ip, lsr #1 + 800088c: bfc2 ittt gt + 800088e: ebd4 050c rsbsgt r5, r4, ip + 8000892: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 8000896: bd70 popgt {r4, r5, r6, pc} + 8000898: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 800089c: f04f 0e00 mov.w lr, #0 + 80008a0: 3c01 subs r4, #1 + 80008a2: e690 b.n 80005c6 <__aeabi_dmul+0xde> + 80008a4: ea45 0e06 orr.w lr, r5, r6 + 80008a8: e68d b.n 80005c6 <__aeabi_dmul+0xde> + 80008aa: ea0c 5513 and.w r5, ip, r3, lsr #20 + 80008ae: ea94 0f0c teq r4, ip + 80008b2: bf08 it eq + 80008b4: ea95 0f0c teqeq r5, ip + 80008b8: f43f af3b beq.w 8000732 <__aeabi_dmul+0x24a> + 80008bc: ea94 0f0c teq r4, ip + 80008c0: d10a bne.n 80008d8 <__aeabi_ddiv+0x19c> + 80008c2: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 80008c6: f47f af34 bne.w 8000732 <__aeabi_dmul+0x24a> + 80008ca: ea95 0f0c teq r5, ip + 80008ce: f47f af25 bne.w 800071c <__aeabi_dmul+0x234> + 80008d2: 4610 mov r0, r2 + 80008d4: 4619 mov r1, r3 + 80008d6: e72c b.n 8000732 <__aeabi_dmul+0x24a> + 80008d8: ea95 0f0c teq r5, ip + 80008dc: d106 bne.n 80008ec <__aeabi_ddiv+0x1b0> + 80008de: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 80008e2: f43f aefd beq.w 80006e0 <__aeabi_dmul+0x1f8> + 80008e6: 4610 mov r0, r2 + 80008e8: 4619 mov r1, r3 + 80008ea: e722 b.n 8000732 <__aeabi_dmul+0x24a> + 80008ec: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80008f0: bf18 it ne + 80008f2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80008f6: f47f aec5 bne.w 8000684 <__aeabi_dmul+0x19c> + 80008fa: ea50 0441 orrs.w r4, r0, r1, lsl #1 + 80008fe: f47f af0d bne.w 800071c <__aeabi_dmul+0x234> + 8000902: ea52 0543 orrs.w r5, r2, r3, lsl #1 + 8000906: f47f aeeb bne.w 80006e0 <__aeabi_dmul+0x1f8> + 800090a: e712 b.n 8000732 <__aeabi_dmul+0x24a> + +0800090c <__gedf2>: + 800090c: f04f 3cff mov.w ip, #4294967295 + 8000910: e006 b.n 8000920 <__cmpdf2+0x4> + 8000912: bf00 nop + +08000914 <__ledf2>: + 8000914: f04f 0c01 mov.w ip, #1 + 8000918: e002 b.n 8000920 <__cmpdf2+0x4> + 800091a: bf00 nop + +0800091c <__cmpdf2>: + 800091c: f04f 0c01 mov.w ip, #1 + 8000920: f84d cd04 str.w ip, [sp, #-4]! + 8000924: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000928: ea7f 5c6c mvns.w ip, ip, asr #21 + 800092c: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000930: bf18 it ne + 8000932: ea7f 5c6c mvnsne.w ip, ip, asr #21 + 8000936: d01b beq.n 8000970 <__cmpdf2+0x54> + 8000938: b001 add sp, #4 + 800093a: ea50 0c41 orrs.w ip, r0, r1, lsl #1 + 800093e: bf0c ite eq + 8000940: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 + 8000944: ea91 0f03 teqne r1, r3 + 8000948: bf02 ittt eq + 800094a: ea90 0f02 teqeq r0, r2 + 800094e: 2000 moveq r0, #0 + 8000950: 4770 bxeq lr + 8000952: f110 0f00 cmn.w r0, #0 + 8000956: ea91 0f03 teq r1, r3 + 800095a: bf58 it pl + 800095c: 4299 cmppl r1, r3 + 800095e: bf08 it eq + 8000960: 4290 cmpeq r0, r2 + 8000962: bf2c ite cs + 8000964: 17d8 asrcs r0, r3, #31 + 8000966: ea6f 70e3 mvncc.w r0, r3, asr #31 + 800096a: f040 0001 orr.w r0, r0, #1 + 800096e: 4770 bx lr + 8000970: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000974: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000978: d102 bne.n 8000980 <__cmpdf2+0x64> + 800097a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 800097e: d107 bne.n 8000990 <__cmpdf2+0x74> + 8000980: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000984: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000988: d1d6 bne.n 8000938 <__cmpdf2+0x1c> + 800098a: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 800098e: d0d3 beq.n 8000938 <__cmpdf2+0x1c> + 8000990: f85d 0b04 ldr.w r0, [sp], #4 + 8000994: 4770 bx lr + 8000996: bf00 nop + +08000998 <__aeabi_cdrcmple>: + 8000998: 4684 mov ip, r0 + 800099a: 4610 mov r0, r2 + 800099c: 4662 mov r2, ip + 800099e: 468c mov ip, r1 + 80009a0: 4619 mov r1, r3 + 80009a2: 4663 mov r3, ip + 80009a4: e000 b.n 80009a8 <__aeabi_cdcmpeq> + 80009a6: bf00 nop + +080009a8 <__aeabi_cdcmpeq>: + 80009a8: b501 push {r0, lr} + 80009aa: f7ff ffb7 bl 800091c <__cmpdf2> + 80009ae: 2800 cmp r0, #0 + 80009b0: bf48 it mi + 80009b2: f110 0f00 cmnmi.w r0, #0 + 80009b6: bd01 pop {r0, pc} + +080009b8 <__aeabi_dcmpeq>: + 80009b8: f84d ed08 str.w lr, [sp, #-8]! + 80009bc: f7ff fff4 bl 80009a8 <__aeabi_cdcmpeq> + 80009c0: bf0c ite eq + 80009c2: 2001 moveq r0, #1 + 80009c4: 2000 movne r0, #0 + 80009c6: f85d fb08 ldr.w pc, [sp], #8 + 80009ca: bf00 nop + +080009cc <__aeabi_dcmplt>: + 80009cc: f84d ed08 str.w lr, [sp, #-8]! + 80009d0: f7ff ffea bl 80009a8 <__aeabi_cdcmpeq> + 80009d4: bf34 ite cc + 80009d6: 2001 movcc r0, #1 + 80009d8: 2000 movcs r0, #0 + 80009da: f85d fb08 ldr.w pc, [sp], #8 + 80009de: bf00 nop + +080009e0 <__aeabi_dcmple>: + 80009e0: f84d ed08 str.w lr, [sp, #-8]! + 80009e4: f7ff ffe0 bl 80009a8 <__aeabi_cdcmpeq> + 80009e8: bf94 ite ls + 80009ea: 2001 movls r0, #1 + 80009ec: 2000 movhi r0, #0 + 80009ee: f85d fb08 ldr.w pc, [sp], #8 + 80009f2: bf00 nop + +080009f4 <__aeabi_dcmpge>: + 80009f4: f84d ed08 str.w lr, [sp, #-8]! + 80009f8: f7ff ffce bl 8000998 <__aeabi_cdrcmple> + 80009fc: bf94 ite ls + 80009fe: 2001 movls r0, #1 + 8000a00: 2000 movhi r0, #0 + 8000a02: f85d fb08 ldr.w pc, [sp], #8 + 8000a06: bf00 nop + +08000a08 <__aeabi_dcmpgt>: + 8000a08: f84d ed08 str.w lr, [sp, #-8]! + 8000a0c: f7ff ffc4 bl 8000998 <__aeabi_cdrcmple> + 8000a10: bf34 ite cc + 8000a12: 2001 movcc r0, #1 + 8000a14: 2000 movcs r0, #0 + 8000a16: f85d fb08 ldr.w pc, [sp], #8 + 8000a1a: bf00 nop + +08000a1c <__aeabi_dcmpun>: + 8000a1c: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000a20: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a24: d102 bne.n 8000a2c <__aeabi_dcmpun+0x10> + 8000a26: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8000a2a: d10a bne.n 8000a42 <__aeabi_dcmpun+0x26> + 8000a2c: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000a30: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a34: d102 bne.n 8000a3c <__aeabi_dcmpun+0x20> + 8000a36: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000a3a: d102 bne.n 8000a42 <__aeabi_dcmpun+0x26> + 8000a3c: f04f 0000 mov.w r0, #0 + 8000a40: 4770 bx lr + 8000a42: f04f 0001 mov.w r0, #1 + 8000a46: 4770 bx lr + +08000a48 <__aeabi_d2iz>: + 8000a48: ea4f 0241 mov.w r2, r1, lsl #1 + 8000a4c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000a50: d215 bcs.n 8000a7e <__aeabi_d2iz+0x36> + 8000a52: d511 bpl.n 8000a78 <__aeabi_d2iz+0x30> + 8000a54: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000a58: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000a5c: d912 bls.n 8000a84 <__aeabi_d2iz+0x3c> + 8000a5e: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000a62: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000a66: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000a6a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000a6e: fa23 f002 lsr.w r0, r3, r2 + 8000a72: bf18 it ne + 8000a74: 4240 negne r0, r0 + 8000a76: 4770 bx lr + 8000a78: f04f 0000 mov.w r0, #0 + 8000a7c: 4770 bx lr + 8000a7e: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000a82: d105 bne.n 8000a90 <__aeabi_d2iz+0x48> + 8000a84: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 + 8000a88: bf08 it eq + 8000a8a: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 + 8000a8e: 4770 bx lr + 8000a90: f04f 0000 mov.w r0, #0 + 8000a94: 4770 bx lr + 8000a96: bf00 nop + +08000a98 <__aeabi_d2uiz>: + 8000a98: 004a lsls r2, r1, #1 + 8000a9a: d211 bcs.n 8000ac0 <__aeabi_d2uiz+0x28> + 8000a9c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000aa0: d211 bcs.n 8000ac6 <__aeabi_d2uiz+0x2e> + 8000aa2: d50d bpl.n 8000ac0 <__aeabi_d2uiz+0x28> + 8000aa4: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000aa8: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000aac: d40e bmi.n 8000acc <__aeabi_d2uiz+0x34> + 8000aae: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000ab2: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000ab6: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000aba: fa23 f002 lsr.w r0, r3, r2 + 8000abe: 4770 bx lr + 8000ac0: f04f 0000 mov.w r0, #0 + 8000ac4: 4770 bx lr + 8000ac6: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000aca: d102 bne.n 8000ad2 <__aeabi_d2uiz+0x3a> + 8000acc: f04f 30ff mov.w r0, #4294967295 + 8000ad0: 4770 bx lr + 8000ad2: f04f 0000 mov.w r0, #0 + 8000ad6: 4770 bx lr + +08000ad8 <__aeabi_d2f>: + 8000ad8: ea4f 0241 mov.w r2, r1, lsl #1 + 8000adc: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 + 8000ae0: bf24 itt cs + 8000ae2: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 + 8000ae6: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 + 8000aea: d90d bls.n 8000b08 <__aeabi_d2f+0x30> + 8000aec: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 + 8000af0: ea4f 02c0 mov.w r2, r0, lsl #3 + 8000af4: ea4c 7050 orr.w r0, ip, r0, lsr #29 + 8000af8: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 + 8000afc: eb40 0083 adc.w r0, r0, r3, lsl #2 + 8000b00: bf08 it eq + 8000b02: f020 0001 biceq.w r0, r0, #1 + 8000b06: 4770 bx lr + 8000b08: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 + 8000b0c: d121 bne.n 8000b52 <__aeabi_d2f+0x7a> + 8000b0e: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 + 8000b12: bfbc itt lt + 8000b14: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 + 8000b18: 4770 bxlt lr + 8000b1a: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000b1e: ea4f 5252 mov.w r2, r2, lsr #21 + 8000b22: f1c2 0218 rsb r2, r2, #24 + 8000b26: f1c2 0c20 rsb ip, r2, #32 + 8000b2a: fa10 f30c lsls.w r3, r0, ip + 8000b2e: fa20 f002 lsr.w r0, r0, r2 + 8000b32: bf18 it ne + 8000b34: f040 0001 orrne.w r0, r0, #1 + 8000b38: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000b3c: ea4f 23d3 mov.w r3, r3, lsr #11 + 8000b40: fa03 fc0c lsl.w ip, r3, ip + 8000b44: ea40 000c orr.w r0, r0, ip + 8000b48: fa23 f302 lsr.w r3, r3, r2 + 8000b4c: ea4f 0343 mov.w r3, r3, lsl #1 + 8000b50: e7cc b.n 8000aec <__aeabi_d2f+0x14> + 8000b52: ea7f 5362 mvns.w r3, r2, asr #21 + 8000b56: d107 bne.n 8000b68 <__aeabi_d2f+0x90> + 8000b58: ea50 3301 orrs.w r3, r0, r1, lsl #12 + 8000b5c: bf1e ittt ne + 8000b5e: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 + 8000b62: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 + 8000b66: 4770 bxne lr + 8000b68: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 + 8000b6c: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 + 8000b70: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000b74: 4770 bx lr + 8000b76: bf00 nop + +08000b78 <__aeabi_frsub>: + 8000b78: f080 4000 eor.w r0, r0, #2147483648 ; 0x80000000 + 8000b7c: e002 b.n 8000b84 <__addsf3> + 8000b7e: bf00 nop + +08000b80 <__aeabi_fsub>: + 8000b80: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 + +08000b84 <__addsf3>: + 8000b84: 0042 lsls r2, r0, #1 + 8000b86: bf1f itttt ne + 8000b88: ea5f 0341 movsne.w r3, r1, lsl #1 + 8000b8c: ea92 0f03 teqne r2, r3 + 8000b90: ea7f 6c22 mvnsne.w ip, r2, asr #24 + 8000b94: ea7f 6c23 mvnsne.w ip, r3, asr #24 + 8000b98: d06a beq.n 8000c70 <__addsf3+0xec> + 8000b9a: ea4f 6212 mov.w r2, r2, lsr #24 + 8000b9e: ebd2 6313 rsbs r3, r2, r3, lsr #24 + 8000ba2: bfc1 itttt gt + 8000ba4: 18d2 addgt r2, r2, r3 + 8000ba6: 4041 eorgt r1, r0 + 8000ba8: 4048 eorgt r0, r1 + 8000baa: 4041 eorgt r1, r0 + 8000bac: bfb8 it lt + 8000bae: 425b neglt r3, r3 + 8000bb0: 2b19 cmp r3, #25 + 8000bb2: bf88 it hi + 8000bb4: 4770 bxhi lr + 8000bb6: f010 4f00 tst.w r0, #2147483648 ; 0x80000000 + 8000bba: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000bbe: f020 407f bic.w r0, r0, #4278190080 ; 0xff000000 + 8000bc2: bf18 it ne + 8000bc4: 4240 negne r0, r0 + 8000bc6: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000bca: f441 0100 orr.w r1, r1, #8388608 ; 0x800000 + 8000bce: f021 417f bic.w r1, r1, #4278190080 ; 0xff000000 + 8000bd2: bf18 it ne + 8000bd4: 4249 negne r1, r1 + 8000bd6: ea92 0f03 teq r2, r3 + 8000bda: d03f beq.n 8000c5c <__addsf3+0xd8> + 8000bdc: f1a2 0201 sub.w r2, r2, #1 + 8000be0: fa41 fc03 asr.w ip, r1, r3 + 8000be4: eb10 000c adds.w r0, r0, ip + 8000be8: f1c3 0320 rsb r3, r3, #32 + 8000bec: fa01 f103 lsl.w r1, r1, r3 + 8000bf0: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 + 8000bf4: d502 bpl.n 8000bfc <__addsf3+0x78> + 8000bf6: 4249 negs r1, r1 + 8000bf8: eb60 0040 sbc.w r0, r0, r0, lsl #1 + 8000bfc: f5b0 0f00 cmp.w r0, #8388608 ; 0x800000 + 8000c00: d313 bcc.n 8000c2a <__addsf3+0xa6> + 8000c02: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 + 8000c06: d306 bcc.n 8000c16 <__addsf3+0x92> + 8000c08: 0840 lsrs r0, r0, #1 + 8000c0a: ea4f 0131 mov.w r1, r1, rrx + 8000c0e: f102 0201 add.w r2, r2, #1 + 8000c12: 2afe cmp r2, #254 ; 0xfe + 8000c14: d251 bcs.n 8000cba <__addsf3+0x136> + 8000c16: f1b1 4f00 cmp.w r1, #2147483648 ; 0x80000000 + 8000c1a: eb40 50c2 adc.w r0, r0, r2, lsl #23 + 8000c1e: bf08 it eq + 8000c20: f020 0001 biceq.w r0, r0, #1 + 8000c24: ea40 0003 orr.w r0, r0, r3 + 8000c28: 4770 bx lr + 8000c2a: 0049 lsls r1, r1, #1 + 8000c2c: eb40 0000 adc.w r0, r0, r0 + 8000c30: f410 0f00 tst.w r0, #8388608 ; 0x800000 + 8000c34: f1a2 0201 sub.w r2, r2, #1 + 8000c38: d1ed bne.n 8000c16 <__addsf3+0x92> + 8000c3a: fab0 fc80 clz ip, r0 + 8000c3e: f1ac 0c08 sub.w ip, ip, #8 + 8000c42: ebb2 020c subs.w r2, r2, ip + 8000c46: fa00 f00c lsl.w r0, r0, ip + 8000c4a: bfaa itet ge + 8000c4c: eb00 50c2 addge.w r0, r0, r2, lsl #23 + 8000c50: 4252 neglt r2, r2 + 8000c52: 4318 orrge r0, r3 + 8000c54: bfbc itt lt + 8000c56: 40d0 lsrlt r0, r2 + 8000c58: 4318 orrlt r0, r3 + 8000c5a: 4770 bx lr + 8000c5c: f092 0f00 teq r2, #0 + 8000c60: f481 0100 eor.w r1, r1, #8388608 ; 0x800000 + 8000c64: bf06 itte eq + 8000c66: f480 0000 eoreq.w r0, r0, #8388608 ; 0x800000 + 8000c6a: 3201 addeq r2, #1 + 8000c6c: 3b01 subne r3, #1 + 8000c6e: e7b5 b.n 8000bdc <__addsf3+0x58> + 8000c70: ea4f 0341 mov.w r3, r1, lsl #1 + 8000c74: ea7f 6c22 mvns.w ip, r2, asr #24 + 8000c78: bf18 it ne + 8000c7a: ea7f 6c23 mvnsne.w ip, r3, asr #24 + 8000c7e: d021 beq.n 8000cc4 <__addsf3+0x140> + 8000c80: ea92 0f03 teq r2, r3 + 8000c84: d004 beq.n 8000c90 <__addsf3+0x10c> + 8000c86: f092 0f00 teq r2, #0 + 8000c8a: bf08 it eq + 8000c8c: 4608 moveq r0, r1 + 8000c8e: 4770 bx lr + 8000c90: ea90 0f01 teq r0, r1 + 8000c94: bf1c itt ne + 8000c96: 2000 movne r0, #0 + 8000c98: 4770 bxne lr + 8000c9a: f012 4f7f tst.w r2, #4278190080 ; 0xff000000 + 8000c9e: d104 bne.n 8000caa <__addsf3+0x126> + 8000ca0: 0040 lsls r0, r0, #1 + 8000ca2: bf28 it cs + 8000ca4: f040 4000 orrcs.w r0, r0, #2147483648 ; 0x80000000 + 8000ca8: 4770 bx lr + 8000caa: f112 7200 adds.w r2, r2, #33554432 ; 0x2000000 + 8000cae: bf3c itt cc + 8000cb0: f500 0000 addcc.w r0, r0, #8388608 ; 0x800000 + 8000cb4: 4770 bxcc lr + 8000cb6: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 + 8000cba: f043 40fe orr.w r0, r3, #2130706432 ; 0x7f000000 + 8000cbe: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000cc2: 4770 bx lr + 8000cc4: ea7f 6222 mvns.w r2, r2, asr #24 + 8000cc8: bf16 itet ne + 8000cca: 4608 movne r0, r1 + 8000ccc: ea7f 6323 mvnseq.w r3, r3, asr #24 + 8000cd0: 4601 movne r1, r0 + 8000cd2: 0242 lsls r2, r0, #9 + 8000cd4: bf06 itte eq + 8000cd6: ea5f 2341 movseq.w r3, r1, lsl #9 + 8000cda: ea90 0f01 teqeq r0, r1 + 8000cde: f440 0080 orrne.w r0, r0, #4194304 ; 0x400000 + 8000ce2: 4770 bx lr + +08000ce4 <__aeabi_ui2f>: + 8000ce4: f04f 0300 mov.w r3, #0 + 8000ce8: e004 b.n 8000cf4 <__aeabi_i2f+0x8> + 8000cea: bf00 nop + +08000cec <__aeabi_i2f>: + 8000cec: f010 4300 ands.w r3, r0, #2147483648 ; 0x80000000 + 8000cf0: bf48 it mi + 8000cf2: 4240 negmi r0, r0 + 8000cf4: ea5f 0c00 movs.w ip, r0 + 8000cf8: bf08 it eq + 8000cfa: 4770 bxeq lr + 8000cfc: f043 4396 orr.w r3, r3, #1258291200 ; 0x4b000000 + 8000d00: 4601 mov r1, r0 + 8000d02: f04f 0000 mov.w r0, #0 + 8000d06: e01c b.n 8000d42 <__aeabi_l2f+0x2a> + +08000d08 <__aeabi_ul2f>: + 8000d08: ea50 0201 orrs.w r2, r0, r1 + 8000d0c: bf08 it eq + 8000d0e: 4770 bxeq lr + 8000d10: f04f 0300 mov.w r3, #0 + 8000d14: e00a b.n 8000d2c <__aeabi_l2f+0x14> + 8000d16: bf00 nop + +08000d18 <__aeabi_l2f>: + 8000d18: ea50 0201 orrs.w r2, r0, r1 + 8000d1c: bf08 it eq + 8000d1e: 4770 bxeq lr + 8000d20: f011 4300 ands.w r3, r1, #2147483648 ; 0x80000000 + 8000d24: d502 bpl.n 8000d2c <__aeabi_l2f+0x14> + 8000d26: 4240 negs r0, r0 + 8000d28: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8000d2c: ea5f 0c01 movs.w ip, r1 + 8000d30: bf02 ittt eq + 8000d32: 4684 moveq ip, r0 + 8000d34: 4601 moveq r1, r0 + 8000d36: 2000 moveq r0, #0 + 8000d38: f043 43b6 orr.w r3, r3, #1526726656 ; 0x5b000000 + 8000d3c: bf08 it eq + 8000d3e: f1a3 5380 subeq.w r3, r3, #268435456 ; 0x10000000 + 8000d42: f5a3 0300 sub.w r3, r3, #8388608 ; 0x800000 + 8000d46: fabc f28c clz r2, ip + 8000d4a: 3a08 subs r2, #8 + 8000d4c: eba3 53c2 sub.w r3, r3, r2, lsl #23 + 8000d50: db10 blt.n 8000d74 <__aeabi_l2f+0x5c> + 8000d52: fa01 fc02 lsl.w ip, r1, r2 + 8000d56: 4463 add r3, ip + 8000d58: fa00 fc02 lsl.w ip, r0, r2 + 8000d5c: f1c2 0220 rsb r2, r2, #32 + 8000d60: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 + 8000d64: fa20 f202 lsr.w r2, r0, r2 + 8000d68: eb43 0002 adc.w r0, r3, r2 + 8000d6c: bf08 it eq + 8000d6e: f020 0001 biceq.w r0, r0, #1 + 8000d72: 4770 bx lr + 8000d74: f102 0220 add.w r2, r2, #32 + 8000d78: fa01 fc02 lsl.w ip, r1, r2 + 8000d7c: f1c2 0220 rsb r2, r2, #32 + 8000d80: ea50 004c orrs.w r0, r0, ip, lsl #1 + 8000d84: fa21 f202 lsr.w r2, r1, r2 + 8000d88: eb43 0002 adc.w r0, r3, r2 + 8000d8c: bf08 it eq + 8000d8e: ea20 70dc biceq.w r0, r0, ip, lsr #31 + 8000d92: 4770 bx lr + +08000d94 <__aeabi_fmul>: + 8000d94: f04f 0cff mov.w ip, #255 ; 0xff + 8000d98: ea1c 52d0 ands.w r2, ip, r0, lsr #23 + 8000d9c: bf1e ittt ne + 8000d9e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 + 8000da2: ea92 0f0c teqne r2, ip + 8000da6: ea93 0f0c teqne r3, ip + 8000daa: d06f beq.n 8000e8c <__aeabi_fmul+0xf8> + 8000dac: 441a add r2, r3 + 8000dae: ea80 0c01 eor.w ip, r0, r1 + 8000db2: 0240 lsls r0, r0, #9 + 8000db4: bf18 it ne + 8000db6: ea5f 2141 movsne.w r1, r1, lsl #9 + 8000dba: d01e beq.n 8000dfa <__aeabi_fmul+0x66> + 8000dbc: f04f 6300 mov.w r3, #134217728 ; 0x8000000 + 8000dc0: ea43 1050 orr.w r0, r3, r0, lsr #5 + 8000dc4: ea43 1151 orr.w r1, r3, r1, lsr #5 + 8000dc8: fba0 3101 umull r3, r1, r0, r1 + 8000dcc: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 + 8000dd0: f5b1 0f00 cmp.w r1, #8388608 ; 0x800000 + 8000dd4: bf3e ittt cc + 8000dd6: 0049 lslcc r1, r1, #1 + 8000dd8: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 + 8000ddc: 005b lslcc r3, r3, #1 + 8000dde: ea40 0001 orr.w r0, r0, r1 + 8000de2: f162 027f sbc.w r2, r2, #127 ; 0x7f + 8000de6: 2afd cmp r2, #253 ; 0xfd + 8000de8: d81d bhi.n 8000e26 <__aeabi_fmul+0x92> + 8000dea: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 8000dee: eb40 50c2 adc.w r0, r0, r2, lsl #23 + 8000df2: bf08 it eq + 8000df4: f020 0001 biceq.w r0, r0, #1 + 8000df8: 4770 bx lr + 8000dfa: f090 0f00 teq r0, #0 + 8000dfe: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 + 8000e02: bf08 it eq + 8000e04: 0249 lsleq r1, r1, #9 + 8000e06: ea4c 2050 orr.w r0, ip, r0, lsr #9 + 8000e0a: ea40 2051 orr.w r0, r0, r1, lsr #9 + 8000e0e: 3a7f subs r2, #127 ; 0x7f + 8000e10: bfc2 ittt gt + 8000e12: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff + 8000e16: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 + 8000e1a: 4770 bxgt lr + 8000e1c: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000e20: f04f 0300 mov.w r3, #0 + 8000e24: 3a01 subs r2, #1 + 8000e26: dc5d bgt.n 8000ee4 <__aeabi_fmul+0x150> + 8000e28: f112 0f19 cmn.w r2, #25 + 8000e2c: bfdc itt le + 8000e2e: f000 4000 andle.w r0, r0, #2147483648 ; 0x80000000 + 8000e32: 4770 bxle lr + 8000e34: f1c2 0200 rsb r2, r2, #0 + 8000e38: 0041 lsls r1, r0, #1 + 8000e3a: fa21 f102 lsr.w r1, r1, r2 + 8000e3e: f1c2 0220 rsb r2, r2, #32 + 8000e42: fa00 fc02 lsl.w ip, r0, r2 + 8000e46: ea5f 0031 movs.w r0, r1, rrx + 8000e4a: f140 0000 adc.w r0, r0, #0 + 8000e4e: ea53 034c orrs.w r3, r3, ip, lsl #1 + 8000e52: bf08 it eq + 8000e54: ea20 70dc biceq.w r0, r0, ip, lsr #31 + 8000e58: 4770 bx lr + 8000e5a: f092 0f00 teq r2, #0 + 8000e5e: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 + 8000e62: bf02 ittt eq + 8000e64: 0040 lsleq r0, r0, #1 + 8000e66: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 + 8000e6a: 3a01 subeq r2, #1 + 8000e6c: d0f9 beq.n 8000e62 <__aeabi_fmul+0xce> + 8000e6e: ea40 000c orr.w r0, r0, ip + 8000e72: f093 0f00 teq r3, #0 + 8000e76: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 + 8000e7a: bf02 ittt eq + 8000e7c: 0049 lsleq r1, r1, #1 + 8000e7e: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 + 8000e82: 3b01 subeq r3, #1 + 8000e84: d0f9 beq.n 8000e7a <__aeabi_fmul+0xe6> + 8000e86: ea41 010c orr.w r1, r1, ip + 8000e8a: e78f b.n 8000dac <__aeabi_fmul+0x18> + 8000e8c: ea0c 53d1 and.w r3, ip, r1, lsr #23 + 8000e90: ea92 0f0c teq r2, ip + 8000e94: bf18 it ne + 8000e96: ea93 0f0c teqne r3, ip + 8000e9a: d00a beq.n 8000eb2 <__aeabi_fmul+0x11e> + 8000e9c: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 + 8000ea0: bf18 it ne + 8000ea2: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 + 8000ea6: d1d8 bne.n 8000e5a <__aeabi_fmul+0xc6> + 8000ea8: ea80 0001 eor.w r0, r0, r1 + 8000eac: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 + 8000eb0: 4770 bx lr + 8000eb2: f090 0f00 teq r0, #0 + 8000eb6: bf17 itett ne + 8000eb8: f090 4f00 teqne r0, #2147483648 ; 0x80000000 + 8000ebc: 4608 moveq r0, r1 + 8000ebe: f091 0f00 teqne r1, #0 + 8000ec2: f091 4f00 teqne r1, #2147483648 ; 0x80000000 + 8000ec6: d014 beq.n 8000ef2 <__aeabi_fmul+0x15e> + 8000ec8: ea92 0f0c teq r2, ip + 8000ecc: d101 bne.n 8000ed2 <__aeabi_fmul+0x13e> + 8000ece: 0242 lsls r2, r0, #9 + 8000ed0: d10f bne.n 8000ef2 <__aeabi_fmul+0x15e> + 8000ed2: ea93 0f0c teq r3, ip + 8000ed6: d103 bne.n 8000ee0 <__aeabi_fmul+0x14c> + 8000ed8: 024b lsls r3, r1, #9 + 8000eda: bf18 it ne + 8000edc: 4608 movne r0, r1 + 8000ede: d108 bne.n 8000ef2 <__aeabi_fmul+0x15e> + 8000ee0: ea80 0001 eor.w r0, r0, r1 + 8000ee4: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 + 8000ee8: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 + 8000eec: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000ef0: 4770 bx lr + 8000ef2: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 + 8000ef6: f440 0040 orr.w r0, r0, #12582912 ; 0xc00000 + 8000efa: 4770 bx lr + +08000efc <__aeabi_fdiv>: + 8000efc: f04f 0cff mov.w ip, #255 ; 0xff + 8000f00: ea1c 52d0 ands.w r2, ip, r0, lsr #23 + 8000f04: bf1e ittt ne + 8000f06: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 + 8000f0a: ea92 0f0c teqne r2, ip + 8000f0e: ea93 0f0c teqne r3, ip + 8000f12: d069 beq.n 8000fe8 <__aeabi_fdiv+0xec> + 8000f14: eba2 0203 sub.w r2, r2, r3 + 8000f18: ea80 0c01 eor.w ip, r0, r1 + 8000f1c: 0249 lsls r1, r1, #9 + 8000f1e: ea4f 2040 mov.w r0, r0, lsl #9 + 8000f22: d037 beq.n 8000f94 <__aeabi_fdiv+0x98> + 8000f24: f04f 5380 mov.w r3, #268435456 ; 0x10000000 + 8000f28: ea43 1111 orr.w r1, r3, r1, lsr #4 + 8000f2c: ea43 1310 orr.w r3, r3, r0, lsr #4 + 8000f30: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 + 8000f34: 428b cmp r3, r1 + 8000f36: bf38 it cc + 8000f38: 005b lslcc r3, r3, #1 + 8000f3a: f142 027d adc.w r2, r2, #125 ; 0x7d + 8000f3e: f44f 0c00 mov.w ip, #8388608 ; 0x800000 + 8000f42: 428b cmp r3, r1 + 8000f44: bf24 itt cs + 8000f46: 1a5b subcs r3, r3, r1 + 8000f48: ea40 000c orrcs.w r0, r0, ip + 8000f4c: ebb3 0f51 cmp.w r3, r1, lsr #1 + 8000f50: bf24 itt cs + 8000f52: eba3 0351 subcs.w r3, r3, r1, lsr #1 + 8000f56: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 8000f5a: ebb3 0f91 cmp.w r3, r1, lsr #2 + 8000f5e: bf24 itt cs + 8000f60: eba3 0391 subcs.w r3, r3, r1, lsr #2 + 8000f64: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 8000f68: ebb3 0fd1 cmp.w r3, r1, lsr #3 + 8000f6c: bf24 itt cs + 8000f6e: eba3 03d1 subcs.w r3, r3, r1, lsr #3 + 8000f72: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 8000f76: 011b lsls r3, r3, #4 + 8000f78: bf18 it ne + 8000f7a: ea5f 1c1c movsne.w ip, ip, lsr #4 + 8000f7e: d1e0 bne.n 8000f42 <__aeabi_fdiv+0x46> + 8000f80: 2afd cmp r2, #253 ; 0xfd + 8000f82: f63f af50 bhi.w 8000e26 <__aeabi_fmul+0x92> + 8000f86: 428b cmp r3, r1 + 8000f88: eb40 50c2 adc.w r0, r0, r2, lsl #23 + 8000f8c: bf08 it eq + 8000f8e: f020 0001 biceq.w r0, r0, #1 + 8000f92: 4770 bx lr + 8000f94: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 + 8000f98: ea4c 2050 orr.w r0, ip, r0, lsr #9 + 8000f9c: 327f adds r2, #127 ; 0x7f + 8000f9e: bfc2 ittt gt + 8000fa0: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff + 8000fa4: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 + 8000fa8: 4770 bxgt lr + 8000faa: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000fae: f04f 0300 mov.w r3, #0 + 8000fb2: 3a01 subs r2, #1 + 8000fb4: e737 b.n 8000e26 <__aeabi_fmul+0x92> + 8000fb6: f092 0f00 teq r2, #0 + 8000fba: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 + 8000fbe: bf02 ittt eq + 8000fc0: 0040 lsleq r0, r0, #1 + 8000fc2: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 + 8000fc6: 3a01 subeq r2, #1 + 8000fc8: d0f9 beq.n 8000fbe <__aeabi_fdiv+0xc2> + 8000fca: ea40 000c orr.w r0, r0, ip + 8000fce: f093 0f00 teq r3, #0 + 8000fd2: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 + 8000fd6: bf02 ittt eq + 8000fd8: 0049 lsleq r1, r1, #1 + 8000fda: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 + 8000fde: 3b01 subeq r3, #1 + 8000fe0: d0f9 beq.n 8000fd6 <__aeabi_fdiv+0xda> + 8000fe2: ea41 010c orr.w r1, r1, ip + 8000fe6: e795 b.n 8000f14 <__aeabi_fdiv+0x18> + 8000fe8: ea0c 53d1 and.w r3, ip, r1, lsr #23 + 8000fec: ea92 0f0c teq r2, ip + 8000ff0: d108 bne.n 8001004 <__aeabi_fdiv+0x108> + 8000ff2: 0242 lsls r2, r0, #9 + 8000ff4: f47f af7d bne.w 8000ef2 <__aeabi_fmul+0x15e> + 8000ff8: ea93 0f0c teq r3, ip + 8000ffc: f47f af70 bne.w 8000ee0 <__aeabi_fmul+0x14c> + 8001000: 4608 mov r0, r1 + 8001002: e776 b.n 8000ef2 <__aeabi_fmul+0x15e> + 8001004: ea93 0f0c teq r3, ip + 8001008: d104 bne.n 8001014 <__aeabi_fdiv+0x118> + 800100a: 024b lsls r3, r1, #9 + 800100c: f43f af4c beq.w 8000ea8 <__aeabi_fmul+0x114> + 8001010: 4608 mov r0, r1 + 8001012: e76e b.n 8000ef2 <__aeabi_fmul+0x15e> + 8001014: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 + 8001018: bf18 it ne + 800101a: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 + 800101e: d1ca bne.n 8000fb6 <__aeabi_fdiv+0xba> + 8001020: f030 4200 bics.w r2, r0, #2147483648 ; 0x80000000 + 8001024: f47f af5c bne.w 8000ee0 <__aeabi_fmul+0x14c> + 8001028: f031 4300 bics.w r3, r1, #2147483648 ; 0x80000000 + 800102c: f47f af3c bne.w 8000ea8 <__aeabi_fmul+0x114> + 8001030: e75f b.n 8000ef2 <__aeabi_fmul+0x15e> + 8001032: bf00 nop + +08001034 <__gesf2>: + 8001034: f04f 3cff mov.w ip, #4294967295 + 8001038: e006 b.n 8001048 <__cmpsf2+0x4> + 800103a: bf00 nop + +0800103c <__lesf2>: + 800103c: f04f 0c01 mov.w ip, #1 + 8001040: e002 b.n 8001048 <__cmpsf2+0x4> + 8001042: bf00 nop + +08001044 <__cmpsf2>: + 8001044: f04f 0c01 mov.w ip, #1 + 8001048: f84d cd04 str.w ip, [sp, #-4]! + 800104c: ea4f 0240 mov.w r2, r0, lsl #1 + 8001050: ea4f 0341 mov.w r3, r1, lsl #1 + 8001054: ea7f 6c22 mvns.w ip, r2, asr #24 + 8001058: bf18 it ne + 800105a: ea7f 6c23 mvnsne.w ip, r3, asr #24 + 800105e: d011 beq.n 8001084 <__cmpsf2+0x40> + 8001060: b001 add sp, #4 + 8001062: ea52 0c53 orrs.w ip, r2, r3, lsr #1 + 8001066: bf18 it ne + 8001068: ea90 0f01 teqne r0, r1 + 800106c: bf58 it pl + 800106e: ebb2 0003 subspl.w r0, r2, r3 + 8001072: bf88 it hi + 8001074: 17c8 asrhi r0, r1, #31 + 8001076: bf38 it cc + 8001078: ea6f 70e1 mvncc.w r0, r1, asr #31 + 800107c: bf18 it ne + 800107e: f040 0001 orrne.w r0, r0, #1 + 8001082: 4770 bx lr + 8001084: ea7f 6c22 mvns.w ip, r2, asr #24 + 8001088: d102 bne.n 8001090 <__cmpsf2+0x4c> + 800108a: ea5f 2c40 movs.w ip, r0, lsl #9 + 800108e: d105 bne.n 800109c <__cmpsf2+0x58> + 8001090: ea7f 6c23 mvns.w ip, r3, asr #24 + 8001094: d1e4 bne.n 8001060 <__cmpsf2+0x1c> + 8001096: ea5f 2c41 movs.w ip, r1, lsl #9 + 800109a: d0e1 beq.n 8001060 <__cmpsf2+0x1c> + 800109c: f85d 0b04 ldr.w r0, [sp], #4 + 80010a0: 4770 bx lr + 80010a2: bf00 nop + +080010a4 <__aeabi_cfrcmple>: + 80010a4: 4684 mov ip, r0 + 80010a6: 4608 mov r0, r1 + 80010a8: 4661 mov r1, ip + 80010aa: e7ff b.n 80010ac <__aeabi_cfcmpeq> + +080010ac <__aeabi_cfcmpeq>: + 80010ac: b50f push {r0, r1, r2, r3, lr} + 80010ae: f7ff ffc9 bl 8001044 <__cmpsf2> + 80010b2: 2800 cmp r0, #0 + 80010b4: bf48 it mi + 80010b6: f110 0f00 cmnmi.w r0, #0 + 80010ba: bd0f pop {r0, r1, r2, r3, pc} + +080010bc <__aeabi_fcmpeq>: + 80010bc: f84d ed08 str.w lr, [sp, #-8]! + 80010c0: f7ff fff4 bl 80010ac <__aeabi_cfcmpeq> + 80010c4: bf0c ite eq + 80010c6: 2001 moveq r0, #1 + 80010c8: 2000 movne r0, #0 + 80010ca: f85d fb08 ldr.w pc, [sp], #8 + 80010ce: bf00 nop + +080010d0 <__aeabi_fcmplt>: + 80010d0: f84d ed08 str.w lr, [sp, #-8]! + 80010d4: f7ff ffea bl 80010ac <__aeabi_cfcmpeq> + 80010d8: bf34 ite cc + 80010da: 2001 movcc r0, #1 + 80010dc: 2000 movcs r0, #0 + 80010de: f85d fb08 ldr.w pc, [sp], #8 + 80010e2: bf00 nop + +080010e4 <__aeabi_fcmple>: + 80010e4: f84d ed08 str.w lr, [sp, #-8]! + 80010e8: f7ff ffe0 bl 80010ac <__aeabi_cfcmpeq> + 80010ec: bf94 ite ls + 80010ee: 2001 movls r0, #1 + 80010f0: 2000 movhi r0, #0 + 80010f2: f85d fb08 ldr.w pc, [sp], #8 + 80010f6: bf00 nop + +080010f8 <__aeabi_fcmpge>: + 80010f8: f84d ed08 str.w lr, [sp, #-8]! + 80010fc: f7ff ffd2 bl 80010a4 <__aeabi_cfrcmple> + 8001100: bf94 ite ls + 8001102: 2001 movls r0, #1 + 8001104: 2000 movhi r0, #0 + 8001106: f85d fb08 ldr.w pc, [sp], #8 + 800110a: bf00 nop + +0800110c <__aeabi_fcmpgt>: + 800110c: f84d ed08 str.w lr, [sp, #-8]! + 8001110: f7ff ffc8 bl 80010a4 <__aeabi_cfrcmple> + 8001114: bf34 ite cc + 8001116: 2001 movcc r0, #1 + 8001118: 2000 movcs r0, #0 + 800111a: f85d fb08 ldr.w pc, [sp], #8 + 800111e: bf00 nop + +08001120 <__aeabi_f2iz>: + 8001120: ea4f 0240 mov.w r2, r0, lsl #1 + 8001124: f1b2 4ffe cmp.w r2, #2130706432 ; 0x7f000000 + 8001128: d30f bcc.n 800114a <__aeabi_f2iz+0x2a> + 800112a: f04f 039e mov.w r3, #158 ; 0x9e + 800112e: ebb3 6212 subs.w r2, r3, r2, lsr #24 + 8001132: d90d bls.n 8001150 <__aeabi_f2iz+0x30> + 8001134: ea4f 2300 mov.w r3, r0, lsl #8 + 8001138: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 800113c: f010 4f00 tst.w r0, #2147483648 ; 0x80000000 + 8001140: fa23 f002 lsr.w r0, r3, r2 + 8001144: bf18 it ne + 8001146: 4240 negne r0, r0 + 8001148: 4770 bx lr + 800114a: f04f 0000 mov.w r0, #0 + 800114e: 4770 bx lr + 8001150: f112 0f61 cmn.w r2, #97 ; 0x61 + 8001154: d101 bne.n 800115a <__aeabi_f2iz+0x3a> + 8001156: 0242 lsls r2, r0, #9 + 8001158: d105 bne.n 8001166 <__aeabi_f2iz+0x46> + 800115a: f010 4000 ands.w r0, r0, #2147483648 ; 0x80000000 + 800115e: bf08 it eq + 8001160: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 + 8001164: 4770 bx lr + 8001166: f04f 0000 mov.w r0, #0 + 800116a: 4770 bx lr + +0800116c <__aeabi_f2uiz>: + 800116c: 0042 lsls r2, r0, #1 + 800116e: d20e bcs.n 800118e <__aeabi_f2uiz+0x22> + 8001170: f1b2 4ffe cmp.w r2, #2130706432 ; 0x7f000000 + 8001174: d30b bcc.n 800118e <__aeabi_f2uiz+0x22> + 8001176: f04f 039e mov.w r3, #158 ; 0x9e + 800117a: ebb3 6212 subs.w r2, r3, r2, lsr #24 + 800117e: d409 bmi.n 8001194 <__aeabi_f2uiz+0x28> + 8001180: ea4f 2300 mov.w r3, r0, lsl #8 + 8001184: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8001188: fa23 f002 lsr.w r0, r3, r2 + 800118c: 4770 bx lr + 800118e: f04f 0000 mov.w r0, #0 + 8001192: 4770 bx lr + 8001194: f112 0f61 cmn.w r2, #97 ; 0x61 + 8001198: d101 bne.n 800119e <__aeabi_f2uiz+0x32> + 800119a: 0242 lsls r2, r0, #9 + 800119c: d102 bne.n 80011a4 <__aeabi_f2uiz+0x38> + 800119e: f04f 30ff mov.w r0, #4294967295 + 80011a2: 4770 bx lr + 80011a4: f04f 0000 mov.w r0, #0 + 80011a8: 4770 bx lr + 80011aa: bf00 nop + +080011ac : + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 80011ac: b580 push {r7, lr} + 80011ae: af00 add r7, sp, #0 + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + 80011b0: 4b15 ldr r3, [pc, #84] ; (8001208 ) + 80011b2: 681b ldr r3, [r3, #0] + 80011b4: 4a14 ldr r2, [pc, #80] ; (8001208 ) + 80011b6: f043 0301 orr.w r3, r3, #1 + 80011ba: 6013 str r3, [r2, #0] + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; + 80011bc: 4b12 ldr r3, [pc, #72] ; (8001208 ) + 80011be: 685a ldr r2, [r3, #4] + 80011c0: 4911 ldr r1, [pc, #68] ; (8001208 ) + 80011c2: 4b12 ldr r3, [pc, #72] ; (800120c ) + 80011c4: 4013 ands r3, r2 + 80011c6: 604b str r3, [r1, #4] +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + 80011c8: 4b0f ldr r3, [pc, #60] ; (8001208 ) + 80011ca: 681b ldr r3, [r3, #0] + 80011cc: 4a0e ldr r2, [pc, #56] ; (8001208 ) + 80011ce: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 + 80011d2: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80011d6: 6013 str r3, [r2, #0] + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + 80011d8: 4b0b ldr r3, [pc, #44] ; (8001208 ) + 80011da: 681b ldr r3, [r3, #0] + 80011dc: 4a0a ldr r2, [pc, #40] ; (8001208 ) + 80011de: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80011e2: 6013 str r3, [r2, #0] + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + 80011e4: 4b08 ldr r3, [pc, #32] ; (8001208 ) + 80011e6: 685b ldr r3, [r3, #4] + 80011e8: 4a07 ldr r2, [pc, #28] ; (8001208 ) + 80011ea: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 + 80011ee: 6053 str r3, [r2, #4] + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + 80011f0: 4b05 ldr r3, [pc, #20] ; (8001208 ) + 80011f2: f44f 021f mov.w r2, #10420224 ; 0x9f0000 + 80011f6: 609a str r2, [r3, #8] + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + 80011f8: f000 f80c bl 8001214 + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ + 80011fc: 4b04 ldr r3, [pc, #16] ; (8001210 ) + 80011fe: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 8001202: 609a str r2, [r3, #8] +#endif +} + 8001204: bf00 nop + 8001206: bd80 pop {r7, pc} + 8001208: 40021000 .word 0x40021000 + 800120c: f8ff0000 .word 0xf8ff0000 + 8001210: e000ed00 .word 0xe000ed00 + +08001214 : + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + 8001214: b580 push {r7, lr} + 8001216: af00 add r7, sp, #0 +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); + 8001218: f000 f802 bl 8001220 +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + 800121c: bf00 nop + 800121e: bd80 pop {r7, pc} + +08001220 : + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + 8001220: b480 push {r7} + 8001222: b083 sub sp, #12 + 8001224: af00 add r7, sp, #0 + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + 8001226: 2300 movs r3, #0 + 8001228: 607b str r3, [r7, #4] + 800122a: 2300 movs r3, #0 + 800122c: 603b str r3, [r7, #0] + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + 800122e: 4b3a ldr r3, [pc, #232] ; (8001318 ) + 8001230: 681b ldr r3, [r3, #0] + 8001232: 4a39 ldr r2, [pc, #228] ; (8001318 ) + 8001234: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8001238: 6013 str r3, [r2, #0] + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + 800123a: 4b37 ldr r3, [pc, #220] ; (8001318 ) + 800123c: 681b ldr r3, [r3, #0] + 800123e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001242: 603b str r3, [r7, #0] + StartUpCounter++; + 8001244: 687b ldr r3, [r7, #4] + 8001246: 3301 adds r3, #1 + 8001248: 607b str r3, [r7, #4] + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + 800124a: 683b ldr r3, [r7, #0] + 800124c: 2b00 cmp r3, #0 + 800124e: d103 bne.n 8001258 + 8001250: 687b ldr r3, [r7, #4] + 8001252: f5b3 6fa0 cmp.w r3, #1280 ; 0x500 + 8001256: d1f0 bne.n 800123a + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + 8001258: 4b2f ldr r3, [pc, #188] ; (8001318 ) + 800125a: 681b ldr r3, [r3, #0] + 800125c: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001260: 2b00 cmp r3, #0 + 8001262: d002 beq.n 800126a + { + HSEStatus = (uint32_t)0x01; + 8001264: 2301 movs r3, #1 + 8001266: 603b str r3, [r7, #0] + 8001268: e001 b.n 800126e + } + else + { + HSEStatus = (uint32_t)0x00; + 800126a: 2300 movs r3, #0 + 800126c: 603b str r3, [r7, #0] + } + + if (HSEStatus == (uint32_t)0x01) + 800126e: 683b ldr r3, [r7, #0] + 8001270: 2b01 cmp r3, #1 + 8001272: d14b bne.n 800130c + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + 8001274: 4b29 ldr r3, [pc, #164] ; (800131c ) + 8001276: 681b ldr r3, [r3, #0] + 8001278: 4a28 ldr r2, [pc, #160] ; (800131c ) + 800127a: f043 0310 orr.w r3, r3, #16 + 800127e: 6013 str r3, [r2, #0] + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + 8001280: 4b26 ldr r3, [pc, #152] ; (800131c ) + 8001282: 681b ldr r3, [r3, #0] + 8001284: 4a25 ldr r2, [pc, #148] ; (800131c ) + 8001286: f023 0303 bic.w r3, r3, #3 + 800128a: 6013 str r3, [r2, #0] + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + 800128c: 4b23 ldr r3, [pc, #140] ; (800131c ) + 800128e: 681b ldr r3, [r3, #0] + 8001290: 4a22 ldr r2, [pc, #136] ; (800131c ) + 8001292: f043 0302 orr.w r3, r3, #2 + 8001296: 6013 str r3, [r2, #0] + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + 8001298: 4b1f ldr r3, [pc, #124] ; (8001318 ) + 800129a: 4a1f ldr r2, [pc, #124] ; (8001318 ) + 800129c: 685b ldr r3, [r3, #4] + 800129e: 6053 str r3, [r2, #4] + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + 80012a0: 4b1d ldr r3, [pc, #116] ; (8001318 ) + 80012a2: 4a1d ldr r2, [pc, #116] ; (8001318 ) + 80012a4: 685b ldr r3, [r3, #4] + 80012a6: 6053 str r3, [r2, #4] + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + 80012a8: 4b1b ldr r3, [pc, #108] ; (8001318 ) + 80012aa: 685b ldr r3, [r3, #4] + 80012ac: 4a1a ldr r2, [pc, #104] ; (8001318 ) + 80012ae: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 80012b2: 6053 str r3, [r2, #4] + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + 80012b4: 4b18 ldr r3, [pc, #96] ; (8001318 ) + 80012b6: 685b ldr r3, [r3, #4] + 80012b8: 4a17 ldr r2, [pc, #92] ; (8001318 ) + 80012ba: f423 137c bic.w r3, r3, #4128768 ; 0x3f0000 + 80012be: 6053 str r3, [r2, #4] + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); + 80012c0: 4b15 ldr r3, [pc, #84] ; (8001318 ) + 80012c2: 685b ldr r3, [r3, #4] + 80012c4: 4a14 ldr r2, [pc, #80] ; (8001318 ) + 80012c6: f443 13e8 orr.w r3, r3, #1900544 ; 0x1d0000 + 80012ca: 6053 str r3, [r2, #4] +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + 80012cc: 4b12 ldr r3, [pc, #72] ; (8001318 ) + 80012ce: 681b ldr r3, [r3, #0] + 80012d0: 4a11 ldr r2, [pc, #68] ; (8001318 ) + 80012d2: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 80012d6: 6013 str r3, [r2, #0] + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + 80012d8: bf00 nop + 80012da: 4b0f ldr r3, [pc, #60] ; (8001318 ) + 80012dc: 681b ldr r3, [r3, #0] + 80012de: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80012e2: 2b00 cmp r3, #0 + 80012e4: d0f9 beq.n 80012da + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + 80012e6: 4b0c ldr r3, [pc, #48] ; (8001318 ) + 80012e8: 685b ldr r3, [r3, #4] + 80012ea: 4a0b ldr r2, [pc, #44] ; (8001318 ) + 80012ec: f023 0303 bic.w r3, r3, #3 + 80012f0: 6053 str r3, [r2, #4] + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + 80012f2: 4b09 ldr r3, [pc, #36] ; (8001318 ) + 80012f4: 685b ldr r3, [r3, #4] + 80012f6: 4a08 ldr r2, [pc, #32] ; (8001318 ) + 80012f8: f043 0302 orr.w r3, r3, #2 + 80012fc: 6053 str r3, [r2, #4] + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + 80012fe: bf00 nop + 8001300: 4b05 ldr r3, [pc, #20] ; (8001318 ) + 8001302: 685b ldr r3, [r3, #4] + 8001304: f003 030c and.w r3, r3, #12 + 8001308: 2b08 cmp r3, #8 + 800130a: d1f9 bne.n 8001300 + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + 800130c: bf00 nop + 800130e: 370c adds r7, #12 + 8001310: 46bd mov sp, r7 + 8001312: bc80 pop {r7} + 8001314: 4770 bx lr + 8001316: bf00 nop + 8001318: 40021000 .word 0x40021000 + 800131c: 40022000 .word 0x40022000 + +08001320 : + + + +//ADC Init +void adc_init(void) +{ + 8001320: b580 push {r7, lr} + 8001322: af00 add r7, sp, #0 + //ADC prescaller + RCC->CFGR &= ~RCC_CFGR_ADCPRE; //div by 8 + 8001324: 4b20 ldr r3, [pc, #128] ; (80013a8 ) + 8001326: 685b ldr r3, [r3, #4] + 8001328: 4a1f ldr r2, [pc, #124] ; (80013a8 ) + 800132a: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 800132e: 6053 str r3, [r2, #4] + + //ADC clock on + RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; + 8001330: 4b1d ldr r3, [pc, #116] ; (80013a8 ) + 8001332: 699b ldr r3, [r3, #24] + 8001334: 4a1c ldr r2, [pc, #112] ; (80013a8 ) + 8001336: f443 7300 orr.w r3, r3, #512 ; 0x200 + 800133a: 6193 str r3, [r2, #24] + + //Sample time + ADC1->SMPR2 |= ADC_SMPR2_SMP0_1; //13.5 cycles + 800133c: 4b1b ldr r3, [pc, #108] ; (80013ac ) + 800133e: 691b ldr r3, [r3, #16] + 8001340: 4a1a ldr r2, [pc, #104] ; (80013ac ) + 8001342: f043 0302 orr.w r3, r3, #2 + 8001346: 6113 str r3, [r2, #16] + + //Number of conversions in regular sequence + ADC1->SQR1 &= ~ADC_SQR1_L; //1 conversion + 8001348: 4b18 ldr r3, [pc, #96] ; (80013ac ) + 800134a: 6adb ldr r3, [r3, #44] ; 0x2c + 800134c: 4a17 ldr r2, [pc, #92] ; (80013ac ) + 800134e: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 + 8001352: 62d3 str r3, [r2, #44] ; 0x2c + + //First channel in regular sequence + ADC1->SQR3 &= ~ADC_SQR3_SQ1; //channel #0 + 8001354: 4b15 ldr r3, [pc, #84] ; (80013ac ) + 8001356: 6b5b ldr r3, [r3, #52] ; 0x34 + 8001358: 4a14 ldr r2, [pc, #80] ; (80013ac ) + 800135a: f023 031f bic.w r3, r3, #31 + 800135e: 6353 str r3, [r2, #52] ; 0x34 + + //Extermal trigger enable for regular sequence + ADC1->CR2 |= ADC_CR2_EXTTRIG; + 8001360: 4b12 ldr r3, [pc, #72] ; (80013ac ) + 8001362: 689b ldr r3, [r3, #8] + 8001364: 4a11 ldr r2, [pc, #68] ; (80013ac ) + 8001366: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 800136a: 6093 str r3, [r2, #8] + + //Event to start regular sequence + ADC1->CR2 |= ADC_CR2_EXTSEL; //start by software + 800136c: 4b0f ldr r3, [pc, #60] ; (80013ac ) + 800136e: 689b ldr r3, [r3, #8] + 8001370: 4a0e ldr r2, [pc, #56] ; (80013ac ) + 8001372: f443 2360 orr.w r3, r3, #917504 ; 0xe0000 + 8001376: 6093 str r3, [r2, #8] + + //ADC enable + ADC1->CR2 |= ADC_CR2_ADON; + 8001378: 4b0c ldr r3, [pc, #48] ; (80013ac ) + 800137a: 689b ldr r3, [r3, #8] + 800137c: 4a0b ldr r2, [pc, #44] ; (80013ac ) + 800137e: f043 0301 orr.w r3, r3, #1 + 8001382: 6093 str r3, [r2, #8] + + //Calibration + delay_cyc(100000); + 8001384: 480a ldr r0, [pc, #40] ; (80013b0 ) + 8001386: f007 f84f bl 8008428 + ADC1->CR2 |= ADC_CR2_CAL; //start cal + 800138a: 4b08 ldr r3, [pc, #32] ; (80013ac ) + 800138c: 689b ldr r3, [r3, #8] + 800138e: 4a07 ldr r2, [pc, #28] ; (80013ac ) + 8001390: f043 0304 orr.w r3, r3, #4 + 8001394: 6093 str r3, [r2, #8] + while (ADC1->CR2 & ADC_CR2_CAL); //wait + 8001396: bf00 nop + 8001398: 4b04 ldr r3, [pc, #16] ; (80013ac ) + 800139a: 689b ldr r3, [r3, #8] + 800139c: f003 0304 and.w r3, r3, #4 + 80013a0: 2b00 cmp r3, #0 + 80013a2: d1f9 bne.n 8001398 +} + 80013a4: bf00 nop + 80013a6: bd80 pop {r7, pc} + 80013a8: 40021000 .word 0x40021000 + 80013ac: 40012400 .word 0x40012400 + 80013b0: 000186a0 .word 0x000186a0 + 80013b4: 00000000 .word 0x00000000 + +080013b8 : + + + +//Get battery voltage +uint8_t adc_get_bat_voltage(void) +{ + 80013b8: b580 push {r7, lr} + 80013ba: af00 add r7, sp, #0 + bat_interval_counter++; + 80013bc: 4b4e ldr r3, [pc, #312] ; (80014f8 ) + 80013be: 781b ldrb r3, [r3, #0] + 80013c0: 3301 adds r3, #1 + 80013c2: b2da uxtb r2, r3 + 80013c4: 4b4c ldr r3, [pc, #304] ; (80014f8 ) + 80013c6: 701a strb r2, [r3, #0] + + if (bat_interval_counter >= GET_BAT_VOLTAGE_INTERVAL) + 80013c8: 4b4b ldr r3, [pc, #300] ; (80014f8 ) + 80013ca: 781b ldrb r3, [r3, #0] + 80013cc: 2b09 cmp r3, #9 + 80013ce: d97e bls.n 80014ce + { + bat_interval_counter = 0; + 80013d0: 4b49 ldr r3, [pc, #292] ; (80014f8 ) + 80013d2: 2200 movs r2, #0 + 80013d4: 701a strb r2, [r3, #0] + + bat_mon_on(); //Enable resistive divider and wait a bit + 80013d6: f000 fca9 bl 8001d2c + delay_cyc(100); + 80013da: 2064 movs r0, #100 ; 0x64 + 80013dc: f007 f824 bl 8008428 + + //Start conversation + ADC1->CR2 |= ADC_CR2_SWSTART; + 80013e0: 4b46 ldr r3, [pc, #280] ; (80014fc ) + 80013e2: 689b ldr r3, [r3, #8] + 80013e4: 4a45 ldr r2, [pc, #276] ; (80014fc ) + 80013e6: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 + 80013ea: 6093 str r3, [r2, #8] + + //Wait for conversation end + while (!(ADC1->SR & ADC_SR_EOC)); + 80013ec: bf00 nop + 80013ee: 4b43 ldr r3, [pc, #268] ; (80014fc ) + 80013f0: 681b ldr r3, [r3, #0] + 80013f2: f003 0302 and.w r3, r3, #2 + 80013f6: 2b00 cmp r3, #0 + 80013f8: d0f9 beq.n 80013ee + + bat_mon_off(); //Disable resistive divider + 80013fa: f000 fca3 bl 8001d44 + + //Convert + bat_voltage = 2 * ((ADC1->DR * vref) / 4096); //x2 due to resistive voltage divider before ADC input + 80013fe: 4b3f ldr r3, [pc, #252] ; (80014fc ) + 8001400: 6cdb ldr r3, [r3, #76] ; 0x4c + 8001402: 4618 mov r0, r3 + 8001404: f7ff fc6e bl 8000ce4 <__aeabi_ui2f> + 8001408: 4602 mov r2, r0 + 800140a: 4b3d ldr r3, [pc, #244] ; (8001500 ) + 800140c: 4619 mov r1, r3 + 800140e: 4610 mov r0, r2 + 8001410: f7ff fcc0 bl 8000d94 <__aeabi_fmul> + 8001414: 4603 mov r3, r0 + 8001416: f04f 418b mov.w r1, #1166016512 ; 0x45800000 + 800141a: 4618 mov r0, r3 + 800141c: f7ff fd6e bl 8000efc <__aeabi_fdiv> + 8001420: 4603 mov r3, r0 + 8001422: 4619 mov r1, r3 + 8001424: 4618 mov r0, r3 + 8001426: f7ff fbad bl 8000b84 <__addsf3> + 800142a: 4603 mov r3, r0 + 800142c: 461a mov r2, r3 + 800142e: 4b35 ldr r3, [pc, #212] ; (8001504 ) + 8001430: 601a str r2, [r3, #0] + + //Refresh flags + if (bat_voltage > V_BATTERY_75_TO_100) + 8001432: 4b34 ldr r3, [pc, #208] ; (8001504 ) + 8001434: 681b ldr r3, [r3, #0] + 8001436: 4618 mov r0, r3 + 8001438: f7fe fffe bl 8000438 <__aeabi_f2d> + 800143c: a326 add r3, pc, #152 ; (adr r3, 80014d8 ) + 800143e: e9d3 2300 ldrd r2, r3, [r3] + 8001442: f7ff fae1 bl 8000a08 <__aeabi_dcmpgt> + 8001446: 4603 mov r3, r0 + 8001448: 2b00 cmp r3, #0 + 800144a: d004 beq.n 8001456 + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_75_TO_100); + 800144c: 2104 movs r1, #4 + 800144e: 2001 movs r0, #1 + 8001450: f001 f9b6 bl 80027c0 + 8001454: e03b b.n 80014ce + } + else if (bat_voltage > V_BATTERY_50_TO_75) + 8001456: 4b2b ldr r3, [pc, #172] ; (8001504 ) + 8001458: 681b ldr r3, [r3, #0] + 800145a: 4618 mov r0, r3 + 800145c: f7fe ffec bl 8000438 <__aeabi_f2d> + 8001460: a31f add r3, pc, #124 ; (adr r3, 80014e0 ) + 8001462: e9d3 2300 ldrd r2, r3, [r3] + 8001466: f7ff facf bl 8000a08 <__aeabi_dcmpgt> + 800146a: 4603 mov r3, r0 + 800146c: 2b00 cmp r3, #0 + 800146e: d004 beq.n 800147a + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_50_TO_75); + 8001470: 2103 movs r1, #3 + 8001472: 2001 movs r0, #1 + 8001474: f001 f9a4 bl 80027c0 + 8001478: e029 b.n 80014ce + } + else if (bat_voltage > V_BATTERY_25_TO_50) + 800147a: 4b22 ldr r3, [pc, #136] ; (8001504 ) + 800147c: 681b ldr r3, [r3, #0] + 800147e: 4618 mov r0, r3 + 8001480: f7fe ffda bl 8000438 <__aeabi_f2d> + 8001484: a318 add r3, pc, #96 ; (adr r3, 80014e8 ) + 8001486: e9d3 2300 ldrd r2, r3, [r3] + 800148a: f7ff fabd bl 8000a08 <__aeabi_dcmpgt> + 800148e: 4603 mov r3, r0 + 8001490: 2b00 cmp r3, #0 + 8001492: d004 beq.n 800149e + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_25_TO_50); + 8001494: 2102 movs r1, #2 + 8001496: 2001 movs r0, #1 + 8001498: f001 f992 bl 80027c0 + 800149c: e017 b.n 80014ce + } + else if (bat_voltage > V_BATTERY_10_TO_25) + 800149e: 4b19 ldr r3, [pc, #100] ; (8001504 ) + 80014a0: 681b ldr r3, [r3, #0] + 80014a2: 4618 mov r0, r3 + 80014a4: f7fe ffc8 bl 8000438 <__aeabi_f2d> + 80014a8: a311 add r3, pc, #68 ; (adr r3, 80014f0 ) + 80014aa: e9d3 2300 ldrd r2, r3, [r3] + 80014ae: f7ff faab bl 8000a08 <__aeabi_dcmpgt> + 80014b2: 4603 mov r3, r0 + 80014b4: 2b00 cmp r3, #0 + 80014b6: d004 beq.n 80014c2 + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_10_TO_25); + 80014b8: 2101 movs r1, #1 + 80014ba: 2001 movs r0, #1 + 80014bc: f001 f980 bl 80027c0 + 80014c0: e005 b.n 80014ce + } + else + { + set_device_flags(FLAGS_BATTERY, FLAG_BATTERY_0_TO_10); + 80014c2: 2100 movs r1, #0 + 80014c4: 2001 movs r0, #1 + 80014c6: f001 f97b bl 80027c0 + return 1; + 80014ca: 2301 movs r3, #1 + 80014cc: e000 b.n 80014d0 + } + } + + return 0; + 80014ce: 2300 movs r3, #0 +} + 80014d0: 4618 mov r0, r3 + 80014d2: bd80 pop {r7, pc} + 80014d4: f3af 8000 nop.w + 80014d8: 33333333 .word 0x33333333 + 80014dc: 400f3333 .word 0x400f3333 + 80014e0: cccccccd .word 0xcccccccd + 80014e4: 400ccccc .word 0x400ccccc + 80014e8: 66666666 .word 0x66666666 + 80014ec: 400a6666 .word 0x400a6666 + 80014f0: cccccccd .word 0xcccccccd + 80014f4: 4008cccc .word 0x4008cccc + 80014f8: 200000e4 .word 0x200000e4 + 80014fc: 40012400 .word 0x40012400 + 8001500: 40533333 .word 0x40533333 + 8001504: 20000128 .word 0x20000128 + +08001508 : + + + +float get_bat_voltage(void) +{ + 8001508: b480 push {r7} + 800150a: af00 add r7, sp, #0 + return bat_voltage; + 800150c: 4b02 ldr r3, [pc, #8] ; (8001518 ) + 800150e: 681b ldr r3, [r3, #0] +} + 8001510: 4618 mov r0, r3 + 8001512: 46bd mov sp, r7 + 8001514: bc80 pop {r7} + 8001516: 4770 bx lr + 8001518: 20000128 .word 0x20000128 + +0800151c : + + + +//button return code = {ButtonNumber(0...BUTTONS_NUM-1) * BUTTON_ACTIONS_NUM + BUTTON_ACTION(_SHORT)(_LONG)} + 1 +uint8_t scan_buttons(void) +{ + 800151c: b480 push {r7} + 800151e: b083 sub sp, #12 + 8001520: af00 add r7, sp, #0 + if (scan_interval_counter < SCAN_INTERVAL) + 8001522: 4b6b ldr r3, [pc, #428] ; (80016d0 ) + 8001524: 681b ldr r3, [r3, #0] + 8001526: f240 52db movw r2, #1499 ; 0x5db + 800152a: 4293 cmp r3, r2 + 800152c: d805 bhi.n 800153a + { + scan_interval_counter++; //increase counter + 800152e: 4b68 ldr r3, [pc, #416] ; (80016d0 ) + 8001530: 681b ldr r3, [r3, #0] + 8001532: 3301 adds r3, #1 + 8001534: 4a66 ldr r2, [pc, #408] ; (80016d0 ) + 8001536: 6013 str r3, [r2, #0] + 8001538: e0c3 b.n 80016c2 + } + else + { + scan_interval_counter = 0; //time to scan buttons! reset counter + 800153a: 4b65 ldr r3, [pc, #404] ; (80016d0 ) + 800153c: 2200 movs r2, #0 + 800153e: 601a str r2, [r3, #0] + + idr_register_copy = GPIOA->IDR; //save pins data + 8001540: 4b64 ldr r3, [pc, #400] ; (80016d4 ) + 8001542: 689b ldr r3, [r3, #8] + 8001544: 4a64 ldr r2, [pc, #400] ; (80016d8 ) + 8001546: 6013 str r3, [r2, #0] + idr_register_copy &= (GPIO_IDR_IDR1 | //mask needed pins + 8001548: 4b63 ldr r3, [pc, #396] ; (80016d8 ) + 800154a: 681b ldr r3, [r3, #0] + 800154c: f003 033e and.w r3, r3, #62 ; 0x3e + 8001550: 4a61 ldr r2, [pc, #388] ; (80016d8 ) + 8001552: 6013 str r3, [r2, #0] + GPIO_IDR_IDR2 | + GPIO_IDR_IDR3 | + GPIO_IDR_IDR4 | + GPIO_IDR_IDR5); + + idr_register_copy >>= 1; //align bits to the left, now IDR1(PA1) is in LSBit position + 8001554: 4b60 ldr r3, [pc, #384] ; (80016d8 ) + 8001556: 681b ldr r3, [r3, #0] + 8001558: 085b lsrs r3, r3, #1 + 800155a: 4a5f ldr r2, [pc, #380] ; (80016d8 ) + 800155c: 6013 str r3, [r2, #0] + + for (uint8_t i = 0; i < BUTTONS_NUM; i++) //update buttons weight (digital capacitor, increase or decrease "charge") + 800155e: 2300 movs r3, #0 + 8001560: 71fb strb r3, [r7, #7] + 8001562: e026 b.n 80015b2 + { + if (idr_register_copy & ((uint32_t)1 << i)) //check pin state + 8001564: 4b5c ldr r3, [pc, #368] ; (80016d8 ) + 8001566: 681a ldr r2, [r3, #0] + 8001568: 79fb ldrb r3, [r7, #7] + 800156a: fa22 f303 lsr.w r3, r2, r3 + 800156e: f003 0301 and.w r3, r3, #1 + 8001572: 2b00 cmp r3, #0 + 8001574: d00d beq.n 8001592 + { + if (button_weight[i] < BUTTON_WEIGHT_MAX) + 8001576: 79fb ldrb r3, [r7, #7] + 8001578: 4a58 ldr r2, [pc, #352] ; (80016dc ) + 800157a: 5cd3 ldrb r3, [r2, r3] + 800157c: 2b0f cmp r3, #15 + 800157e: d815 bhi.n 80015ac + { + button_weight[i] += 1; // if input pin = 1, increase weight + 8001580: 79fb ldrb r3, [r7, #7] + 8001582: 4a56 ldr r2, [pc, #344] ; (80016dc ) + 8001584: 5cd2 ldrb r2, [r2, r3] + 8001586: 79fb ldrb r3, [r7, #7] + 8001588: 3201 adds r2, #1 + 800158a: b2d1 uxtb r1, r2 + 800158c: 4a53 ldr r2, [pc, #332] ; (80016dc ) + 800158e: 54d1 strb r1, [r2, r3] + 8001590: e00c b.n 80015ac + } + } + else + { + if (button_weight[i] > BUTTON_WEIGHT_MIN) + 8001592: 79fb ldrb r3, [r7, #7] + 8001594: 4a51 ldr r2, [pc, #324] ; (80016dc ) + 8001596: 5cd3 ldrb r3, [r2, r3] + 8001598: 2b00 cmp r3, #0 + 800159a: d007 beq.n 80015ac + { + button_weight[i] -= 1; // if input pin = 0, decrease weight + 800159c: 79fb ldrb r3, [r7, #7] + 800159e: 4a4f ldr r2, [pc, #316] ; (80016dc ) + 80015a0: 5cd2 ldrb r2, [r2, r3] + 80015a2: 79fb ldrb r3, [r7, #7] + 80015a4: 3a01 subs r2, #1 + 80015a6: b2d1 uxtb r1, r2 + 80015a8: 4a4c ldr r2, [pc, #304] ; (80016dc ) + 80015aa: 54d1 strb r1, [r2, r3] + for (uint8_t i = 0; i < BUTTONS_NUM; i++) //update buttons weight (digital capacitor, increase or decrease "charge") + 80015ac: 79fb ldrb r3, [r7, #7] + 80015ae: 3301 adds r3, #1 + 80015b0: 71fb strb r3, [r7, #7] + 80015b2: 79fb ldrb r3, [r7, #7] + 80015b4: 2b04 cmp r3, #4 + 80015b6: d9d5 bls.n 8001564 + } + } + } + + for (uint8_t i = 0; i < BUTTONS_NUM; i++) //make a desicion "button is pressed or not?" (with hysteresis) + 80015b8: 2300 movs r3, #0 + 80015ba: 71bb strb r3, [r7, #6] + 80015bc: e021 b.n 8001602 + { + if (button_weight[i] > BUTTON_THRESHOLD_HI) + 80015be: 79bb ldrb r3, [r7, #6] + 80015c0: 4a46 ldr r2, [pc, #280] ; (80016dc ) + 80015c2: 5cd3 ldrb r3, [r2, r3] + 80015c4: 2b0c cmp r3, #12 + 80015c6: d90a bls.n 80015de + { + button_prev_state[i] = button_state[i]; + 80015c8: 79ba ldrb r2, [r7, #6] + 80015ca: 79bb ldrb r3, [r7, #6] + 80015cc: 4944 ldr r1, [pc, #272] ; (80016e0 ) + 80015ce: 5c89 ldrb r1, [r1, r2] + 80015d0: 4a44 ldr r2, [pc, #272] ; (80016e4 ) + 80015d2: 54d1 strb r1, [r2, r3] + button_state[i] = BUTTON_RELEASED; + 80015d4: 79bb ldrb r3, [r7, #6] + 80015d6: 4a42 ldr r2, [pc, #264] ; (80016e0 ) + 80015d8: 2101 movs r1, #1 + 80015da: 54d1 strb r1, [r2, r3] + 80015dc: e00e b.n 80015fc + } + else if (button_weight[i] < BUTTON_THRESHOLD_LO) + 80015de: 79bb ldrb r3, [r7, #6] + 80015e0: 4a3e ldr r2, [pc, #248] ; (80016dc ) + 80015e2: 5cd3 ldrb r3, [r2, r3] + 80015e4: 2b03 cmp r3, #3 + 80015e6: d809 bhi.n 80015fc + { + button_prev_state[i] = button_state[i]; + 80015e8: 79ba ldrb r2, [r7, #6] + 80015ea: 79bb ldrb r3, [r7, #6] + 80015ec: 493c ldr r1, [pc, #240] ; (80016e0 ) + 80015ee: 5c89 ldrb r1, [r1, r2] + 80015f0: 4a3c ldr r2, [pc, #240] ; (80016e4 ) + 80015f2: 54d1 strb r1, [r2, r3] + button_state[i] = BUTTON_PRESSED; + 80015f4: 79bb ldrb r3, [r7, #6] + 80015f6: 4a3a ldr r2, [pc, #232] ; (80016e0 ) + 80015f8: 2100 movs r1, #0 + 80015fa: 54d1 strb r1, [r2, r3] + for (uint8_t i = 0; i < BUTTONS_NUM; i++) //make a desicion "button is pressed or not?" (with hysteresis) + 80015fc: 79bb ldrb r3, [r7, #6] + 80015fe: 3301 adds r3, #1 + 8001600: 71bb strb r3, [r7, #6] + 8001602: 79bb ldrb r3, [r7, #6] + 8001604: 2b04 cmp r3, #4 + 8001606: d9da bls.n 80015be + } + } + + for (uint8_t i = 0; i < BUTTONS_NUM; i++) //check click duration. short click after button released (and before timeout overflow); long click after timeout overflow + 8001608: 2300 movs r3, #0 + 800160a: 717b strb r3, [r7, #5] + 800160c: e056 b.n 80016bc + { + if ((button_state[i] == BUTTON_PRESSED) && (button_pressed_counter[i] < BUTTON_PRESSED_COUNTER_MAX)) //increase timeout counter, update overflow states + 800160e: 797b ldrb r3, [r7, #5] + 8001610: 4a33 ldr r2, [pc, #204] ; (80016e0 ) + 8001612: 5cd3 ldrb r3, [r2, r3] + 8001614: 2b00 cmp r3, #0 + 8001616: d124 bne.n 8001662 + 8001618: 797b ldrb r3, [r7, #5] + 800161a: 4a33 ldr r2, [pc, #204] ; (80016e8 ) + 800161c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8001620: f64f 72ff movw r2, #65535 ; 0xffff + 8001624: 4293 cmp r3, r2 + 8001626: d01c beq.n 8001662 + { + button_pressed_counter[i]++; + 8001628: 797b ldrb r3, [r7, #5] + 800162a: 4a2f ldr r2, [pc, #188] ; (80016e8 ) + 800162c: f832 2013 ldrh.w r2, [r2, r3, lsl #1] + 8001630: 3201 adds r2, #1 + 8001632: b291 uxth r1, r2 + 8001634: 4a2c ldr r2, [pc, #176] ; (80016e8 ) + 8001636: f822 1013 strh.w r1, [r2, r3, lsl #1] + + timeout_prev_state[i] = timeout_state[i]; + 800163a: 797a ldrb r2, [r7, #5] + 800163c: 797b ldrb r3, [r7, #5] + 800163e: 492b ldr r1, [pc, #172] ; (80016ec ) + 8001640: 5c89 ldrb r1, [r1, r2] + 8001642: 4a2b ldr r2, [pc, #172] ; (80016f0 ) + 8001644: 54d1 strb r1, [r2, r3] + timeout_state[i] = (button_pressed_counter[i] > BUTTON_PRESSED_COUNTER_THRESHOLD); //overflow or not? 1 or 0? + 8001646: 797b ldrb r3, [r7, #5] + 8001648: 4a27 ldr r2, [pc, #156] ; (80016e8 ) + 800164a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 800164e: f5b3 7faf cmp.w r3, #350 ; 0x15e + 8001652: bf8c ite hi + 8001654: 2301 movhi r3, #1 + 8001656: 2300 movls r3, #0 + 8001658: b2da uxtb r2, r3 + 800165a: 797b ldrb r3, [r7, #5] + 800165c: 4611 mov r1, r2 + 800165e: 4a23 ldr r2, [pc, #140] ; (80016ec ) + 8001660: 54d1 strb r1, [r2, r3] + } + + if ((button_state[i] == BUTTON_RELEASED) && (button_prev_state[i] == BUTTON_PRESSED)) //button has been released + 8001662: 797b ldrb r3, [r7, #5] + 8001664: 4a1e ldr r2, [pc, #120] ; (80016e0 ) + 8001666: 5cd3 ldrb r3, [r2, r3] + 8001668: 2b01 cmp r3, #1 + 800166a: d114 bne.n 8001696 + 800166c: 797b ldrb r3, [r7, #5] + 800166e: 4a1d ldr r2, [pc, #116] ; (80016e4 ) + 8001670: 5cd3 ldrb r3, [r2, r3] + 8001672: 2b00 cmp r3, #0 + 8001674: d10f bne.n 8001696 + { + button_pressed_counter[i] = 0; + 8001676: 797b ldrb r3, [r7, #5] + 8001678: 4a1b ldr r2, [pc, #108] ; (80016e8 ) + 800167a: 2100 movs r1, #0 + 800167c: f822 1013 strh.w r1, [r2, r3, lsl #1] + + if (timeout_state[i] == TIMEOUT_NO_OVERFLOW) + 8001680: 797b ldrb r3, [r7, #5] + 8001682: 4a1a ldr r2, [pc, #104] ; (80016ec ) + 8001684: 5cd3 ldrb r3, [r2, r3] + 8001686: 2b00 cmp r3, #0 + 8001688: d105 bne.n 8001696 + { + return (i * BUTTON_ACTIONS_NUM + BUTTON_ACTION_SHORT) + 1; //if before overflow, then short click + 800168a: 797b ldrb r3, [r7, #5] + 800168c: 005b lsls r3, r3, #1 + 800168e: b2db uxtb r3, r3 + 8001690: 3301 adds r3, #1 + 8001692: b2db uxtb r3, r3 + 8001694: e016 b.n 80016c4 + } + } + + if ((timeout_state[i] == TIMEOUT_OVERFLOW) && (timeout_prev_state[i] == TIMEOUT_NO_OVERFLOW)) //overflow occured + 8001696: 797b ldrb r3, [r7, #5] + 8001698: 4a14 ldr r2, [pc, #80] ; (80016ec ) + 800169a: 5cd3 ldrb r3, [r2, r3] + 800169c: 2b01 cmp r3, #1 + 800169e: d10a bne.n 80016b6 + 80016a0: 797b ldrb r3, [r7, #5] + 80016a2: 4a13 ldr r2, [pc, #76] ; (80016f0 ) + 80016a4: 5cd3 ldrb r3, [r2, r3] + 80016a6: 2b00 cmp r3, #0 + 80016a8: d105 bne.n 80016b6 + { + return (i * BUTTON_ACTIONS_NUM + BUTTON_ACTION_LONG) + 1; //long click + 80016aa: 797b ldrb r3, [r7, #5] + 80016ac: 3301 adds r3, #1 + 80016ae: b2db uxtb r3, r3 + 80016b0: 005b lsls r3, r3, #1 + 80016b2: b2db uxtb r3, r3 + 80016b4: e006 b.n 80016c4 + for (uint8_t i = 0; i < BUTTONS_NUM; i++) //check click duration. short click after button released (and before timeout overflow); long click after timeout overflow + 80016b6: 797b ldrb r3, [r7, #5] + 80016b8: 3301 adds r3, #1 + 80016ba: 717b strb r3, [r7, #5] + 80016bc: 797b ldrb r3, [r7, #5] + 80016be: 2b04 cmp r3, #4 + 80016c0: d9a5 bls.n 800160e + } + } + } + return BTN_NO_ACTION; + 80016c2: 2300 movs r3, #0 +} + 80016c4: 4618 mov r0, r3 + 80016c6: 370c adds r7, #12 + 80016c8: 46bd mov sp, r7 + 80016ca: bc80 pop {r7} + 80016cc: 4770 bx lr + 80016ce: bf00 nop + 80016d0: 200000e8 .word 0x200000e8 + 80016d4: 40010800 .word 0x40010800 + 80016d8: 200000ec .word 0x200000ec + 80016dc: 20000000 .word 0x20000000 + 80016e0: 20000008 .word 0x20000008 + 80016e4: 20000010 .word 0x20000010 + 80016e8: 200000f0 .word 0x200000f0 + 80016ec: 200000fc .word 0x200000fc + 80016f0: 20000104 .word 0x20000104 + +080016f4 : + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80016f4: b480 push {r7} + 80016f6: b083 sub sp, #12 + 80016f8: af00 add r7, sp, #0 + 80016fa: 4603 mov r3, r0 + 80016fc: 71fb strb r3, [r7, #7] + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ + 80016fe: 79fb ldrb r3, [r7, #7] + 8001700: f003 031f and.w r3, r3, #31 + 8001704: 2201 movs r2, #1 + 8001706: fa02 f103 lsl.w r1, r2, r3 + 800170a: 4a05 ldr r2, [pc, #20] ; (8001720 ) + 800170c: f997 3007 ldrsb.w r3, [r7, #7] + 8001710: 095b lsrs r3, r3, #5 + 8001712: f842 1023 str.w r1, [r2, r3, lsl #2] +} + 8001716: bf00 nop + 8001718: 370c adds r7, #12 + 800171a: 46bd mov sp, r7 + 800171c: bc80 pop {r7} + 800171e: 4770 bx lr + 8001720: e000e100 .word 0xe000e100 + +08001724 : + + + +//Initialization of all used ports +void gpio_init(void) +{ + 8001724: b580 push {r7, lr} + 8001726: af00 add r7, sp, #0 + //Port A + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; + 8001728: 4b98 ldr r3, [pc, #608] ; (800198c ) + 800172a: 699b ldr r3, [r3, #24] + 800172c: 4a97 ldr r2, [pc, #604] ; (800198c ) + 800172e: f043 0304 orr.w r3, r3, #4 + 8001732: 6193 str r3, [r2, #24] + + //PA0 - ADC0 (Battery voltage) + GPIOA->CRL &= ~GPIO_CRL_MODE0; //input mode + 8001734: 4b96 ldr r3, [pc, #600] ; (8001990 ) + 8001736: 681b ldr r3, [r3, #0] + 8001738: 4a95 ldr r2, [pc, #596] ; (8001990 ) + 800173a: f023 0303 bic.w r3, r3, #3 + 800173e: 6013 str r3, [r2, #0] + GPIOA->CRL &= ~GPIO_CRL_CNF0; //analog input + 8001740: 4b93 ldr r3, [pc, #588] ; (8001990 ) + 8001742: 681b ldr r3, [r3, #0] + 8001744: 4a92 ldr r2, [pc, #584] ; (8001990 ) + 8001746: f023 030c bic.w r3, r3, #12 + 800174a: 6013 str r3, [r2, #0] + + //PA1 - Button 1 + GPIOA->CRL &= ~GPIO_CRL_MODE1; //input mode + 800174c: 4b90 ldr r3, [pc, #576] ; (8001990 ) + 800174e: 681b ldr r3, [r3, #0] + 8001750: 4a8f ldr r2, [pc, #572] ; (8001990 ) + 8001752: f023 0330 bic.w r3, r3, #48 ; 0x30 + 8001756: 6013 str r3, [r2, #0] + GPIOA->CRL &= ~GPIO_CRL_CNF1_0; //input with pull + 8001758: 4b8d ldr r3, [pc, #564] ; (8001990 ) + 800175a: 681b ldr r3, [r3, #0] + 800175c: 4a8c ldr r2, [pc, #560] ; (8001990 ) + 800175e: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8001762: 6013 str r3, [r2, #0] + GPIOA->CRL |= GPIO_CRL_CNF1_1; + 8001764: 4b8a ldr r3, [pc, #552] ; (8001990 ) + 8001766: 681b ldr r3, [r3, #0] + 8001768: 4a89 ldr r2, [pc, #548] ; (8001990 ) + 800176a: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800176e: 6013 str r3, [r2, #0] + GPIOA->ODR |= GPIO_ODR_ODR1; //pull-up on + 8001770: 4b87 ldr r3, [pc, #540] ; (8001990 ) + 8001772: 68db ldr r3, [r3, #12] + 8001774: 4a86 ldr r2, [pc, #536] ; (8001990 ) + 8001776: f043 0302 orr.w r3, r3, #2 + 800177a: 60d3 str r3, [r2, #12] + + //PA2 - Button 2 + GPIOA->CRL &= ~GPIO_CRL_MODE2; //input mode + 800177c: 4b84 ldr r3, [pc, #528] ; (8001990 ) + 800177e: 681b ldr r3, [r3, #0] + 8001780: 4a83 ldr r2, [pc, #524] ; (8001990 ) + 8001782: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8001786: 6013 str r3, [r2, #0] + GPIOA->CRL &= ~GPIO_CRL_CNF2_0; //input with pull + 8001788: 4b81 ldr r3, [pc, #516] ; (8001990 ) + 800178a: 681b ldr r3, [r3, #0] + 800178c: 4a80 ldr r2, [pc, #512] ; (8001990 ) + 800178e: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 8001792: 6013 str r3, [r2, #0] + GPIOA->CRL |= GPIO_CRL_CNF2_1; + 8001794: 4b7e ldr r3, [pc, #504] ; (8001990 ) + 8001796: 681b ldr r3, [r3, #0] + 8001798: 4a7d ldr r2, [pc, #500] ; (8001990 ) + 800179a: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 800179e: 6013 str r3, [r2, #0] + GPIOA->ODR |= GPIO_ODR_ODR2; //pull-up on + 80017a0: 4b7b ldr r3, [pc, #492] ; (8001990 ) + 80017a2: 68db ldr r3, [r3, #12] + 80017a4: 4a7a ldr r2, [pc, #488] ; (8001990 ) + 80017a6: f043 0304 orr.w r3, r3, #4 + 80017aa: 60d3 str r3, [r2, #12] + + //PA3 - Button 3 + GPIOA->CRL &= ~GPIO_CRL_MODE3; //input mode + 80017ac: 4b78 ldr r3, [pc, #480] ; (8001990 ) + 80017ae: 681b ldr r3, [r3, #0] + 80017b0: 4a77 ldr r2, [pc, #476] ; (8001990 ) + 80017b2: f423 5340 bic.w r3, r3, #12288 ; 0x3000 + 80017b6: 6013 str r3, [r2, #0] + GPIOA->CRL &= ~GPIO_CRL_CNF3_0; //input with pull + 80017b8: 4b75 ldr r3, [pc, #468] ; (8001990 ) + 80017ba: 681b ldr r3, [r3, #0] + 80017bc: 4a74 ldr r2, [pc, #464] ; (8001990 ) + 80017be: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 80017c2: 6013 str r3, [r2, #0] + GPIOA->CRL |= GPIO_CRL_CNF3_1; + 80017c4: 4b72 ldr r3, [pc, #456] ; (8001990 ) + 80017c6: 681b ldr r3, [r3, #0] + 80017c8: 4a71 ldr r2, [pc, #452] ; (8001990 ) + 80017ca: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80017ce: 6013 str r3, [r2, #0] + GPIOA->ODR |= GPIO_ODR_ODR3; //pull-up on + 80017d0: 4b6f ldr r3, [pc, #444] ; (8001990 ) + 80017d2: 68db ldr r3, [r3, #12] + 80017d4: 4a6e ldr r2, [pc, #440] ; (8001990 ) + 80017d6: f043 0308 orr.w r3, r3, #8 + 80017da: 60d3 str r3, [r2, #12] + + //PA4 - Button 4 + GPIOA->CRL &= ~GPIO_CRL_MODE4; //input mode + 80017dc: 4b6c ldr r3, [pc, #432] ; (8001990 ) + 80017de: 681b ldr r3, [r3, #0] + 80017e0: 4a6b ldr r2, [pc, #428] ; (8001990 ) + 80017e2: f423 3340 bic.w r3, r3, #196608 ; 0x30000 + 80017e6: 6013 str r3, [r2, #0] + GPIOA->CRL &= ~GPIO_CRL_CNF4_0; //input with pull + 80017e8: 4b69 ldr r3, [pc, #420] ; (8001990 ) + 80017ea: 681b ldr r3, [r3, #0] + 80017ec: 4a68 ldr r2, [pc, #416] ; (8001990 ) + 80017ee: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80017f2: 6013 str r3, [r2, #0] + GPIOA->CRL |= GPIO_CRL_CNF4_1; + 80017f4: 4b66 ldr r3, [pc, #408] ; (8001990 ) + 80017f6: 681b ldr r3, [r3, #0] + 80017f8: 4a65 ldr r2, [pc, #404] ; (8001990 ) + 80017fa: f443 2300 orr.w r3, r3, #524288 ; 0x80000 + 80017fe: 6013 str r3, [r2, #0] + GPIOA->ODR |= GPIO_ODR_ODR4; //pull-up on + 8001800: 4b63 ldr r3, [pc, #396] ; (8001990 ) + 8001802: 68db ldr r3, [r3, #12] + 8001804: 4a62 ldr r2, [pc, #392] ; (8001990 ) + 8001806: f043 0310 orr.w r3, r3, #16 + 800180a: 60d3 str r3, [r2, #12] + + //PA5 - Button 5 + GPIOA->CRL &= ~GPIO_CRL_MODE5; //input mode + 800180c: 4b60 ldr r3, [pc, #384] ; (8001990 ) + 800180e: 681b ldr r3, [r3, #0] + 8001810: 4a5f ldr r2, [pc, #380] ; (8001990 ) + 8001812: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 + 8001816: 6013 str r3, [r2, #0] + GPIOA->CRL &= ~GPIO_CRL_CNF5_0; //input with pull + 8001818: 4b5d ldr r3, [pc, #372] ; (8001990 ) + 800181a: 681b ldr r3, [r3, #0] + 800181c: 4a5c ldr r2, [pc, #368] ; (8001990 ) + 800181e: f423 0380 bic.w r3, r3, #4194304 ; 0x400000 + 8001822: 6013 str r3, [r2, #0] + GPIOA->CRL |= GPIO_CRL_CNF5_1; + 8001824: 4b5a ldr r3, [pc, #360] ; (8001990 ) + 8001826: 681b ldr r3, [r3, #0] + 8001828: 4a59 ldr r2, [pc, #356] ; (8001990 ) + 800182a: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 800182e: 6013 str r3, [r2, #0] + GPIOA->ODR |= GPIO_ODR_ODR5; //pull-up on + 8001830: 4b57 ldr r3, [pc, #348] ; (8001990 ) + 8001832: 68db ldr r3, [r3, #12] + 8001834: 4a56 ldr r2, [pc, #344] ; (8001990 ) + 8001836: f043 0320 orr.w r3, r3, #32 + 800183a: 60d3 str r3, [r2, #12] + + //PA6 - Battery monitor switch + GPIOA->CRL |= GPIO_CRL_MODE6; //output 50 MHz + 800183c: 4b54 ldr r3, [pc, #336] ; (8001990 ) + 800183e: 681b ldr r3, [r3, #0] + 8001840: 4a53 ldr r2, [pc, #332] ; (8001990 ) + 8001842: f043 7340 orr.w r3, r3, #50331648 ; 0x3000000 + 8001846: 6013 str r3, [r2, #0] + GPIOA->CRL &= ~GPIO_CRL_CNF6; //output push-pull + 8001848: 4b51 ldr r3, [pc, #324] ; (8001990 ) + 800184a: 681b ldr r3, [r3, #0] + 800184c: 4a50 ldr r2, [pc, #320] ; (8001990 ) + 800184e: f023 6340 bic.w r3, r3, #201326592 ; 0xc000000 + 8001852: 6013 str r3, [r2, #0] + + //PA7 - Piezo Buzzer (PWM) + GPIOA->CRL |= GPIO_CRL_MODE7; //output mode + 8001854: 4b4e ldr r3, [pc, #312] ; (8001990 ) + 8001856: 681b ldr r3, [r3, #0] + 8001858: 4a4d ldr r2, [pc, #308] ; (8001990 ) + 800185a: f043 5340 orr.w r3, r3, #805306368 ; 0x30000000 + 800185e: 6013 str r3, [r2, #0] + GPIOA->CRL &= ~GPIO_CRL_CNF7_0; //alternate output push-pull + 8001860: 4b4b ldr r3, [pc, #300] ; (8001990 ) + 8001862: 681b ldr r3, [r3, #0] + 8001864: 4a4a ldr r2, [pc, #296] ; (8001990 ) + 8001866: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 800186a: 6013 str r3, [r2, #0] + GPIOA->CRL |= GPIO_CRL_CNF7_1; + 800186c: 4b48 ldr r3, [pc, #288] ; (8001990 ) + 800186e: 681b ldr r3, [r3, #0] + 8001870: 4a47 ldr r2, [pc, #284] ; (8001990 ) + 8001872: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8001876: 6013 str r3, [r2, #0] + + //PA8 - RES (SSD1306) + GPIOA->CRH |= GPIO_CRH_MODE8; //output 50 MHz + 8001878: 4b45 ldr r3, [pc, #276] ; (8001990 ) + 800187a: 685b ldr r3, [r3, #4] + 800187c: 4a44 ldr r2, [pc, #272] ; (8001990 ) + 800187e: f043 0303 orr.w r3, r3, #3 + 8001882: 6053 str r3, [r2, #4] + GPIOA->CRH &= ~GPIO_CRH_CNF8; //output push-pull + 8001884: 4b42 ldr r3, [pc, #264] ; (8001990 ) + 8001886: 685b ldr r3, [r3, #4] + 8001888: 4a41 ldr r2, [pc, #260] ; (8001990 ) + 800188a: f023 030c bic.w r3, r3, #12 + 800188e: 6053 str r3, [r2, #4] + + //PA9 - USART TX1 (Debug out) + GPIOA->CRH |= GPIO_CRH_MODE9; //output 50 MHz + 8001890: 4b3f ldr r3, [pc, #252] ; (8001990 ) + 8001892: 685b ldr r3, [r3, #4] + 8001894: 4a3e ldr r2, [pc, #248] ; (8001990 ) + 8001896: f043 0330 orr.w r3, r3, #48 ; 0x30 + 800189a: 6053 str r3, [r2, #4] + GPIOA->CRH &= ~GPIO_CRH_CNF9_0; //alternate output push-pull + 800189c: 4b3c ldr r3, [pc, #240] ; (8001990 ) + 800189e: 685b ldr r3, [r3, #4] + 80018a0: 4a3b ldr r2, [pc, #236] ; (8001990 ) + 80018a2: f023 0340 bic.w r3, r3, #64 ; 0x40 + 80018a6: 6053 str r3, [r2, #4] + GPIOA->CRH |= GPIO_CRH_CNF9_1; + 80018a8: 4b39 ldr r3, [pc, #228] ; (8001990 ) + 80018aa: 685b ldr r3, [r3, #4] + 80018ac: 4a38 ldr r2, [pc, #224] ; (8001990 ) + 80018ae: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80018b2: 6053 str r3, [r2, #4] + + //PA10 - USART RX1 (GPS NMEA here) + GPIOA->CRH &= ~GPIO_CRH_MODE10; //input + 80018b4: 4b36 ldr r3, [pc, #216] ; (8001990 ) + 80018b6: 685b ldr r3, [r3, #4] + 80018b8: 4a35 ldr r2, [pc, #212] ; (8001990 ) + 80018ba: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80018be: 6053 str r3, [r2, #4] + GPIOA->CRH |= GPIO_CRH_CNF10_0; //alternate input floating + 80018c0: 4b33 ldr r3, [pc, #204] ; (8001990 ) + 80018c2: 685b ldr r3, [r3, #4] + 80018c4: 4a32 ldr r2, [pc, #200] ; (8001990 ) + 80018c6: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 80018ca: 6053 str r3, [r2, #4] + GPIOA->CRH &= ~GPIO_CRH_CNF10_1; + 80018cc: 4b30 ldr r3, [pc, #192] ; (8001990 ) + 80018ce: 685b ldr r3, [r3, #4] + 80018d0: 4a2f ldr r2, [pc, #188] ; (8001990 ) + 80018d2: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 80018d6: 6053 str r3, [r2, #4] + + //PA11 - GPS (PPS interrupt) + GPIOA->CRH &= ~GPIO_CRH_MODE11; //input mode + 80018d8: 4b2d ldr r3, [pc, #180] ; (8001990 ) + 80018da: 685b ldr r3, [r3, #4] + 80018dc: 4a2c ldr r2, [pc, #176] ; (8001990 ) + 80018de: f423 5340 bic.w r3, r3, #12288 ; 0x3000 + 80018e2: 6053 str r3, [r2, #4] + GPIOA->CRH &= ~GPIO_CRH_CNF11_0; //input with pull + 80018e4: 4b2a ldr r3, [pc, #168] ; (8001990 ) + 80018e6: 685b ldr r3, [r3, #4] + 80018e8: 4a29 ldr r2, [pc, #164] ; (8001990 ) + 80018ea: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 80018ee: 6053 str r3, [r2, #4] + GPIOA->CRH |= GPIO_CRH_CNF11_1; + 80018f0: 4b27 ldr r3, [pc, #156] ; (8001990 ) + 80018f2: 685b ldr r3, [r3, #4] + 80018f4: 4a26 ldr r2, [pc, #152] ; (8001990 ) + 80018f6: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80018fa: 6053 str r3, [r2, #4] + GPIOA->ODR &= ~GPIO_ODR_ODR11; //pull-down + 80018fc: 4b24 ldr r3, [pc, #144] ; (8001990 ) + 80018fe: 68db ldr r3, [r3, #12] + 8001900: 4a23 ldr r2, [pc, #140] ; (8001990 ) + 8001902: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 8001906: 60d3 str r3, [r2, #12] + + //PA12 - CTS (SI4463) + GPIOA->CRH &= ~GPIO_CRH_MODE11; //input mode + 8001908: 4b21 ldr r3, [pc, #132] ; (8001990 ) + 800190a: 685b ldr r3, [r3, #4] + 800190c: 4a20 ldr r2, [pc, #128] ; (8001990 ) + 800190e: f423 5340 bic.w r3, r3, #12288 ; 0x3000 + 8001912: 6053 str r3, [r2, #4] + GPIOA->CRH &= ~GPIO_CRH_CNF11_0; //input with pull + 8001914: 4b1e ldr r3, [pc, #120] ; (8001990 ) + 8001916: 685b ldr r3, [r3, #4] + 8001918: 4a1d ldr r2, [pc, #116] ; (8001990 ) + 800191a: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800191e: 6053 str r3, [r2, #4] + GPIOA->CRH |= GPIO_CRH_CNF11_1; + 8001920: 4b1b ldr r3, [pc, #108] ; (8001990 ) + 8001922: 685b ldr r3, [r3, #4] + 8001924: 4a1a ldr r2, [pc, #104] ; (8001990 ) + 8001926: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800192a: 6053 str r3, [r2, #4] + GPIOA->ODR &= ~GPIO_ODR_ODR11; //pull-down + 800192c: 4b18 ldr r3, [pc, #96] ; (8001990 ) + 800192e: 68db ldr r3, [r3, #12] + 8001930: 4a17 ldr r2, [pc, #92] ; (8001990 ) + 8001932: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 8001936: 60d3 str r3, [r2, #12] + + //PA15 - CS (SI4463) + GPIOA->CRH |= GPIO_CRH_MODE15; //output 50 MHz + 8001938: 4b15 ldr r3, [pc, #84] ; (8001990 ) + 800193a: 685b ldr r3, [r3, #4] + 800193c: 4a14 ldr r2, [pc, #80] ; (8001990 ) + 800193e: f043 5340 orr.w r3, r3, #805306368 ; 0x30000000 + 8001942: 6053 str r3, [r2, #4] + GPIOA->CRH &= ~GPIO_CRH_CNF15; //output push-pull + 8001944: 4b12 ldr r3, [pc, #72] ; (8001990 ) + 8001946: 685b ldr r3, [r3, #4] + 8001948: 4a11 ldr r2, [pc, #68] ; (8001990 ) + 800194a: f023 4340 bic.w r3, r3, #3221225472 ; 0xc0000000 + 800194e: 6053 str r3, [r2, #4] + + + //Port B + RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; + 8001950: 4b0e ldr r3, [pc, #56] ; (800198c ) + 8001952: 699b ldr r3, [r3, #24] + 8001954: 4a0d ldr r2, [pc, #52] ; (800198c ) + 8001956: f043 0308 orr.w r3, r3, #8 + 800195a: 6193 str r3, [r2, #24] + + //PB0 - Red LED + GPIOB->CRL |= GPIO_CRL_MODE0; //output 50 MHz + 800195c: 4b0d ldr r3, [pc, #52] ; (8001994 ) + 800195e: 681b ldr r3, [r3, #0] + 8001960: 4a0c ldr r2, [pc, #48] ; (8001994 ) + 8001962: f043 0303 orr.w r3, r3, #3 + 8001966: 6013 str r3, [r2, #0] + GPIOB->CRL &= ~GPIO_CRL_CNF0; //output push-pull + 8001968: 4b0a ldr r3, [pc, #40] ; (8001994 ) + 800196a: 681b ldr r3, [r3, #0] + 800196c: 4a09 ldr r2, [pc, #36] ; (8001994 ) + 800196e: f023 030c bic.w r3, r3, #12 + 8001972: 6013 str r3, [r2, #0] + + //PB1 - Green LED + GPIOB->CRL |= GPIO_CRL_MODE1; //output 50 MHz + 8001974: 4b07 ldr r3, [pc, #28] ; (8001994 ) + 8001976: 681b ldr r3, [r3, #0] + 8001978: 4a06 ldr r2, [pc, #24] ; (8001994 ) + 800197a: f043 0330 orr.w r3, r3, #48 ; 0x30 + 800197e: 6013 str r3, [r2, #0] + GPIOB->CRL &= ~GPIO_CRL_CNF1; //output push-pull + 8001980: 4b04 ldr r3, [pc, #16] ; (8001994 ) + 8001982: 681b ldr r3, [r3, #0] + 8001984: 4a03 ldr r2, [pc, #12] ; (8001994 ) + 8001986: f023 03c0 bic.w r3, r3, #192 ; 0xc0 + 800198a: e005 b.n 8001998 + 800198c: 40021000 .word 0x40021000 + 8001990: 40010800 .word 0x40010800 + 8001994: 40010c00 .word 0x40010c00 + 8001998: 6013 str r3, [r2, #0] + + //PB3 - SCK (SI4463) + GPIOB->CRL |= GPIO_CRL_MODE3; //output 50 MHz + 800199a: 4b62 ldr r3, [pc, #392] ; (8001b24 ) + 800199c: 681b ldr r3, [r3, #0] + 800199e: 4a61 ldr r2, [pc, #388] ; (8001b24 ) + 80019a0: f443 5340 orr.w r3, r3, #12288 ; 0x3000 + 80019a4: 6013 str r3, [r2, #0] + GPIOB->CRL &= ~GPIO_CRL_CNF3_0; //alternate output push-pull + 80019a6: 4b5f ldr r3, [pc, #380] ; (8001b24 ) + 80019a8: 681b ldr r3, [r3, #0] + 80019aa: 4a5e ldr r2, [pc, #376] ; (8001b24 ) + 80019ac: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 80019b0: 6013 str r3, [r2, #0] + GPIOB->CRL |= GPIO_CRL_CNF3_1; + 80019b2: 4b5c ldr r3, [pc, #368] ; (8001b24 ) + 80019b4: 681b ldr r3, [r3, #0] + 80019b6: 4a5b ldr r2, [pc, #364] ; (8001b24 ) + 80019b8: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80019bc: 6013 str r3, [r2, #0] + + //PB4 - MISO (SI4463) + GPIOB->CRL &= ~GPIO_CRL_MODE4; //input mode + 80019be: 4b59 ldr r3, [pc, #356] ; (8001b24 ) + 80019c0: 681b ldr r3, [r3, #0] + 80019c2: 4a58 ldr r2, [pc, #352] ; (8001b24 ) + 80019c4: f423 3340 bic.w r3, r3, #196608 ; 0x30000 + 80019c8: 6013 str r3, [r2, #0] + GPIOB->CRL |= GPIO_CRL_CNF4_0; //floating input + 80019ca: 4b56 ldr r3, [pc, #344] ; (8001b24 ) + 80019cc: 681b ldr r3, [r3, #0] + 80019ce: 4a55 ldr r2, [pc, #340] ; (8001b24 ) + 80019d0: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 80019d4: 6013 str r3, [r2, #0] + GPIOB->CRL &= ~GPIO_CRL_CNF4_1; + 80019d6: 4b53 ldr r3, [pc, #332] ; (8001b24 ) + 80019d8: 681b ldr r3, [r3, #0] + 80019da: 4a52 ldr r2, [pc, #328] ; (8001b24 ) + 80019dc: f423 2300 bic.w r3, r3, #524288 ; 0x80000 + 80019e0: 6013 str r3, [r2, #0] + + //PB5 - MOSI (SI4463) + GPIOB->CRL |= GPIO_CRL_MODE5; //output 50 MHz + 80019e2: 4b50 ldr r3, [pc, #320] ; (8001b24 ) + 80019e4: 681b ldr r3, [r3, #0] + 80019e6: 4a4f ldr r2, [pc, #316] ; (8001b24 ) + 80019e8: f443 1340 orr.w r3, r3, #3145728 ; 0x300000 + 80019ec: 6013 str r3, [r2, #0] + GPIOB->CRL &= ~GPIO_CRL_CNF5_0; //alternate output push-pull + 80019ee: 4b4d ldr r3, [pc, #308] ; (8001b24 ) + 80019f0: 681b ldr r3, [r3, #0] + 80019f2: 4a4c ldr r2, [pc, #304] ; (8001b24 ) + 80019f4: f423 0380 bic.w r3, r3, #4194304 ; 0x400000 + 80019f8: 6013 str r3, [r2, #0] + GPIOB->CRL |= GPIO_CRL_CNF5_1; + 80019fa: 4b4a ldr r3, [pc, #296] ; (8001b24 ) + 80019fc: 681b ldr r3, [r3, #0] + 80019fe: 4a49 ldr r2, [pc, #292] ; (8001b24 ) + 8001a00: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8001a04: 6013 str r3, [r2, #0] + + //PB6 - IRQn (SI4463 interrupt) + GPIOB->CRL &= ~GPIO_CRL_MODE6; //input mode + 8001a06: 4b47 ldr r3, [pc, #284] ; (8001b24 ) + 8001a08: 681b ldr r3, [r3, #0] + 8001a0a: 4a46 ldr r2, [pc, #280] ; (8001b24 ) + 8001a0c: f023 7340 bic.w r3, r3, #50331648 ; 0x3000000 + 8001a10: 6013 str r3, [r2, #0] + GPIOB->CRL &= ~GPIO_CRL_CNF6_0; //input with pull + 8001a12: 4b44 ldr r3, [pc, #272] ; (8001b24 ) + 8001a14: 681b ldr r3, [r3, #0] + 8001a16: 4a43 ldr r2, [pc, #268] ; (8001b24 ) + 8001a18: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 8001a1c: 6013 str r3, [r2, #0] + GPIOB->CRL |= GPIO_CRL_CNF6_1; + 8001a1e: 4b41 ldr r3, [pc, #260] ; (8001b24 ) + 8001a20: 681b ldr r3, [r3, #0] + 8001a22: 4a40 ldr r2, [pc, #256] ; (8001b24 ) + 8001a24: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 + 8001a28: 6013 str r3, [r2, #0] + GPIOB->ODR |= GPIO_ODR_ODR6; //pull-up + 8001a2a: 4b3e ldr r3, [pc, #248] ; (8001b24 ) + 8001a2c: 68db ldr r3, [r3, #12] + 8001a2e: 4a3d ldr r2, [pc, #244] ; (8001b24 ) + 8001a30: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8001a34: 60d3 str r3, [r2, #12] + + //PB7 - SDN (SI4463) + GPIOB->CRL |= GPIO_CRL_MODE7; //output 50 MHz + 8001a36: 4b3b ldr r3, [pc, #236] ; (8001b24 ) + 8001a38: 681b ldr r3, [r3, #0] + 8001a3a: 4a3a ldr r2, [pc, #232] ; (8001b24 ) + 8001a3c: f043 5340 orr.w r3, r3, #805306368 ; 0x30000000 + 8001a40: 6013 str r3, [r2, #0] + GPIOB->CRL &= ~GPIO_CRL_CNF7; //output push-pull + 8001a42: 4b38 ldr r3, [pc, #224] ; (8001b24 ) + 8001a44: 681b ldr r3, [r3, #0] + 8001a46: 4a37 ldr r2, [pc, #220] ; (8001b24 ) + 8001a48: f023 4340 bic.w r3, r3, #3221225472 ; 0xc0000000 + 8001a4c: 6013 str r3, [r2, #0] + + //PB10 - I2C SCL + GPIOB->CRH |= GPIO_CRH_MODE10; //output 50 MHz + 8001a4e: 4b35 ldr r3, [pc, #212] ; (8001b24 ) + 8001a50: 685b ldr r3, [r3, #4] + 8001a52: 4a34 ldr r2, [pc, #208] ; (8001b24 ) + 8001a54: f443 7340 orr.w r3, r3, #768 ; 0x300 + 8001a58: 6053 str r3, [r2, #4] + GPIOB->CRH |= GPIO_CRH_CNF10; //alternate function open-drain + 8001a5a: 4b32 ldr r3, [pc, #200] ; (8001b24 ) + 8001a5c: 685b ldr r3, [r3, #4] + 8001a5e: 4a31 ldr r2, [pc, #196] ; (8001b24 ) + 8001a60: f443 6340 orr.w r3, r3, #3072 ; 0xc00 + 8001a64: 6053 str r3, [r2, #4] + + //PB11 - I2C SDA + GPIOB->CRH |= GPIO_CRH_MODE11; //output max speed + 8001a66: 4b2f ldr r3, [pc, #188] ; (8001b24 ) + 8001a68: 685b ldr r3, [r3, #4] + 8001a6a: 4a2e ldr r2, [pc, #184] ; (8001b24 ) + 8001a6c: f443 5340 orr.w r3, r3, #12288 ; 0x3000 + 8001a70: 6053 str r3, [r2, #4] + GPIOB->CRH |= GPIO_CRH_CNF11; //alternate function open-drain + 8001a72: 4b2c ldr r3, [pc, #176] ; (8001b24 ) + 8001a74: 685b ldr r3, [r3, #4] + 8001a76: 4a2b ldr r2, [pc, #172] ; (8001b24 ) + 8001a78: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 8001a7c: 6053 str r3, [r2, #4] + + //PB12 - CS (SSD1306) + GPIOB->CRH |= GPIO_CRH_MODE12; //output 50 MHz + 8001a7e: 4b29 ldr r3, [pc, #164] ; (8001b24 ) + 8001a80: 685b ldr r3, [r3, #4] + 8001a82: 4a28 ldr r2, [pc, #160] ; (8001b24 ) + 8001a84: f443 3340 orr.w r3, r3, #196608 ; 0x30000 + 8001a88: 6053 str r3, [r2, #4] + GPIOB->CRH &= ~GPIO_CRH_CNF12; //output push-pull + 8001a8a: 4b26 ldr r3, [pc, #152] ; (8001b24 ) + 8001a8c: 685b ldr r3, [r3, #4] + 8001a8e: 4a25 ldr r2, [pc, #148] ; (8001b24 ) + 8001a90: f423 2340 bic.w r3, r3, #786432 ; 0xc0000 + 8001a94: 6053 str r3, [r2, #4] + + //PB13 - SCK (SSD1306) + GPIOB->CRH |= GPIO_CRH_MODE13; //output 50 MHz + 8001a96: 4b23 ldr r3, [pc, #140] ; (8001b24 ) + 8001a98: 685b ldr r3, [r3, #4] + 8001a9a: 4a22 ldr r2, [pc, #136] ; (8001b24 ) + 8001a9c: f443 1340 orr.w r3, r3, #3145728 ; 0x300000 + 8001aa0: 6053 str r3, [r2, #4] + GPIOB->CRH &= ~GPIO_CRH_CNF13_0; //alternate output push-pull + 8001aa2: 4b20 ldr r3, [pc, #128] ; (8001b24 ) + 8001aa4: 685b ldr r3, [r3, #4] + 8001aa6: 4a1f ldr r2, [pc, #124] ; (8001b24 ) + 8001aa8: f423 0380 bic.w r3, r3, #4194304 ; 0x400000 + 8001aac: 6053 str r3, [r2, #4] + GPIOB->CRH |= GPIO_CRH_CNF13_1; + 8001aae: 4b1d ldr r3, [pc, #116] ; (8001b24 ) + 8001ab0: 685b ldr r3, [r3, #4] + 8001ab2: 4a1c ldr r2, [pc, #112] ; (8001b24 ) + 8001ab4: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8001ab8: 6053 str r3, [r2, #4] + + //PB14 - D/C (SSD1306) + GPIOB->CRH |= GPIO_CRH_MODE14; //output 50 MHz + 8001aba: 4b1a ldr r3, [pc, #104] ; (8001b24 ) + 8001abc: 685b ldr r3, [r3, #4] + 8001abe: 4a19 ldr r2, [pc, #100] ; (8001b24 ) + 8001ac0: f043 7340 orr.w r3, r3, #50331648 ; 0x3000000 + 8001ac4: 6053 str r3, [r2, #4] + GPIOB->CRH &= ~GPIO_CRH_CNF14; //output push-pull + 8001ac6: 4b17 ldr r3, [pc, #92] ; (8001b24 ) + 8001ac8: 685b ldr r3, [r3, #4] + 8001aca: 4a16 ldr r2, [pc, #88] ; (8001b24 ) + 8001acc: f023 6340 bic.w r3, r3, #201326592 ; 0xc000000 + 8001ad0: 6053 str r3, [r2, #4] + + //PB15 - MOSI (SSD1306) + GPIOB->CRH |= GPIO_CRH_MODE15; //output 50 MHz + 8001ad2: 4b14 ldr r3, [pc, #80] ; (8001b24 ) + 8001ad4: 685b ldr r3, [r3, #4] + 8001ad6: 4a13 ldr r2, [pc, #76] ; (8001b24 ) + 8001ad8: f043 5340 orr.w r3, r3, #805306368 ; 0x30000000 + 8001adc: 6053 str r3, [r2, #4] + GPIOB->CRH &= ~GPIO_CRH_CNF15_0; //alternate output push-pull + 8001ade: 4b11 ldr r3, [pc, #68] ; (8001b24 ) + 8001ae0: 685b ldr r3, [r3, #4] + 8001ae2: 4a10 ldr r2, [pc, #64] ; (8001b24 ) + 8001ae4: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 + 8001ae8: 6053 str r3, [r2, #4] + GPIOB->CRH |= GPIO_CRH_CNF15_1; + 8001aea: 4b0e ldr r3, [pc, #56] ; (8001b24 ) + 8001aec: 685b ldr r3, [r3, #4] + 8001aee: 4a0d ldr r2, [pc, #52] ; (8001b24 ) + 8001af0: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8001af4: 6053 str r3, [r2, #4] + + + //Port C + RCC->APB2ENR |= RCC_APB2ENR_IOPCEN; + 8001af6: 4b0c ldr r3, [pc, #48] ; (8001b28 ) + 8001af8: 699b ldr r3, [r3, #24] + 8001afa: 4a0b ldr r2, [pc, #44] ; (8001b28 ) + 8001afc: f043 0310 orr.w r3, r3, #16 + 8001b00: 6193 str r3, [r2, #24] + + //PC13 - Blue led + GPIOC->CRH |= GPIO_CRH_MODE13; //output 50 MHz + 8001b02: 4b0a ldr r3, [pc, #40] ; (8001b2c ) + 8001b04: 685b ldr r3, [r3, #4] + 8001b06: 4a09 ldr r2, [pc, #36] ; (8001b2c ) + 8001b08: f443 1340 orr.w r3, r3, #3145728 ; 0x300000 + 8001b0c: 6053 str r3, [r2, #4] + GPIOC->CRH &= ~GPIO_CRH_CNF13; //output push-pull + 8001b0e: 4b07 ldr r3, [pc, #28] ; (8001b2c ) + 8001b10: 685b ldr r3, [r3, #4] + 8001b12: 4a06 ldr r2, [pc, #24] ; (8001b2c ) + 8001b14: f423 0340 bic.w r3, r3, #12582912 ; 0xc00000 + 8001b18: 6053 str r3, [r2, #4] + led_board_off(); + 8001b1a: f000 f883 bl 8001c24 +} + 8001b1e: bf00 nop + 8001b20: bd80 pop {r7, pc} + 8001b22: bf00 nop + 8001b24: 40010c00 .word 0x40010c00 + 8001b28: 40021000 .word 0x40021000 + 8001b2c: 40011000 .word 0x40011000 + +08001b30 : + + + +//Init external interrupts +void ext_int_init(void) +{ + 8001b30: b580 push {r7, lr} + 8001b32: af00 add r7, sp, #0 + RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; //enable afio clock + 8001b34: 4b19 ldr r3, [pc, #100] ; (8001b9c ) + 8001b36: 699b ldr r3, [r3, #24] + 8001b38: 4a18 ldr r2, [pc, #96] ; (8001b9c ) + 8001b3a: f043 0301 orr.w r3, r3, #1 + 8001b3e: 6193 str r3, [r2, #24] + + //PA11 GPS PPS interrupt on rising edge + AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI11_PA; //exti 11 source is port A + 8001b40: 4b17 ldr r3, [pc, #92] ; (8001ba0 ) + 8001b42: 4a17 ldr r2, [pc, #92] ; (8001ba0 ) + 8001b44: 691b ldr r3, [r3, #16] + 8001b46: 6113 str r3, [r2, #16] + EXTI->RTSR |= EXTI_RTSR_TR11; //interrupt 11 on rising edge + 8001b48: 4b16 ldr r3, [pc, #88] ; (8001ba4 ) + 8001b4a: 689b ldr r3, [r3, #8] + 8001b4c: 4a15 ldr r2, [pc, #84] ; (8001ba4 ) + 8001b4e: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 8001b52: 6093 str r3, [r2, #8] + EXTI->IMR |= EXTI_IMR_MR11; //unmask interrupt 11 + 8001b54: 4b13 ldr r3, [pc, #76] ; (8001ba4 ) + 8001b56: 681b ldr r3, [r3, #0] + 8001b58: 4a12 ldr r2, [pc, #72] ; (8001ba4 ) + 8001b5a: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 8001b5e: 6013 str r3, [r2, #0] + NVIC_EnableIRQ(EXTI15_10_IRQn); //enable interrupt + 8001b60: 2028 movs r0, #40 ; 0x28 + 8001b62: f7ff fdc7 bl 80016f4 + + //PB6 SI4463 RX interrupt on falling edge + AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI6_PB; //exti 6 source is port B + 8001b66: 4b0e ldr r3, [pc, #56] ; (8001ba0 ) + 8001b68: 68db ldr r3, [r3, #12] + 8001b6a: 4a0d ldr r2, [pc, #52] ; (8001ba0 ) + 8001b6c: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8001b70: 60d3 str r3, [r2, #12] + EXTI->FTSR |= EXTI_FTSR_TR6; //interrupt 6 on falling edge + 8001b72: 4b0c ldr r3, [pc, #48] ; (8001ba4 ) + 8001b74: 68db ldr r3, [r3, #12] + 8001b76: 4a0b ldr r2, [pc, #44] ; (8001ba4 ) + 8001b78: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8001b7c: 60d3 str r3, [r2, #12] + EXTI->IMR |= EXTI_IMR_MR6; //unmask interrupt 6 + 8001b7e: 4b09 ldr r3, [pc, #36] ; (8001ba4 ) + 8001b80: 681b ldr r3, [r3, #0] + 8001b82: 4a08 ldr r2, [pc, #32] ; (8001ba4 ) + 8001b84: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8001b88: 6013 str r3, [r2, #0] + NVIC_EnableIRQ(EXTI9_5_IRQn); //enable interrupt + 8001b8a: 2017 movs r0, #23 + 8001b8c: f7ff fdb2 bl 80016f4 + + EXTI->PR = (uint32_t)0x0007FFFF; //clear all pending interrupts + 8001b90: 4b04 ldr r3, [pc, #16] ; (8001ba4 ) + 8001b92: 4a05 ldr r2, [pc, #20] ; (8001ba8 ) + 8001b94: 615a str r2, [r3, #20] +} + 8001b96: bf00 nop + 8001b98: bd80 pop {r7, pc} + 8001b9a: bf00 nop + 8001b9c: 40021000 .word 0x40021000 + 8001ba0: 40010000 .word 0x40010000 + 8001ba4: 40010400 .word 0x40010400 + 8001ba8: 0007ffff .word 0x0007ffff + +08001bac : + + + +//Red led on +void led_red_on(void) +{ + 8001bac: b480 push {r7} + 8001bae: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BS0; + 8001bb0: 4b03 ldr r3, [pc, #12] ; (8001bc0 ) + 8001bb2: 2201 movs r2, #1 + 8001bb4: 611a str r2, [r3, #16] +} + 8001bb6: bf00 nop + 8001bb8: 46bd mov sp, r7 + 8001bba: bc80 pop {r7} + 8001bbc: 4770 bx lr + 8001bbe: bf00 nop + 8001bc0: 40010c00 .word 0x40010c00 + +08001bc4 : + + + +//Red led off +void led_red_off(void) +{ + 8001bc4: b480 push {r7} + 8001bc6: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BR0; + 8001bc8: 4b03 ldr r3, [pc, #12] ; (8001bd8 ) + 8001bca: f44f 3280 mov.w r2, #65536 ; 0x10000 + 8001bce: 611a str r2, [r3, #16] +} + 8001bd0: bf00 nop + 8001bd2: 46bd mov sp, r7 + 8001bd4: bc80 pop {r7} + 8001bd6: 4770 bx lr + 8001bd8: 40010c00 .word 0x40010c00 + +08001bdc : + + + +//Red green on +void led_green_on(void) +{ + 8001bdc: b480 push {r7} + 8001bde: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BS1; + 8001be0: 4b03 ldr r3, [pc, #12] ; (8001bf0 ) + 8001be2: 2202 movs r2, #2 + 8001be4: 611a str r2, [r3, #16] +} + 8001be6: bf00 nop + 8001be8: 46bd mov sp, r7 + 8001bea: bc80 pop {r7} + 8001bec: 4770 bx lr + 8001bee: bf00 nop + 8001bf0: 40010c00 .word 0x40010c00 + +08001bf4 : + + + +//Red green off +void led_green_off(void) +{ + 8001bf4: b480 push {r7} + 8001bf6: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BR1; + 8001bf8: 4b03 ldr r3, [pc, #12] ; (8001c08 ) + 8001bfa: f44f 3200 mov.w r2, #131072 ; 0x20000 + 8001bfe: 611a str r2, [r3, #16] +} + 8001c00: bf00 nop + 8001c02: 46bd mov sp, r7 + 8001c04: bc80 pop {r7} + 8001c06: 4770 bx lr + 8001c08: 40010c00 .word 0x40010c00 + +08001c0c : + + + +//Blue led on +void led_board_on(void) +{ + 8001c0c: b480 push {r7} + 8001c0e: af00 add r7, sp, #0 + GPIOC->BSRR = GPIO_BSRR_BR13; + 8001c10: 4b03 ldr r3, [pc, #12] ; (8001c20 ) + 8001c12: f04f 5200 mov.w r2, #536870912 ; 0x20000000 + 8001c16: 611a str r2, [r3, #16] +} + 8001c18: bf00 nop + 8001c1a: 46bd mov sp, r7 + 8001c1c: bc80 pop {r7} + 8001c1e: 4770 bx lr + 8001c20: 40011000 .word 0x40011000 + +08001c24 : + + + +//Blue led off +void led_board_off(void) +{ + 8001c24: b480 push {r7} + 8001c26: af00 add r7, sp, #0 + GPIOC->BSRR = GPIO_BSRR_BS13; + 8001c28: 4b03 ldr r3, [pc, #12] ; (8001c38 ) + 8001c2a: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8001c2e: 611a str r2, [r3, #16] +} + 8001c30: bf00 nop + 8001c32: 46bd mov sp, r7 + 8001c34: bc80 pop {r7} + 8001c36: 4770 bx lr + 8001c38: 40011000 .word 0x40011000 + +08001c3c : + + + +//SDN SI4463 active +void sdn_si4463_active(void) +{ + 8001c3c: b480 push {r7} + 8001c3e: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BS7; + 8001c40: 4b03 ldr r3, [pc, #12] ; (8001c50 ) + 8001c42: 2280 movs r2, #128 ; 0x80 + 8001c44: 611a str r2, [r3, #16] +} + 8001c46: bf00 nop + 8001c48: 46bd mov sp, r7 + 8001c4a: bc80 pop {r7} + 8001c4c: 4770 bx lr + 8001c4e: bf00 nop + 8001c50: 40010c00 .word 0x40010c00 + +08001c54 : + + + +//SDN SI4463 inactive +void sdn_si4463_inactive(void) +{ + 8001c54: b480 push {r7} + 8001c56: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BR7; + 8001c58: 4b03 ldr r3, [pc, #12] ; (8001c68 ) + 8001c5a: f44f 0200 mov.w r2, #8388608 ; 0x800000 + 8001c5e: 611a str r2, [r3, #16] +} + 8001c60: bf00 nop + 8001c62: 46bd mov sp, r7 + 8001c64: bc80 pop {r7} + 8001c66: 4770 bx lr + 8001c68: 40010c00 .word 0x40010c00 + +08001c6c : + + + +//CS SI4463 active +void cs_si4463_active(void) +{ + 8001c6c: b480 push {r7} + 8001c6e: af00 add r7, sp, #0 + GPIOA->BSRR = GPIO_BSRR_BR15; + 8001c70: 4b03 ldr r3, [pc, #12] ; (8001c80 ) + 8001c72: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 + 8001c76: 611a str r2, [r3, #16] +} + 8001c78: bf00 nop + 8001c7a: 46bd mov sp, r7 + 8001c7c: bc80 pop {r7} + 8001c7e: 4770 bx lr + 8001c80: 40010800 .word 0x40010800 + +08001c84 : + + + +//CS SI4463 inactive +void cs_si4463_inactive(void) +{ + 8001c84: b480 push {r7} + 8001c86: af00 add r7, sp, #0 + GPIOA->BSRR = GPIO_BSRR_BS15; + 8001c88: 4b03 ldr r3, [pc, #12] ; (8001c98 ) + 8001c8a: f44f 4200 mov.w r2, #32768 ; 0x8000 + 8001c8e: 611a str r2, [r3, #16] +} + 8001c90: bf00 nop + 8001c92: 46bd mov sp, r7 + 8001c94: bc80 pop {r7} + 8001c96: 4770 bx lr + 8001c98: 40010800 .word 0x40010800 + +08001c9c : + + + +//RES SSD1306 active +void res_ssd1306_active(void) +{ + 8001c9c: b480 push {r7} + 8001c9e: af00 add r7, sp, #0 + GPIOA->BSRR = GPIO_BSRR_BR8; + 8001ca0: 4b03 ldr r3, [pc, #12] ; (8001cb0 ) + 8001ca2: f04f 7280 mov.w r2, #16777216 ; 0x1000000 + 8001ca6: 611a str r2, [r3, #16] +} + 8001ca8: bf00 nop + 8001caa: 46bd mov sp, r7 + 8001cac: bc80 pop {r7} + 8001cae: 4770 bx lr + 8001cb0: 40010800 .word 0x40010800 + +08001cb4 : + + + +//RES SSD1306 inactive +void res_ssd1306_inactive(void) +{ + 8001cb4: b480 push {r7} + 8001cb6: af00 add r7, sp, #0 + GPIOA->BSRR = GPIO_BSRR_BS8; + 8001cb8: 4b03 ldr r3, [pc, #12] ; (8001cc8 ) + 8001cba: f44f 7280 mov.w r2, #256 ; 0x100 + 8001cbe: 611a str r2, [r3, #16] +} + 8001cc0: bf00 nop + 8001cc2: 46bd mov sp, r7 + 8001cc4: bc80 pop {r7} + 8001cc6: 4770 bx lr + 8001cc8: 40010800 .word 0x40010800 + +08001ccc : + + + +//Data mode SSD1306 +void ssd1306_data_mode(void) +{ + 8001ccc: b480 push {r7} + 8001cce: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BS14; + 8001cd0: 4b03 ldr r3, [pc, #12] ; (8001ce0 ) + 8001cd2: f44f 4280 mov.w r2, #16384 ; 0x4000 + 8001cd6: 611a str r2, [r3, #16] +} + 8001cd8: bf00 nop + 8001cda: 46bd mov sp, r7 + 8001cdc: bc80 pop {r7} + 8001cde: 4770 bx lr + 8001ce0: 40010c00 .word 0x40010c00 + +08001ce4 : + + + +//Command mode SSD1306 +void ssd1306_command_mode(void) +{ + 8001ce4: b480 push {r7} + 8001ce6: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BR14; + 8001ce8: 4b03 ldr r3, [pc, #12] ; (8001cf8 ) + 8001cea: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8001cee: 611a str r2, [r3, #16] +} + 8001cf0: bf00 nop + 8001cf2: 46bd mov sp, r7 + 8001cf4: bc80 pop {r7} + 8001cf6: 4770 bx lr + 8001cf8: 40010c00 .word 0x40010c00 + +08001cfc : + + + +//CS SSD1306 active +void cs_ssd1306_active(void) +{ + 8001cfc: b480 push {r7} + 8001cfe: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BR12; + 8001d00: 4b03 ldr r3, [pc, #12] ; (8001d10 ) + 8001d02: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8001d06: 611a str r2, [r3, #16] +} + 8001d08: bf00 nop + 8001d0a: 46bd mov sp, r7 + 8001d0c: bc80 pop {r7} + 8001d0e: 4770 bx lr + 8001d10: 40010c00 .word 0x40010c00 + +08001d14 : + + + +//CS SSD1306 inactive +void cs_ssd1306_inactive(void) +{ + 8001d14: b480 push {r7} + 8001d16: af00 add r7, sp, #0 + GPIOB->BSRR = GPIO_BSRR_BS12; + 8001d18: 4b03 ldr r3, [pc, #12] ; (8001d28 ) + 8001d1a: f44f 5280 mov.w r2, #4096 ; 0x1000 + 8001d1e: 611a str r2, [r3, #16] +} + 8001d20: bf00 nop + 8001d22: 46bd mov sp, r7 + 8001d24: bc80 pop {r7} + 8001d26: 4770 bx lr + 8001d28: 40010c00 .word 0x40010c00 + +08001d2c : + + + +//Battery monitoring on +void bat_mon_on(void) +{ + 8001d2c: b480 push {r7} + 8001d2e: af00 add r7, sp, #0 + GPIOA->BSRR = GPIO_BSRR_BS6; + 8001d30: 4b03 ldr r3, [pc, #12] ; (8001d40 ) + 8001d32: 2240 movs r2, #64 ; 0x40 + 8001d34: 611a str r2, [r3, #16] +} + 8001d36: bf00 nop + 8001d38: 46bd mov sp, r7 + 8001d3a: bc80 pop {r7} + 8001d3c: 4770 bx lr + 8001d3e: bf00 nop + 8001d40: 40010800 .word 0x40010800 + +08001d44 : + + + +//Battery monitoring off +void bat_mon_off(void) +{ + 8001d44: b480 push {r7} + 8001d46: af00 add r7, sp, #0 + GPIOA->BSRR = GPIO_BSRR_BR6; + 8001d48: 4b03 ldr r3, [pc, #12] ; (8001d58 ) + 8001d4a: f44f 0280 mov.w r2, #4194304 ; 0x400000 + 8001d4e: 611a str r2, [r3, #16] +} + 8001d50: bf00 nop + 8001d52: 46bd mov sp, r7 + 8001d54: bc80 pop {r7} + 8001d56: 4770 bx lr + 8001d58: 40010800 .word 0x40010800 + +08001d5c : + + + +//Parse all gps fields all together +uint8_t parse_gps(void) +{ + 8001d5c: b580 push {r7, lr} + 8001d5e: af00 add r7, sp, #0 + memset(&gps_raw, 0, sizeof(gps_raw)); + 8001d60: 226c movs r2, #108 ; 0x6c + 8001d62: 2100 movs r1, #0 + 8001d64: 4811 ldr r0, [pc, #68] ; (8001dac ) + 8001d66: f007 fe02 bl 800996e + if (parse_RMC() && parse_GGA() && parse_GSA() && parse_GSV()) + 8001d6a: f000 f9c3 bl 80020f4 + 8001d6e: 4603 mov r3, r0 + 8001d70: 2b00 cmp r3, #0 + 8001d72: d017 beq.n 8001da4 + 8001d74: f000 fa98 bl 80022a8 + 8001d78: 4603 mov r3, r0 + 8001d7a: 2b00 cmp r3, #0 + 8001d7c: d012 beq.n 8001da4 + 8001d7e: f000 fb09 bl 8002394 + 8001d82: 4603 mov r3, r0 + 8001d84: 2b00 cmp r3, #0 + 8001d86: d00d beq.n 8001da4 + 8001d88: f000 fb7a bl 8002480 + 8001d8c: 4603 mov r3, r0 + 8001d8e: 2b00 cmp r3, #0 + 8001d90: d008 beq.n 8001da4 + { + memset(&gps_num, 0, sizeof(gps_num)); + 8001d92: 2240 movs r2, #64 ; 0x40 + 8001d94: 2100 movs r1, #0 + 8001d96: 4806 ldr r0, [pc, #24] ; (8001db0 ) + 8001d98: f007 fde9 bl 800996e + gps_raw_convert_to_numerical(); + 8001d9c: f000 f80a bl 8001db4 + return 1; + 8001da0: 2301 movs r3, #1 + 8001da2: e000 b.n 8001da6 + } + else + { + return 0; + 8001da4: 2300 movs r3, #0 + } +} + 8001da6: 4618 mov r0, r3 + 8001da8: bd80 pop {r7, pc} + 8001daa: bf00 nop + 8001dac: 20000588 .word 0x20000588 + 8001db0: 20000138 .word 0x20000138 + +08001db4 : + + + +//Converts gps_raw data (symbols) to gps_num data (numbers) with conversions if needed +void gps_raw_convert_to_numerical(void) +{ + 8001db4: b598 push {r3, r4, r7, lr} + 8001db6: af00 add r7, sp, #0 + //Time + tmp_char[0] = gps_raw.time[0]; + 8001db8: 4b8b ldr r3, [pc, #556] ; (8001fe8 ) + 8001dba: 781a ldrb r2, [r3, #0] + 8001dbc: 4b8b ldr r3, [pc, #556] ; (8001fec ) + 8001dbe: 701a strb r2, [r3, #0] + tmp_char[1] = gps_raw.time[1]; + 8001dc0: 4b89 ldr r3, [pc, #548] ; (8001fe8 ) + 8001dc2: 785a ldrb r2, [r3, #1] + 8001dc4: 4b89 ldr r3, [pc, #548] ; (8001fec ) + 8001dc6: 705a strb r2, [r3, #1] + tmp_char[2] = 0; + 8001dc8: 4b88 ldr r3, [pc, #544] ; (8001fec ) + 8001dca: 2200 movs r2, #0 + 8001dcc: 709a strb r2, [r3, #2] + gps_num.hour = (uint8_t)atoi32(&tmp_char[0]); + 8001dce: 4887 ldr r0, [pc, #540] ; (8001fec ) + 8001dd0: f006 fcda bl 8008788 + 8001dd4: 4603 mov r3, r0 + 8001dd6: b2da uxtb r2, r3 + 8001dd8: 4b85 ldr r3, [pc, #532] ; (8001ff0 ) + 8001dda: 701a strb r2, [r3, #0] + + tmp_char[0] = gps_raw.time[2]; + 8001ddc: 4b82 ldr r3, [pc, #520] ; (8001fe8 ) + 8001dde: 789a ldrb r2, [r3, #2] + 8001de0: 4b82 ldr r3, [pc, #520] ; (8001fec ) + 8001de2: 701a strb r2, [r3, #0] + tmp_char[1] = gps_raw.time[3]; + 8001de4: 4b80 ldr r3, [pc, #512] ; (8001fe8 ) + 8001de6: 78da ldrb r2, [r3, #3] + 8001de8: 4b80 ldr r3, [pc, #512] ; (8001fec ) + 8001dea: 705a strb r2, [r3, #1] + tmp_char[2] = 0; + 8001dec: 4b7f ldr r3, [pc, #508] ; (8001fec ) + 8001dee: 2200 movs r2, #0 + 8001df0: 709a strb r2, [r3, #2] + gps_num.minute = (uint8_t)atoi32(&tmp_char[0]); + 8001df2: 487e ldr r0, [pc, #504] ; (8001fec ) + 8001df4: f006 fcc8 bl 8008788 + 8001df8: 4603 mov r3, r0 + 8001dfa: b2da uxtb r2, r3 + 8001dfc: 4b7c ldr r3, [pc, #496] ; (8001ff0 ) + 8001dfe: 705a strb r2, [r3, #1] + + tmp_char[0] = gps_raw.time[4]; + 8001e00: 4b79 ldr r3, [pc, #484] ; (8001fe8 ) + 8001e02: 791a ldrb r2, [r3, #4] + 8001e04: 4b79 ldr r3, [pc, #484] ; (8001fec ) + 8001e06: 701a strb r2, [r3, #0] + tmp_char[1] = gps_raw.time[5]; + 8001e08: 4b77 ldr r3, [pc, #476] ; (8001fe8 ) + 8001e0a: 795a ldrb r2, [r3, #5] + 8001e0c: 4b77 ldr r3, [pc, #476] ; (8001fec ) + 8001e0e: 705a strb r2, [r3, #1] + tmp_char[2] = 0; + 8001e10: 4b76 ldr r3, [pc, #472] ; (8001fec ) + 8001e12: 2200 movs r2, #0 + 8001e14: 709a strb r2, [r3, #2] + gps_num.second = (uint8_t)atoi32(&tmp_char[0]); + 8001e16: 4875 ldr r0, [pc, #468] ; (8001fec ) + 8001e18: f006 fcb6 bl 8008788 + 8001e1c: 4603 mov r3, r0 + 8001e1e: b2da uxtb r2, r3 + 8001e20: 4b73 ldr r3, [pc, #460] ; (8001ff0 ) + 8001e22: 709a strb r2, [r3, #2] + + + //Date + tmp_char[0] = gps_raw.date[0]; + 8001e24: 4b70 ldr r3, [pc, #448] ; (8001fe8 ) + 8001e26: 7b1a ldrb r2, [r3, #12] + 8001e28: 4b70 ldr r3, [pc, #448] ; (8001fec ) + 8001e2a: 701a strb r2, [r3, #0] + tmp_char[1] = gps_raw.date[1]; + 8001e2c: 4b6e ldr r3, [pc, #440] ; (8001fe8 ) + 8001e2e: 7b5a ldrb r2, [r3, #13] + 8001e30: 4b6e ldr r3, [pc, #440] ; (8001fec ) + 8001e32: 705a strb r2, [r3, #1] + tmp_char[2] = 0; + 8001e34: 4b6d ldr r3, [pc, #436] ; (8001fec ) + 8001e36: 2200 movs r2, #0 + 8001e38: 709a strb r2, [r3, #2] + gps_num.day = (uint8_t)atoi32(&tmp_char[0]); + 8001e3a: 486c ldr r0, [pc, #432] ; (8001fec ) + 8001e3c: f006 fca4 bl 8008788 + 8001e40: 4603 mov r3, r0 + 8001e42: b2da uxtb r2, r3 + 8001e44: 4b6a ldr r3, [pc, #424] ; (8001ff0 ) + 8001e46: 70da strb r2, [r3, #3] + + tmp_char[0] = gps_raw.date[2]; + 8001e48: 4b67 ldr r3, [pc, #412] ; (8001fe8 ) + 8001e4a: 7b9a ldrb r2, [r3, #14] + 8001e4c: 4b67 ldr r3, [pc, #412] ; (8001fec ) + 8001e4e: 701a strb r2, [r3, #0] + tmp_char[1] = gps_raw.date[3]; + 8001e50: 4b65 ldr r3, [pc, #404] ; (8001fe8 ) + 8001e52: 7bda ldrb r2, [r3, #15] + 8001e54: 4b65 ldr r3, [pc, #404] ; (8001fec ) + 8001e56: 705a strb r2, [r3, #1] + tmp_char[2] = 0; + 8001e58: 4b64 ldr r3, [pc, #400] ; (8001fec ) + 8001e5a: 2200 movs r2, #0 + 8001e5c: 709a strb r2, [r3, #2] + gps_num.month = (uint8_t)atoi32(&tmp_char[0]); + 8001e5e: 4863 ldr r0, [pc, #396] ; (8001fec ) + 8001e60: f006 fc92 bl 8008788 + 8001e64: 4603 mov r3, r0 + 8001e66: b2da uxtb r2, r3 + 8001e68: 4b61 ldr r3, [pc, #388] ; (8001ff0 ) + 8001e6a: 711a strb r2, [r3, #4] + + tmp_char[0] = gps_raw.date[4]; + 8001e6c: 4b5e ldr r3, [pc, #376] ; (8001fe8 ) + 8001e6e: 7c1a ldrb r2, [r3, #16] + 8001e70: 4b5e ldr r3, [pc, #376] ; (8001fec ) + 8001e72: 701a strb r2, [r3, #0] + tmp_char[1] = gps_raw.date[5]; + 8001e74: 4b5c ldr r3, [pc, #368] ; (8001fe8 ) + 8001e76: 7c5a ldrb r2, [r3, #17] + 8001e78: 4b5c ldr r3, [pc, #368] ; (8001fec ) + 8001e7a: 705a strb r2, [r3, #1] + tmp_char[2] = 0; + 8001e7c: 4b5b ldr r3, [pc, #364] ; (8001fec ) + 8001e7e: 2200 movs r2, #0 + 8001e80: 709a strb r2, [r3, #2] + gps_num.year = (uint8_t)atoi32(&tmp_char[0]); + 8001e82: 485a ldr r0, [pc, #360] ; (8001fec ) + 8001e84: f006 fc80 bl 8008788 + 8001e88: 4603 mov r3, r0 + 8001e8a: b2da uxtb r2, r3 + 8001e8c: 4b58 ldr r3, [pc, #352] ; (8001ff0 ) + 8001e8e: 715a strb r2, [r3, #5] + + + //Latitude + tmp_char[0] = gps_raw.latitude[0]; + 8001e90: 4b55 ldr r3, [pc, #340] ; (8001fe8 ) + 8001e92: 7d5a ldrb r2, [r3, #21] + 8001e94: 4b55 ldr r3, [pc, #340] ; (8001fec ) + 8001e96: 701a strb r2, [r3, #0] + tmp_char[1] = gps_raw.latitude[1]; + 8001e98: 4b53 ldr r3, [pc, #332] ; (8001fe8 ) + 8001e9a: 7d9a ldrb r2, [r3, #22] + 8001e9c: 4b53 ldr r3, [pc, #332] ; (8001fec ) + 8001e9e: 705a strb r2, [r3, #1] + tmp_char[2] = 0; + 8001ea0: 4b52 ldr r3, [pc, #328] ; (8001fec ) + 8001ea2: 2200 movs r2, #0 + 8001ea4: 709a strb r2, [r3, #2] + tmp_uint8 = (uint8_t)atoi32(&tmp_char[0]); //int part of lat + 8001ea6: 4851 ldr r0, [pc, #324] ; (8001fec ) + 8001ea8: f006 fc6e bl 8008788 + 8001eac: 4603 mov r3, r0 + 8001eae: b2da uxtb r2, r3 + 8001eb0: 4b50 ldr r3, [pc, #320] ; (8001ff4 ) + 8001eb2: 701a strb r2, [r3, #0] + tmp_float = atof32(&(gps_raw.latitude[2])); //frac part of lat + 8001eb4: 4850 ldr r0, [pc, #320] ; (8001ff8 ) + 8001eb6: f006 fac7 bl 8008448 + 8001eba: 4602 mov r2, r0 + 8001ebc: 4b4f ldr r3, [pc, #316] ; (8001ffc ) + 8001ebe: 601a str r2, [r3, #0] + + tmp_float /= 60.0; //convert ddmm.mmmm to dd.dddddd + 8001ec0: 4b4e ldr r3, [pc, #312] ; (8001ffc ) + 8001ec2: 681b ldr r3, [r3, #0] + 8001ec4: 494e ldr r1, [pc, #312] ; (8002000 ) + 8001ec6: 4618 mov r0, r3 + 8001ec8: f7ff f818 bl 8000efc <__aeabi_fdiv> + 8001ecc: 4603 mov r3, r0 + 8001ece: 461a mov r2, r3 + 8001ed0: 4b4a ldr r3, [pc, #296] ; (8001ffc ) + 8001ed2: 601a str r2, [r3, #0] + tmp_float += tmp_uint8; + 8001ed4: 4b47 ldr r3, [pc, #284] ; (8001ff4 ) + 8001ed6: 781b ldrb r3, [r3, #0] + 8001ed8: 4618 mov r0, r3 + 8001eda: f7fe ff07 bl 8000cec <__aeabi_i2f> + 8001ede: 4602 mov r2, r0 + 8001ee0: 4b46 ldr r3, [pc, #280] ; (8001ffc ) + 8001ee2: 681b ldr r3, [r3, #0] + 8001ee4: 4619 mov r1, r3 + 8001ee6: 4610 mov r0, r2 + 8001ee8: f7fe fe4c bl 8000b84 <__addsf3> + 8001eec: 4603 mov r3, r0 + 8001eee: 461a mov r2, r3 + 8001ef0: 4b42 ldr r3, [pc, #264] ; (8001ffc ) + 8001ef2: 601a str r2, [r3, #0] + + if (gps_raw.ns[0] == 'S') + 8001ef4: 4b3c ldr r3, [pc, #240] ; (8001fe8 ) + 8001ef6: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 + 8001efa: 2b53 cmp r3, #83 ; 0x53 + 8001efc: d110 bne.n 8001f20 + { + gps_num.latitude.in_deg = tmp_float * -1.0; //negative (southern) latitudes + 8001efe: 4b3f ldr r3, [pc, #252] ; (8001ffc ) + 8001f00: 681b ldr r3, [r3, #0] + 8001f02: 4618 mov r0, r3 + 8001f04: f7fe fa98 bl 8000438 <__aeabi_f2d> + 8001f08: 4603 mov r3, r0 + 8001f0a: 460c mov r4, r1 + 8001f0c: 4618 mov r0, r3 + 8001f0e: 4621 mov r1, r4 + 8001f10: f7fe fde2 bl 8000ad8 <__aeabi_d2f> + 8001f14: 4603 mov r3, r0 + 8001f16: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 + 8001f1a: 4a35 ldr r2, [pc, #212] ; (8001ff0 ) + 8001f1c: 6093 str r3, [r2, #8] + 8001f1e: e003 b.n 8001f28 + } + else + { + gps_num.latitude.in_deg = tmp_float; + 8001f20: 4b36 ldr r3, [pc, #216] ; (8001ffc ) + 8001f22: 681b ldr r3, [r3, #0] + 8001f24: 4a32 ldr r2, [pc, #200] ; (8001ff0 ) + 8001f26: 6093 str r3, [r2, #8] + } + + gps_num.latitude.in_rad = gps_num.latitude.in_deg * deg_to_rad; + 8001f28: 4b31 ldr r3, [pc, #196] ; (8001ff0 ) + 8001f2a: 689b ldr r3, [r3, #8] + 8001f2c: 4618 mov r0, r3 + 8001f2e: f7fe fa83 bl 8000438 <__aeabi_f2d> + 8001f32: 4b34 ldr r3, [pc, #208] ; (8002004 ) + 8001f34: cb18 ldmia r3, {r3, r4} + 8001f36: 461a mov r2, r3 + 8001f38: 4623 mov r3, r4 + 8001f3a: f7fe fad5 bl 80004e8 <__aeabi_dmul> + 8001f3e: 4603 mov r3, r0 + 8001f40: 460c mov r4, r1 + 8001f42: 4a2b ldr r2, [pc, #172] ; (8001ff0 ) + 8001f44: e9c2 3404 strd r3, r4, [r2, #16] + + + //Longitude + tmp_char[0] = gps_raw.longitude[0]; + 8001f48: 4b27 ldr r3, [pc, #156] ; (8001fe8 ) + 8001f4a: f893 2025 ldrb.w r2, [r3, #37] ; 0x25 + 8001f4e: 4b27 ldr r3, [pc, #156] ; (8001fec ) + 8001f50: 701a strb r2, [r3, #0] + tmp_char[1] = gps_raw.longitude[1]; + 8001f52: 4b25 ldr r3, [pc, #148] ; (8001fe8 ) + 8001f54: f893 2026 ldrb.w r2, [r3, #38] ; 0x26 + 8001f58: 4b24 ldr r3, [pc, #144] ; (8001fec ) + 8001f5a: 705a strb r2, [r3, #1] + tmp_char[2] = gps_raw.longitude[2]; + 8001f5c: 4b22 ldr r3, [pc, #136] ; (8001fe8 ) + 8001f5e: f893 2027 ldrb.w r2, [r3, #39] ; 0x27 + 8001f62: 4b22 ldr r3, [pc, #136] ; (8001fec ) + 8001f64: 709a strb r2, [r3, #2] + tmp_char[3] = 0; + 8001f66: 4b21 ldr r3, [pc, #132] ; (8001fec ) + 8001f68: 2200 movs r2, #0 + 8001f6a: 70da strb r2, [r3, #3] + tmp_uint8 = (uint8_t)atoi32(&tmp_char[0]); //int part of lon + 8001f6c: 481f ldr r0, [pc, #124] ; (8001fec ) + 8001f6e: f006 fc0b bl 8008788 + 8001f72: 4603 mov r3, r0 + 8001f74: b2da uxtb r2, r3 + 8001f76: 4b1f ldr r3, [pc, #124] ; (8001ff4 ) + 8001f78: 701a strb r2, [r3, #0] + tmp_float = atof32(&(gps_raw.longitude[3])); //frac part of lon + 8001f7a: 4823 ldr r0, [pc, #140] ; (8002008 ) + 8001f7c: f006 fa64 bl 8008448 + 8001f80: 4602 mov r2, r0 + 8001f82: 4b1e ldr r3, [pc, #120] ; (8001ffc ) + 8001f84: 601a str r2, [r3, #0] + + tmp_float /= 60.0; //convert dddmm.mmmm to ddd.dddddd + 8001f86: 4b1d ldr r3, [pc, #116] ; (8001ffc ) + 8001f88: 681b ldr r3, [r3, #0] + 8001f8a: 491d ldr r1, [pc, #116] ; (8002000 ) + 8001f8c: 4618 mov r0, r3 + 8001f8e: f7fe ffb5 bl 8000efc <__aeabi_fdiv> + 8001f92: 4603 mov r3, r0 + 8001f94: 461a mov r2, r3 + 8001f96: 4b19 ldr r3, [pc, #100] ; (8001ffc ) + 8001f98: 601a str r2, [r3, #0] + tmp_float += tmp_uint8; + 8001f9a: 4b16 ldr r3, [pc, #88] ; (8001ff4 ) + 8001f9c: 781b ldrb r3, [r3, #0] + 8001f9e: 4618 mov r0, r3 + 8001fa0: f7fe fea4 bl 8000cec <__aeabi_i2f> + 8001fa4: 4602 mov r2, r0 + 8001fa6: 4b15 ldr r3, [pc, #84] ; (8001ffc ) + 8001fa8: 681b ldr r3, [r3, #0] + 8001faa: 4619 mov r1, r3 + 8001fac: 4610 mov r0, r2 + 8001fae: f7fe fde9 bl 8000b84 <__addsf3> + 8001fb2: 4603 mov r3, r0 + 8001fb4: 461a mov r2, r3 + 8001fb6: 4b11 ldr r3, [pc, #68] ; (8001ffc ) + 8001fb8: 601a str r2, [r3, #0] + + if (gps_raw.ew[0] == 'W') + 8001fba: 4b0b ldr r3, [pc, #44] ; (8001fe8 ) + 8001fbc: f893 3032 ldrb.w r3, [r3, #50] ; 0x32 + 8001fc0: 2b57 cmp r3, #87 ; 0x57 + 8001fc2: d123 bne.n 800200c + { + gps_num.longitude.in_deg = tmp_float * -1.0; //negative (western) longitudes + 8001fc4: 4b0d ldr r3, [pc, #52] ; (8001ffc ) + 8001fc6: 681b ldr r3, [r3, #0] + 8001fc8: 4618 mov r0, r3 + 8001fca: f7fe fa35 bl 8000438 <__aeabi_f2d> + 8001fce: 4603 mov r3, r0 + 8001fd0: 460c mov r4, r1 + 8001fd2: 4618 mov r0, r3 + 8001fd4: 4621 mov r1, r4 + 8001fd6: f7fe fd7f bl 8000ad8 <__aeabi_d2f> + 8001fda: 4603 mov r3, r0 + 8001fdc: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 + 8001fe0: 4a03 ldr r2, [pc, #12] ; (8001ff0 ) + 8001fe2: 6193 str r3, [r2, #24] + 8001fe4: e016 b.n 8002014 + 8001fe6: bf00 nop + 8001fe8: 20000588 .word 0x20000588 + 8001fec: 20000178 .word 0x20000178 + 8001ff0: 20000138 .word 0x20000138 + 8001ff4: 200005f4 .word 0x200005f4 + 8001ff8: 2000059f .word 0x2000059f + 8001ffc: 20000130 .word 0x20000130 + 8002000: 42700000 .word 0x42700000 + 8002004: 0800cf40 .word 0x0800cf40 + 8002008: 200005b0 .word 0x200005b0 + } + else + { + gps_num.longitude.in_deg = tmp_float; + 800200c: 4b2d ldr r3, [pc, #180] ; (80020c4 ) + 800200e: 681b ldr r3, [r3, #0] + 8002010: 4a2d ldr r2, [pc, #180] ; (80020c8 ) + 8002012: 6193 str r3, [r2, #24] + } + + gps_num.longitude.in_rad = gps_num.longitude.in_deg * deg_to_rad; + 8002014: 4b2c ldr r3, [pc, #176] ; (80020c8 ) + 8002016: 699b ldr r3, [r3, #24] + 8002018: 4618 mov r0, r3 + 800201a: f7fe fa0d bl 8000438 <__aeabi_f2d> + 800201e: 4b2b ldr r3, [pc, #172] ; (80020cc ) + 8002020: cb18 ldmia r3, {r3, r4} + 8002022: 461a mov r2, r3 + 8002024: 4623 mov r3, r4 + 8002026: f7fe fa5f bl 80004e8 <__aeabi_dmul> + 800202a: 4603 mov r3, r0 + 800202c: 460c mov r4, r1 + 800202e: 4a26 ldr r2, [pc, #152] ; (80020c8 ) + 8002030: e9c2 3408 strd r3, r4, [r2, #32] + + + //Speed + gps_num.speed = atof32(&(gps_raw.speed[0])) * knots_to_kph; + 8002034: 4826 ldr r0, [pc, #152] ; (80020d0 ) + 8002036: f006 fa07 bl 8008448 + 800203a: 4602 mov r2, r0 + 800203c: 4b25 ldr r3, [pc, #148] ; (80020d4 ) + 800203e: 4619 mov r1, r3 + 8002040: 4610 mov r0, r2 + 8002042: f7fe fea7 bl 8000d94 <__aeabi_fmul> + 8002046: 4603 mov r3, r0 + 8002048: 461a mov r2, r3 + 800204a: 4b1f ldr r3, [pc, #124] ; (80020c8 ) + 800204c: 629a str r2, [r3, #40] ; 0x28 + + //Course + gps_num.course = atof32(&(gps_raw.course[0])); + 800204e: 4822 ldr r0, [pc, #136] ; (80020d8 ) + 8002050: f006 f9fa bl 8008448 + 8002054: 4602 mov r2, r0 + 8002056: 4b1c ldr r3, [pc, #112] ; (80020c8 ) + 8002058: 62da str r2, [r3, #44] ; 0x2c + + //Altitude + gps_num.altitude = atof32(&(gps_raw.altitude[0])); + 800205a: 4820 ldr r0, [pc, #128] ; (80020dc ) + 800205c: f006 f9f4 bl 8008448 + 8002060: 4602 mov r2, r0 + 8002062: 4b19 ldr r3, [pc, #100] ; (80020c8 ) + 8002064: 631a str r2, [r3, #48] ; 0x30 + + //Satellites + gps_num.sat_view = (uint8_t)atoi32(&(gps_raw.sat_view[0])); + 8002066: 481e ldr r0, [pc, #120] ; (80020e0 ) + 8002068: f006 fb8e bl 8008788 + 800206c: 4603 mov r3, r0 + 800206e: b2da uxtb r2, r3 + 8002070: 4b15 ldr r3, [pc, #84] ; (80020c8 ) + 8002072: f883 2034 strb.w r2, [r3, #52] ; 0x34 + gps_num.sat_used = (uint8_t)atoi32(&(gps_raw.sat_used[0])); + 8002076: 481b ldr r0, [pc, #108] ; (80020e4 ) + 8002078: f006 fb86 bl 8008788 + 800207c: 4603 mov r3, r0 + 800207e: b2da uxtb r2, r3 + 8002080: 4b11 ldr r3, [pc, #68] ; (80020c8 ) + 8002082: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + + //Status, Mode, PDOP + if (gps_raw.status[0] == 'A') + 8002086: 4b18 ldr r3, [pc, #96] ; (80020e8 ) + 8002088: f893 3048 ldrb.w r3, [r3, #72] ; 0x48 + 800208c: 2b41 cmp r3, #65 ; 0x41 + 800208e: d104 bne.n 800209a + { + gps_num.status = GPS_DATA_VALID; + 8002090: 4b0d ldr r3, [pc, #52] ; (80020c8 ) + 8002092: 2201 movs r2, #1 + 8002094: f883 2036 strb.w r2, [r3, #54] ; 0x36 + 8002098: e003 b.n 80020a2 + } + else + { + gps_num.status = GPS_DATA_INVALID; + 800209a: 4b0b ldr r3, [pc, #44] ; (80020c8 ) + 800209c: 2200 movs r2, #0 + 800209e: f883 2036 strb.w r2, [r3, #54] ; 0x36 + } + + gps_num.mode = (uint8_t)atoi32(&(gps_raw.mode[0])); + 80020a2: 4812 ldr r0, [pc, #72] ; (80020ec ) + 80020a4: f006 fb70 bl 8008788 + 80020a8: 4603 mov r3, r0 + 80020aa: b2da uxtb r2, r3 + 80020ac: 4b06 ldr r3, [pc, #24] ; (80020c8 ) + 80020ae: f883 2037 strb.w r2, [r3, #55] ; 0x37 + + gps_num.pdop = atof32(&(gps_raw.pdop[0])); + 80020b2: 480f ldr r0, [pc, #60] ; (80020f0 ) + 80020b4: f006 f9c8 bl 8008448 + 80020b8: 4602 mov r2, r0 + 80020ba: 4b03 ldr r3, [pc, #12] ; (80020c8 ) + 80020bc: 639a str r2, [r3, #56] ; 0x38 +} + 80020be: bf00 nop + 80020c0: bd98 pop {r3, r4, r7, pc} + 80020c2: bf00 nop + 80020c4: 20000130 .word 0x20000130 + 80020c8: 20000138 .word 0x20000138 + 80020cc: 0800cf40 .word 0x0800cf40 + 80020d0: 200005be .word 0x200005be + 80020d4: 3fed0e56 .word 0x3fed0e56 + 80020d8: 200005c8 .word 0x200005c8 + 80020dc: 200005d4 .word 0x200005d4 + 80020e0: 200005de .word 0x200005de + 80020e4: 200005e3 .word 0x200005e3 + 80020e8: 20000588 .word 0x20000588 + 80020ec: 200005e8 .word 0x200005e8 + 80020f0: 200005ec .word 0x200005ec + +080020f4 : + + + +//Parse RMC sentence +uint8_t parse_RMC(void) +{ + 80020f4: b580 push {r7, lr} + 80020f6: b082 sub sp, #8 + 80020f8: af00 add r7, sp, #0 + uint8_t comma = 0; + 80020fa: 2300 movs r3, #0 + 80020fc: 71fb strb r3, [r7, #7] + uint8_t sym = 0; + 80020fe: 2300 movs r3, #0 + 8002100: 71bb strb r3, [r7, #6] + uint16_t pos = 0; + 8002102: 2300 movs r3, #0 + 8002104: 80bb strh r3, [r7, #4] + + while (!((nmea_data[pos] == '$') && + 8002106: e002 b.n 800210e + (nmea_data[pos + 3] == 'R') && + (nmea_data[pos + 4] == 'M') && + (nmea_data[pos + 5] == 'C')) && pos < UART_BUF_LEN) //search for start pos + { + pos++; + 8002108: 88bb ldrh r3, [r7, #4] + 800210a: 3301 adds r3, #1 + 800210c: 80bb strh r3, [r7, #4] + while (!((nmea_data[pos] == '$') && + 800210e: 88bb ldrh r3, [r7, #4] + 8002110: 4a63 ldr r2, [pc, #396] ; (80022a0 ) + 8002112: 5cd3 ldrb r3, [r2, r3] + 8002114: 2b24 cmp r3, #36 ; 0x24 + 8002116: d111 bne.n 800213c + (nmea_data[pos + 3] == 'R') && + 8002118: 88bb ldrh r3, [r7, #4] + 800211a: 3303 adds r3, #3 + 800211c: 4a60 ldr r2, [pc, #384] ; (80022a0 ) + 800211e: 5cd3 ldrb r3, [r2, r3] + while (!((nmea_data[pos] == '$') && + 8002120: 2b52 cmp r3, #82 ; 0x52 + 8002122: d10b bne.n 800213c + (nmea_data[pos + 4] == 'M') && + 8002124: 88bb ldrh r3, [r7, #4] + 8002126: 3304 adds r3, #4 + 8002128: 4a5d ldr r2, [pc, #372] ; (80022a0 ) + 800212a: 5cd3 ldrb r3, [r2, r3] + (nmea_data[pos + 3] == 'R') && + 800212c: 2b4d cmp r3, #77 ; 0x4d + 800212e: d105 bne.n 800213c + (nmea_data[pos + 5] == 'C')) && pos < UART_BUF_LEN) //search for start pos + 8002130: 88bb ldrh r3, [r7, #4] + 8002132: 3305 adds r3, #5 + 8002134: 4a5a ldr r2, [pc, #360] ; (80022a0 ) + 8002136: 5cd3 ldrb r3, [r2, r3] + while (!((nmea_data[pos] == '$') && + 8002138: 2b43 cmp r3, #67 ; 0x43 + 800213a: d003 beq.n 8002144 + (nmea_data[pos + 5] == 'C')) && pos < UART_BUF_LEN) //search for start pos + 800213c: 88bb ldrh r3, [r7, #4] + 800213e: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8002142: d3e1 bcc.n 8002108 + } + + if(nmea_checksum(pos) == 0) + 8002144: 88bb ldrh r3, [r7, #4] + 8002146: 4618 mov r0, r3 + 8002148: f000 fa02 bl 8002550 + 800214c: 4603 mov r3, r0 + 800214e: 2b00 cmp r3, #0 + 8002150: d101 bne.n 8002156 + { + return 0; //checksum error + 8002152: 2300 movs r3, #0 + 8002154: e0a0 b.n 8002298 + } + + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + 8002156: 88bb ldrh r3, [r7, #4] + 8002158: 3306 adds r3, #6 + 800215a: 807b strh r3, [r7, #2] + 800215c: e096 b.n 800228c + { + if (nmea_data[i] == '*') return 1; //end of the sentence + 800215e: 887b ldrh r3, [r7, #2] + 8002160: 4a4f ldr r2, [pc, #316] ; (80022a0 ) + 8002162: 5cd3 ldrb r3, [r2, r3] + 8002164: 2b2a cmp r3, #42 ; 0x2a + 8002166: d101 bne.n 800216c + 8002168: 2301 movs r3, #1 + 800216a: e095 b.n 8002298 + + if (nmea_data[i] == ',') + 800216c: 887b ldrh r3, [r7, #2] + 800216e: 4a4c ldr r2, [pc, #304] ; (80022a0 ) + 8002170: 5cd3 ldrb r3, [r2, r3] + 8002172: 2b2c cmp r3, #44 ; 0x2c + 8002174: d105 bne.n 8002182 + { + comma++; //increase comma counter + 8002176: 79fb ldrb r3, [r7, #7] + 8002178: 3301 adds r3, #1 + 800217a: 71fb strb r3, [r7, #7] + sym = 0; + 800217c: 2300 movs r3, #0 + 800217e: 71bb strb r3, [r7, #6] + 8002180: e081 b.n 8002286 + } + else + { + switch (comma) //surfing through RMC data fields + 8002182: 79fb ldrb r3, [r7, #7] + 8002184: 3b01 subs r3, #1 + 8002186: 2b08 cmp r3, #8 + 8002188: d87c bhi.n 8002284 + 800218a: a201 add r2, pc, #4 ; (adr r2, 8002190 ) + 800218c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002190: 080021b5 .word 0x080021b5 + 8002194: 080021c9 .word 0x080021c9 + 8002198: 080021e1 .word 0x080021e1 + 800219c: 080021f7 .word 0x080021f7 + 80021a0: 0800220f .word 0x0800220f + 80021a4: 08002227 .word 0x08002227 + 80021a8: 0800223f .word 0x0800223f + 80021ac: 08002257 .word 0x08002257 + 80021b0: 0800226f .word 0x0800226f + { + case 1: + gps_raw.time[sym++] = nmea_data[i]; + 80021b4: 887a ldrh r2, [r7, #2] + 80021b6: 79bb ldrb r3, [r7, #6] + 80021b8: 1c59 adds r1, r3, #1 + 80021ba: 71b9 strb r1, [r7, #6] + 80021bc: 4619 mov r1, r3 + 80021be: 4b38 ldr r3, [pc, #224] ; (80022a0 ) + 80021c0: 5c9a ldrb r2, [r3, r2] + 80021c2: 4b38 ldr r3, [pc, #224] ; (80022a4 ) + 80021c4: 545a strb r2, [r3, r1] + break; + 80021c6: e05e b.n 8002286 + case 2: + gps_raw.status[sym++] = nmea_data[i]; + 80021c8: 887a ldrh r2, [r7, #2] + 80021ca: 79bb ldrb r3, [r7, #6] + 80021cc: 1c59 adds r1, r3, #1 + 80021ce: 71b9 strb r1, [r7, #6] + 80021d0: 4619 mov r1, r3 + 80021d2: 4b33 ldr r3, [pc, #204] ; (80022a0 ) + 80021d4: 5c9a ldrb r2, [r3, r2] + 80021d6: 4b33 ldr r3, [pc, #204] ; (80022a4 ) + 80021d8: 440b add r3, r1 + 80021da: f883 2048 strb.w r2, [r3, #72] ; 0x48 + break; + 80021de: e052 b.n 8002286 + case 3: + gps_raw.latitude[sym++] = nmea_data[i]; + 80021e0: 887a ldrh r2, [r7, #2] + 80021e2: 79bb ldrb r3, [r7, #6] + 80021e4: 1c59 adds r1, r3, #1 + 80021e6: 71b9 strb r1, [r7, #6] + 80021e8: 4619 mov r1, r3 + 80021ea: 4b2d ldr r3, [pc, #180] ; (80022a0 ) + 80021ec: 5c9a ldrb r2, [r3, r2] + 80021ee: 4b2d ldr r3, [pc, #180] ; (80022a4 ) + 80021f0: 440b add r3, r1 + 80021f2: 755a strb r2, [r3, #21] + break; + 80021f4: e047 b.n 8002286 + case 4: + gps_raw.ns[sym++] = nmea_data[i]; + 80021f6: 887a ldrh r2, [r7, #2] + 80021f8: 79bb ldrb r3, [r7, #6] + 80021fa: 1c59 adds r1, r3, #1 + 80021fc: 71b9 strb r1, [r7, #6] + 80021fe: 4619 mov r1, r3 + 8002200: 4b27 ldr r3, [pc, #156] ; (80022a0 ) + 8002202: 5c9a ldrb r2, [r3, r2] + 8002204: 4b27 ldr r3, [pc, #156] ; (80022a4 ) + 8002206: 440b add r3, r1 + 8002208: f883 2021 strb.w r2, [r3, #33] ; 0x21 + break; + 800220c: e03b b.n 8002286 + case 5: + gps_raw.longitude[sym++] = nmea_data[i]; + 800220e: 887a ldrh r2, [r7, #2] + 8002210: 79bb ldrb r3, [r7, #6] + 8002212: 1c59 adds r1, r3, #1 + 8002214: 71b9 strb r1, [r7, #6] + 8002216: 4619 mov r1, r3 + 8002218: 4b21 ldr r3, [pc, #132] ; (80022a0 ) + 800221a: 5c9a ldrb r2, [r3, r2] + 800221c: 4b21 ldr r3, [pc, #132] ; (80022a4 ) + 800221e: 440b add r3, r1 + 8002220: f883 2025 strb.w r2, [r3, #37] ; 0x25 + break; + 8002224: e02f b.n 8002286 + case 6: + gps_raw.ew[sym++] = nmea_data[i]; + 8002226: 887a ldrh r2, [r7, #2] + 8002228: 79bb ldrb r3, [r7, #6] + 800222a: 1c59 adds r1, r3, #1 + 800222c: 71b9 strb r1, [r7, #6] + 800222e: 4619 mov r1, r3 + 8002230: 4b1b ldr r3, [pc, #108] ; (80022a0 ) + 8002232: 5c9a ldrb r2, [r3, r2] + 8002234: 4b1b ldr r3, [pc, #108] ; (80022a4 ) + 8002236: 440b add r3, r1 + 8002238: f883 2032 strb.w r2, [r3, #50] ; 0x32 + break; + 800223c: e023 b.n 8002286 + case 7: + gps_raw.speed[sym++] = nmea_data[i]; + 800223e: 887a ldrh r2, [r7, #2] + 8002240: 79bb ldrb r3, [r7, #6] + 8002242: 1c59 adds r1, r3, #1 + 8002244: 71b9 strb r1, [r7, #6] + 8002246: 4619 mov r1, r3 + 8002248: 4b15 ldr r3, [pc, #84] ; (80022a0 ) + 800224a: 5c9a ldrb r2, [r3, r2] + 800224c: 4b15 ldr r3, [pc, #84] ; (80022a4 ) + 800224e: 440b add r3, r1 + 8002250: f883 2036 strb.w r2, [r3, #54] ; 0x36 + break; + 8002254: e017 b.n 8002286 + case 8: + gps_raw.course[sym++] = nmea_data[i]; + 8002256: 887a ldrh r2, [r7, #2] + 8002258: 79bb ldrb r3, [r7, #6] + 800225a: 1c59 adds r1, r3, #1 + 800225c: 71b9 strb r1, [r7, #6] + 800225e: 4619 mov r1, r3 + 8002260: 4b0f ldr r3, [pc, #60] ; (80022a0 ) + 8002262: 5c9a ldrb r2, [r3, r2] + 8002264: 4b0f ldr r3, [pc, #60] ; (80022a4 ) + 8002266: 440b add r3, r1 + 8002268: f883 2040 strb.w r2, [r3, #64] ; 0x40 + break; + 800226c: e00b b.n 8002286 + case 9: + gps_raw.date[sym++] = nmea_data[i]; + 800226e: 887a ldrh r2, [r7, #2] + 8002270: 79bb ldrb r3, [r7, #6] + 8002272: 1c59 adds r1, r3, #1 + 8002274: 71b9 strb r1, [r7, #6] + 8002276: 4619 mov r1, r3 + 8002278: 4b09 ldr r3, [pc, #36] ; (80022a0 ) + 800227a: 5c9a ldrb r2, [r3, r2] + 800227c: 4b09 ldr r3, [pc, #36] ; (80022a4 ) + 800227e: 440b add r3, r1 + 8002280: 731a strb r2, [r3, #12] + break; + 8002282: e000 b.n 8002286 + default: + break; + 8002284: bf00 nop + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + 8002286: 887b ldrh r3, [r7, #2] + 8002288: 3301 adds r3, #1 + 800228a: 807b strh r3, [r7, #2] + 800228c: 887b ldrh r3, [r7, #2] + 800228e: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8002292: f4ff af64 bcc.w 800215e + } + } + } + return 1; + 8002296: 2301 movs r3, #1 +} + 8002298: 4618 mov r0, r3 + 800229a: 3708 adds r7, #8 + 800229c: 46bd mov sp, r7 + 800229e: bd80 pop {r7, pc} + 80022a0: 20000188 .word 0x20000188 + 80022a4: 20000588 .word 0x20000588 + +080022a8 : + + + +//Parse GGA sentence +uint8_t parse_GGA(void) +{ + 80022a8: b580 push {r7, lr} + 80022aa: b082 sub sp, #8 + 80022ac: af00 add r7, sp, #0 + uint8_t comma = 0; + 80022ae: 2300 movs r3, #0 + 80022b0: 71fb strb r3, [r7, #7] + uint8_t sym = 0; + 80022b2: 2300 movs r3, #0 + 80022b4: 71bb strb r3, [r7, #6] + uint16_t pos = 0; + 80022b6: 2300 movs r3, #0 + 80022b8: 80bb strh r3, [r7, #4] + + while (!((nmea_data[pos] == '$') && + 80022ba: e002 b.n 80022c2 + (nmea_data[pos + 3] == 'G') && + (nmea_data[pos + 4] == 'G') && + (nmea_data[pos + 5] == 'A')) && pos < UART_BUF_LEN) //search for start pos + { + pos++; + 80022bc: 88bb ldrh r3, [r7, #4] + 80022be: 3301 adds r3, #1 + 80022c0: 80bb strh r3, [r7, #4] + while (!((nmea_data[pos] == '$') && + 80022c2: 88bb ldrh r3, [r7, #4] + 80022c4: 4a31 ldr r2, [pc, #196] ; (800238c ) + 80022c6: 5cd3 ldrb r3, [r2, r3] + 80022c8: 2b24 cmp r3, #36 ; 0x24 + 80022ca: d111 bne.n 80022f0 + (nmea_data[pos + 3] == 'G') && + 80022cc: 88bb ldrh r3, [r7, #4] + 80022ce: 3303 adds r3, #3 + 80022d0: 4a2e ldr r2, [pc, #184] ; (800238c ) + 80022d2: 5cd3 ldrb r3, [r2, r3] + while (!((nmea_data[pos] == '$') && + 80022d4: 2b47 cmp r3, #71 ; 0x47 + 80022d6: d10b bne.n 80022f0 + (nmea_data[pos + 4] == 'G') && + 80022d8: 88bb ldrh r3, [r7, #4] + 80022da: 3304 adds r3, #4 + 80022dc: 4a2b ldr r2, [pc, #172] ; (800238c ) + 80022de: 5cd3 ldrb r3, [r2, r3] + (nmea_data[pos + 3] == 'G') && + 80022e0: 2b47 cmp r3, #71 ; 0x47 + 80022e2: d105 bne.n 80022f0 + (nmea_data[pos + 5] == 'A')) && pos < UART_BUF_LEN) //search for start pos + 80022e4: 88bb ldrh r3, [r7, #4] + 80022e6: 3305 adds r3, #5 + 80022e8: 4a28 ldr r2, [pc, #160] ; (800238c ) + 80022ea: 5cd3 ldrb r3, [r2, r3] + while (!((nmea_data[pos] == '$') && + 80022ec: 2b41 cmp r3, #65 ; 0x41 + 80022ee: d003 beq.n 80022f8 + (nmea_data[pos + 5] == 'A')) && pos < UART_BUF_LEN) //search for start pos + 80022f0: 88bb ldrh r3, [r7, #4] + 80022f2: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80022f6: d3e1 bcc.n 80022bc + } + + if(nmea_checksum(pos) == 0) + 80022f8: 88bb ldrh r3, [r7, #4] + 80022fa: 4618 mov r0, r3 + 80022fc: f000 f928 bl 8002550 + 8002300: 4603 mov r3, r0 + 8002302: 2b00 cmp r3, #0 + 8002304: d101 bne.n 800230a + { + return 0; //checksum error + 8002306: 2300 movs r3, #0 + 8002308: e03b b.n 8002382 + } + + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + 800230a: 88bb ldrh r3, [r7, #4] + 800230c: 3306 adds r3, #6 + 800230e: 807b strh r3, [r7, #2] + 8002310: e032 b.n 8002378 + { + if (nmea_data[i] == '*') return 1; //end of the sentence + 8002312: 887b ldrh r3, [r7, #2] + 8002314: 4a1d ldr r2, [pc, #116] ; (800238c ) + 8002316: 5cd3 ldrb r3, [r2, r3] + 8002318: 2b2a cmp r3, #42 ; 0x2a + 800231a: d101 bne.n 8002320 + 800231c: 2301 movs r3, #1 + 800231e: e030 b.n 8002382 + + if (nmea_data[i] == ',') + 8002320: 887b ldrh r3, [r7, #2] + 8002322: 4a1a ldr r2, [pc, #104] ; (800238c ) + 8002324: 5cd3 ldrb r3, [r2, r3] + 8002326: 2b2c cmp r3, #44 ; 0x2c + 8002328: d105 bne.n 8002336 + { + comma++; //increase comma counter + 800232a: 79fb ldrb r3, [r7, #7] + 800232c: 3301 adds r3, #1 + 800232e: 71fb strb r3, [r7, #7] + sym = 0; + 8002330: 2300 movs r3, #0 + 8002332: 71bb strb r3, [r7, #6] + 8002334: e01d b.n 8002372 + } + else + { + switch (comma) //surfing through GGA data fields + 8002336: 79fb ldrb r3, [r7, #7] + 8002338: 2b07 cmp r3, #7 + 800233a: d002 beq.n 8002342 + 800233c: 2b09 cmp r3, #9 + 800233e: d00c beq.n 800235a + break; + case 9: + gps_raw.altitude[sym++] = nmea_data[i]; + break; + default: + break; + 8002340: e017 b.n 8002372 + gps_raw.sat_used[sym++] = nmea_data[i]; + 8002342: 887a ldrh r2, [r7, #2] + 8002344: 79bb ldrb r3, [r7, #6] + 8002346: 1c59 adds r1, r3, #1 + 8002348: 71b9 strb r1, [r7, #6] + 800234a: 4619 mov r1, r3 + 800234c: 4b0f ldr r3, [pc, #60] ; (800238c ) + 800234e: 5c9a ldrb r2, [r3, r2] + 8002350: 4b0f ldr r3, [pc, #60] ; (8002390 ) + 8002352: 440b add r3, r1 + 8002354: f883 205b strb.w r2, [r3, #91] ; 0x5b + break; + 8002358: e00b b.n 8002372 + gps_raw.altitude[sym++] = nmea_data[i]; + 800235a: 887a ldrh r2, [r7, #2] + 800235c: 79bb ldrb r3, [r7, #6] + 800235e: 1c59 adds r1, r3, #1 + 8002360: 71b9 strb r1, [r7, #6] + 8002362: 4619 mov r1, r3 + 8002364: 4b09 ldr r3, [pc, #36] ; (800238c ) + 8002366: 5c9a ldrb r2, [r3, r2] + 8002368: 4b09 ldr r3, [pc, #36] ; (8002390 ) + 800236a: 440b add r3, r1 + 800236c: f883 204c strb.w r2, [r3, #76] ; 0x4c + break; + 8002370: bf00 nop + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + 8002372: 887b ldrh r3, [r7, #2] + 8002374: 3301 adds r3, #1 + 8002376: 807b strh r3, [r7, #2] + 8002378: 887b ldrh r3, [r7, #2] + 800237a: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800237e: d3c8 bcc.n 8002312 + } + } + } + return 1; + 8002380: 2301 movs r3, #1 +} + 8002382: 4618 mov r0, r3 + 8002384: 3708 adds r7, #8 + 8002386: 46bd mov sp, r7 + 8002388: bd80 pop {r7, pc} + 800238a: bf00 nop + 800238c: 20000188 .word 0x20000188 + 8002390: 20000588 .word 0x20000588 + +08002394 : + + + +//Parse GSA sentence +uint8_t parse_GSA(void) +{ + 8002394: b580 push {r7, lr} + 8002396: b082 sub sp, #8 + 8002398: af00 add r7, sp, #0 + uint8_t comma = 0; + 800239a: 2300 movs r3, #0 + 800239c: 71fb strb r3, [r7, #7] + uint8_t sym = 0; + 800239e: 2300 movs r3, #0 + 80023a0: 71bb strb r3, [r7, #6] + uint16_t pos = 0; + 80023a2: 2300 movs r3, #0 + 80023a4: 80bb strh r3, [r7, #4] + + while (!((nmea_data[pos] == '$') && + 80023a6: e002 b.n 80023ae + (nmea_data[pos + 3] == 'G') && + (nmea_data[pos + 4] == 'S') && + (nmea_data[pos + 5] == 'A')) && pos < UART_BUF_LEN) //search for start pos + { + pos++; + 80023a8: 88bb ldrh r3, [r7, #4] + 80023aa: 3301 adds r3, #1 + 80023ac: 80bb strh r3, [r7, #4] + while (!((nmea_data[pos] == '$') && + 80023ae: 88bb ldrh r3, [r7, #4] + 80023b0: 4a31 ldr r2, [pc, #196] ; (8002478 ) + 80023b2: 5cd3 ldrb r3, [r2, r3] + 80023b4: 2b24 cmp r3, #36 ; 0x24 + 80023b6: d111 bne.n 80023dc + (nmea_data[pos + 3] == 'G') && + 80023b8: 88bb ldrh r3, [r7, #4] + 80023ba: 3303 adds r3, #3 + 80023bc: 4a2e ldr r2, [pc, #184] ; (8002478 ) + 80023be: 5cd3 ldrb r3, [r2, r3] + while (!((nmea_data[pos] == '$') && + 80023c0: 2b47 cmp r3, #71 ; 0x47 + 80023c2: d10b bne.n 80023dc + (nmea_data[pos + 4] == 'S') && + 80023c4: 88bb ldrh r3, [r7, #4] + 80023c6: 3304 adds r3, #4 + 80023c8: 4a2b ldr r2, [pc, #172] ; (8002478 ) + 80023ca: 5cd3 ldrb r3, [r2, r3] + (nmea_data[pos + 3] == 'G') && + 80023cc: 2b53 cmp r3, #83 ; 0x53 + 80023ce: d105 bne.n 80023dc + (nmea_data[pos + 5] == 'A')) && pos < UART_BUF_LEN) //search for start pos + 80023d0: 88bb ldrh r3, [r7, #4] + 80023d2: 3305 adds r3, #5 + 80023d4: 4a28 ldr r2, [pc, #160] ; (8002478 ) + 80023d6: 5cd3 ldrb r3, [r2, r3] + while (!((nmea_data[pos] == '$') && + 80023d8: 2b41 cmp r3, #65 ; 0x41 + 80023da: d003 beq.n 80023e4 + (nmea_data[pos + 5] == 'A')) && pos < UART_BUF_LEN) //search for start pos + 80023dc: 88bb ldrh r3, [r7, #4] + 80023de: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80023e2: d3e1 bcc.n 80023a8 + } + + if(nmea_checksum(pos) == 0) + 80023e4: 88bb ldrh r3, [r7, #4] + 80023e6: 4618 mov r0, r3 + 80023e8: f000 f8b2 bl 8002550 + 80023ec: 4603 mov r3, r0 + 80023ee: 2b00 cmp r3, #0 + 80023f0: d101 bne.n 80023f6 + { + return 0; //checksum error + 80023f2: 2300 movs r3, #0 + 80023f4: e03b b.n 800246e + } + + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + 80023f6: 88bb ldrh r3, [r7, #4] + 80023f8: 3306 adds r3, #6 + 80023fa: 807b strh r3, [r7, #2] + 80023fc: e032 b.n 8002464 + { + if (nmea_data[i] == '*') return 1; //end of the sentence + 80023fe: 887b ldrh r3, [r7, #2] + 8002400: 4a1d ldr r2, [pc, #116] ; (8002478 ) + 8002402: 5cd3 ldrb r3, [r2, r3] + 8002404: 2b2a cmp r3, #42 ; 0x2a + 8002406: d101 bne.n 800240c + 8002408: 2301 movs r3, #1 + 800240a: e030 b.n 800246e + + if (nmea_data[i] == ',') + 800240c: 887b ldrh r3, [r7, #2] + 800240e: 4a1a ldr r2, [pc, #104] ; (8002478 ) + 8002410: 5cd3 ldrb r3, [r2, r3] + 8002412: 2b2c cmp r3, #44 ; 0x2c + 8002414: d105 bne.n 8002422 + { + comma++; //increase comma counter + 8002416: 79fb ldrb r3, [r7, #7] + 8002418: 3301 adds r3, #1 + 800241a: 71fb strb r3, [r7, #7] + sym = 0; + 800241c: 2300 movs r3, #0 + 800241e: 71bb strb r3, [r7, #6] + 8002420: e01d b.n 800245e + } + else + { + switch (comma) //surfing through GSA data fields + 8002422: 79fb ldrb r3, [r7, #7] + 8002424: 2b02 cmp r3, #2 + 8002426: d002 beq.n 800242e + 8002428: 2b0f cmp r3, #15 + 800242a: d00c beq.n 8002446 + break; + case 15: + gps_raw.pdop[sym++] = nmea_data[i]; + break; + default: + break; + 800242c: e017 b.n 800245e + gps_raw.mode[sym++] = nmea_data[i]; + 800242e: 887a ldrh r2, [r7, #2] + 8002430: 79bb ldrb r3, [r7, #6] + 8002432: 1c59 adds r1, r3, #1 + 8002434: 71b9 strb r1, [r7, #6] + 8002436: 4619 mov r1, r3 + 8002438: 4b0f ldr r3, [pc, #60] ; (8002478 ) + 800243a: 5c9a ldrb r2, [r3, r2] + 800243c: 4b0f ldr r3, [pc, #60] ; (800247c ) + 800243e: 440b add r3, r1 + 8002440: f883 2060 strb.w r2, [r3, #96] ; 0x60 + break; + 8002444: e00b b.n 800245e + gps_raw.pdop[sym++] = nmea_data[i]; + 8002446: 887a ldrh r2, [r7, #2] + 8002448: 79bb ldrb r3, [r7, #6] + 800244a: 1c59 adds r1, r3, #1 + 800244c: 71b9 strb r1, [r7, #6] + 800244e: 4619 mov r1, r3 + 8002450: 4b09 ldr r3, [pc, #36] ; (8002478 ) + 8002452: 5c9a ldrb r2, [r3, r2] + 8002454: 4b09 ldr r3, [pc, #36] ; (800247c ) + 8002456: 440b add r3, r1 + 8002458: f883 2064 strb.w r2, [r3, #100] ; 0x64 + break; + 800245c: bf00 nop + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + 800245e: 887b ldrh r3, [r7, #2] + 8002460: 3301 adds r3, #1 + 8002462: 807b strh r3, [r7, #2] + 8002464: 887b ldrh r3, [r7, #2] + 8002466: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800246a: d3c8 bcc.n 80023fe + } + } + } + return 1; + 800246c: 2301 movs r3, #1 +} + 800246e: 4618 mov r0, r3 + 8002470: 3708 adds r7, #8 + 8002472: 46bd mov sp, r7 + 8002474: bd80 pop {r7, pc} + 8002476: bf00 nop + 8002478: 20000188 .word 0x20000188 + 800247c: 20000588 .word 0x20000588 + +08002480 : + + + +//Parse GSV sentence +uint8_t parse_GSV(void) +{ + 8002480: b580 push {r7, lr} + 8002482: b082 sub sp, #8 + 8002484: af00 add r7, sp, #0 + uint8_t comma = 0; + 8002486: 2300 movs r3, #0 + 8002488: 71fb strb r3, [r7, #7] + uint8_t sym = 0; + 800248a: 2300 movs r3, #0 + 800248c: 71bb strb r3, [r7, #6] + uint16_t pos = 0; + 800248e: 2300 movs r3, #0 + 8002490: 80bb strh r3, [r7, #4] + + while (!((nmea_data[pos] == '$') && + 8002492: e002 b.n 800249a + (nmea_data[pos + 3] == 'G') && + (nmea_data[pos + 4] == 'S') && + (nmea_data[pos + 5] == 'V')) && pos < UART_BUF_LEN) //search for start pos + { + pos++; + 8002494: 88bb ldrh r3, [r7, #4] + 8002496: 3301 adds r3, #1 + 8002498: 80bb strh r3, [r7, #4] + while (!((nmea_data[pos] == '$') && + 800249a: 88bb ldrh r3, [r7, #4] + 800249c: 4a2a ldr r2, [pc, #168] ; (8002548 ) + 800249e: 5cd3 ldrb r3, [r2, r3] + 80024a0: 2b24 cmp r3, #36 ; 0x24 + 80024a2: d111 bne.n 80024c8 + (nmea_data[pos + 3] == 'G') && + 80024a4: 88bb ldrh r3, [r7, #4] + 80024a6: 3303 adds r3, #3 + 80024a8: 4a27 ldr r2, [pc, #156] ; (8002548 ) + 80024aa: 5cd3 ldrb r3, [r2, r3] + while (!((nmea_data[pos] == '$') && + 80024ac: 2b47 cmp r3, #71 ; 0x47 + 80024ae: d10b bne.n 80024c8 + (nmea_data[pos + 4] == 'S') && + 80024b0: 88bb ldrh r3, [r7, #4] + 80024b2: 3304 adds r3, #4 + 80024b4: 4a24 ldr r2, [pc, #144] ; (8002548 ) + 80024b6: 5cd3 ldrb r3, [r2, r3] + (nmea_data[pos + 3] == 'G') && + 80024b8: 2b53 cmp r3, #83 ; 0x53 + 80024ba: d105 bne.n 80024c8 + (nmea_data[pos + 5] == 'V')) && pos < UART_BUF_LEN) //search for start pos + 80024bc: 88bb ldrh r3, [r7, #4] + 80024be: 3305 adds r3, #5 + 80024c0: 4a21 ldr r2, [pc, #132] ; (8002548 ) + 80024c2: 5cd3 ldrb r3, [r2, r3] + while (!((nmea_data[pos] == '$') && + 80024c4: 2b56 cmp r3, #86 ; 0x56 + 80024c6: d003 beq.n 80024d0 + (nmea_data[pos + 5] == 'V')) && pos < UART_BUF_LEN) //search for start pos + 80024c8: 88bb ldrh r3, [r7, #4] + 80024ca: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80024ce: d3e1 bcc.n 8002494 + } + + if(nmea_checksum(pos) == 0) + 80024d0: 88bb ldrh r3, [r7, #4] + 80024d2: 4618 mov r0, r3 + 80024d4: f000 f83c bl 8002550 + 80024d8: 4603 mov r3, r0 + 80024da: 2b00 cmp r3, #0 + 80024dc: d101 bne.n 80024e2 + { + return 0; //checksum error + 80024de: 2300 movs r3, #0 + 80024e0: e02d b.n 800253e + } + + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + 80024e2: 88bb ldrh r3, [r7, #4] + 80024e4: 3306 adds r3, #6 + 80024e6: 807b strh r3, [r7, #2] + 80024e8: e024 b.n 8002534 + { + if (nmea_data[i] == '*') return 1; //end of the sentence + 80024ea: 887b ldrh r3, [r7, #2] + 80024ec: 4a16 ldr r2, [pc, #88] ; (8002548 ) + 80024ee: 5cd3 ldrb r3, [r2, r3] + 80024f0: 2b2a cmp r3, #42 ; 0x2a + 80024f2: d101 bne.n 80024f8 + 80024f4: 2301 movs r3, #1 + 80024f6: e022 b.n 800253e + + if (nmea_data[i] == ',') + 80024f8: 887b ldrh r3, [r7, #2] + 80024fa: 4a13 ldr r2, [pc, #76] ; (8002548 ) + 80024fc: 5cd3 ldrb r3, [r2, r3] + 80024fe: 2b2c cmp r3, #44 ; 0x2c + 8002500: d105 bne.n 800250e + { + comma++; //increase comma counter + 8002502: 79fb ldrb r3, [r7, #7] + 8002504: 3301 adds r3, #1 + 8002506: 71fb strb r3, [r7, #7] + sym = 0; + 8002508: 2300 movs r3, #0 + 800250a: 71bb strb r3, [r7, #6] + 800250c: e00f b.n 800252e + } + else + { + switch (comma) //surfing through GSV data fields + 800250e: 79fb ldrb r3, [r7, #7] + 8002510: 2b03 cmp r3, #3 + 8002512: d000 beq.n 8002516 + { + case 3: + gps_raw.sat_view[sym++] = nmea_data[i]; + break; + default: + break; + 8002514: e00b b.n 800252e + gps_raw.sat_view[sym++] = nmea_data[i]; + 8002516: 887a ldrh r2, [r7, #2] + 8002518: 79bb ldrb r3, [r7, #6] + 800251a: 1c59 adds r1, r3, #1 + 800251c: 71b9 strb r1, [r7, #6] + 800251e: 4619 mov r1, r3 + 8002520: 4b09 ldr r3, [pc, #36] ; (8002548 ) + 8002522: 5c9a ldrb r2, [r3, r2] + 8002524: 4b09 ldr r3, [pc, #36] ; (800254c ) + 8002526: 440b add r3, r1 + 8002528: f883 2056 strb.w r2, [r3, #86] ; 0x56 + break; + 800252c: bf00 nop + for (uint16_t i = pos + 6; i < UART_BUF_LEN ; i++) //i starts from the symbol right after "$GPRMC" string + 800252e: 887b ldrh r3, [r7, #2] + 8002530: 3301 adds r3, #1 + 8002532: 807b strh r3, [r7, #2] + 8002534: 887b ldrh r3, [r7, #2] + 8002536: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800253a: d3d6 bcc.n 80024ea + } + } + } + return 1; + 800253c: 2301 movs r3, #1 +} + 800253e: 4618 mov r0, r3 + 8002540: 3708 adds r7, #8 + 8002542: 46bd mov sp, r7 + 8002544: bd80 pop {r7, pc} + 8002546: bf00 nop + 8002548: 20000188 .word 0x20000188 + 800254c: 20000588 .word 0x20000588 + +08002550 : + + + +//NMEA checksum +uint8_t nmea_checksum(uint16_t pos) +{ + 8002550: b480 push {r7} + 8002552: b085 sub sp, #20 + 8002554: af00 add r7, sp, #0 + 8002556: 4603 mov r3, r0 + 8002558: 80fb strh r3, [r7, #6] + uint8_t CheckSum = 0; + 800255a: 2300 movs r3, #0 + 800255c: 73fb strb r3, [r7, #15] + uint8_t MessageCheckSum = 0; + 800255e: 2300 movs r3, #0 + 8002560: 73bb strb r3, [r7, #14] + + pos++; //pick up symbol right after $ + 8002562: 88fb ldrh r3, [r7, #6] + 8002564: 3301 adds r3, #1 + 8002566: 80fb strh r3, [r7, #6] + while (nmea_data[pos] != '*') + 8002568: e00e b.n 8002588 + { + CheckSum ^= nmea_data[pos]; + 800256a: 88fb ldrh r3, [r7, #6] + 800256c: 4a27 ldr r2, [pc, #156] ; (800260c ) + 800256e: 5cd2 ldrb r2, [r2, r3] + 8002570: 7bfb ldrb r3, [r7, #15] + 8002572: 4053 eors r3, r2 + 8002574: 73fb strb r3, [r7, #15] + if (++pos >= UART_BUF_LEN) return 0; //check sum not found + 8002576: 88fb ldrh r3, [r7, #6] + 8002578: 3301 adds r3, #1 + 800257a: 80fb strh r3, [r7, #6] + 800257c: 88fb ldrh r3, [r7, #6] + 800257e: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8002582: d301 bcc.n 8002588 + 8002584: 2300 movs r3, #0 + 8002586: e03b b.n 8002600 + while (nmea_data[pos] != '*') + 8002588: 88fb ldrh r3, [r7, #6] + 800258a: 4a20 ldr r2, [pc, #128] ; (800260c ) + 800258c: 5cd3 ldrb r3, [r2, r3] + 800258e: 2b2a cmp r3, #42 ; 0x2a + 8002590: d1eb bne.n 800256a + } + + if (nmea_data[++pos] > 0x40) + 8002592: 88fb ldrh r3, [r7, #6] + 8002594: 3301 adds r3, #1 + 8002596: 80fb strh r3, [r7, #6] + 8002598: 88fb ldrh r3, [r7, #6] + 800259a: 4a1c ldr r2, [pc, #112] ; (800260c ) + 800259c: 5cd3 ldrb r3, [r2, r3] + 800259e: 2b40 cmp r3, #64 ; 0x40 + 80025a0: d907 bls.n 80025b2 + { + MessageCheckSum = (nmea_data[pos] - 0x37) << 4; //ascii hex to number + 80025a2: 88fb ldrh r3, [r7, #6] + 80025a4: 4a19 ldr r2, [pc, #100] ; (800260c ) + 80025a6: 5cd3 ldrb r3, [r2, r3] + 80025a8: 3b37 subs r3, #55 ; 0x37 + 80025aa: b2db uxtb r3, r3 + 80025ac: 011b lsls r3, r3, #4 + 80025ae: 73bb strb r3, [r7, #14] + 80025b0: e006 b.n 80025c0 + } + else + { + MessageCheckSum = (nmea_data[pos] - 0x30) << 4; + 80025b2: 88fb ldrh r3, [r7, #6] + 80025b4: 4a15 ldr r2, [pc, #84] ; (800260c ) + 80025b6: 5cd3 ldrb r3, [r2, r3] + 80025b8: 3b30 subs r3, #48 ; 0x30 + 80025ba: b2db uxtb r3, r3 + 80025bc: 011b lsls r3, r3, #4 + 80025be: 73bb strb r3, [r7, #14] + } + + if (nmea_data[++pos] > 0x40) + 80025c0: 88fb ldrh r3, [r7, #6] + 80025c2: 3301 adds r3, #1 + 80025c4: 80fb strh r3, [r7, #6] + 80025c6: 88fb ldrh r3, [r7, #6] + 80025c8: 4a10 ldr r2, [pc, #64] ; (800260c ) + 80025ca: 5cd3 ldrb r3, [r2, r3] + 80025cc: 2b40 cmp r3, #64 ; 0x40 + 80025ce: d908 bls.n 80025e2 + { + MessageCheckSum += (nmea_data[pos] - 0x37); //ascii hex to number + 80025d0: 88fb ldrh r3, [r7, #6] + 80025d2: 4a0e ldr r2, [pc, #56] ; (800260c ) + 80025d4: 5cd2 ldrb r2, [r2, r3] + 80025d6: 7bbb ldrb r3, [r7, #14] + 80025d8: 4413 add r3, r2 + 80025da: b2db uxtb r3, r3 + 80025dc: 3b37 subs r3, #55 ; 0x37 + 80025de: 73bb strb r3, [r7, #14] + 80025e0: e007 b.n 80025f2 + } + else + { + MessageCheckSum += (nmea_data[pos] - 0x30); + 80025e2: 88fb ldrh r3, [r7, #6] + 80025e4: 4a09 ldr r2, [pc, #36] ; (800260c ) + 80025e6: 5cd2 ldrb r2, [r2, r3] + 80025e8: 7bbb ldrb r3, [r7, #14] + 80025ea: 4413 add r3, r2 + 80025ec: b2db uxtb r3, r3 + 80025ee: 3b30 subs r3, #48 ; 0x30 + 80025f0: 73bb strb r3, [r7, #14] + } + + if (MessageCheckSum == CheckSum) + 80025f2: 7bba ldrb r2, [r7, #14] + 80025f4: 7bfb ldrb r3, [r7, #15] + 80025f6: 429a cmp r2, r3 + 80025f8: d101 bne.n 80025fe + { + return 1; + 80025fa: 2301 movs r3, #1 + 80025fc: e000 b.n 8002600 + } + else + { + return 0; + 80025fe: 2300 movs r3, #0 + } +} + 8002600: 4618 mov r0, r3 + 8002602: 3714 adds r7, #20 + 8002604: 46bd mov sp, r7 + 8002606: bc80 pop {r7} + 8002608: 4770 bx lr + 800260a: bf00 nop + 800260c: 20000188 .word 0x20000188 + +08002610 : + + + +uint8_t get_gps_status(void) +{ + 8002610: b480 push {r7} + 8002612: af00 add r7, sp, #0 + return gps_num.status; + 8002614: 4b03 ldr r3, [pc, #12] ; (8002624 ) + 8002616: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 +} + 800261a: 4618 mov r0, r3 + 800261c: 46bd mov sp, r7 + 800261e: bc80 pop {r7} + 8002620: 4770 bx lr + 8002622: bf00 nop + 8002624: 20000138 .word 0x20000138 + +08002628 : + + + +char *get_nmea_buf(void) +{ + 8002628: b480 push {r7} + 800262a: af00 add r7, sp, #0 + return &nmea_data[0]; + 800262c: 4b02 ldr r3, [pc, #8] ; (8002638 ) +} + 800262e: 4618 mov r0, r3 + 8002630: 46bd mov sp, r7 + 8002632: bc80 pop {r7} + 8002634: 4770 bx lr + 8002636: bf00 nop + 8002638: 20000188 .word 0x20000188 + +0800263c : + + + +struct gps_raw_struct *get_gps_raw(void) +{ + 800263c: b480 push {r7} + 800263e: af00 add r7, sp, #0 + return &gps_raw; + 8002640: 4b02 ldr r3, [pc, #8] ; (800264c ) +} + 8002642: 4618 mov r0, r3 + 8002644: 46bd mov sp, r7 + 8002646: bc80 pop {r7} + 8002648: 4770 bx lr + 800264a: bf00 nop + 800264c: 20000588 .word 0x20000588 + +08002650 : + + + +struct gps_num_struct *get_gps_num(void) +{ + 8002650: b480 push {r7} + 8002652: af00 add r7, sp, #0 + return &gps_num; + 8002654: 4b02 ldr r3, [pc, #8] ; (8002660 ) +} + 8002656: 4618 mov r0, r3 + 8002658: 46bd mov sp, r7 + 800265a: bc80 pop {r7} + 800265c: 4770 bx lr + 800265e: bf00 nop + 8002660: 20000138 .word 0x20000138 + +08002664 : +#define I2C_CLOCK_DELAY (500) + + + +void i2c_init(void) +{ + 8002664: b480 push {r7} + 8002666: af00 add r7, sp, #0 + //I2C config + RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; //enable i2c clock + 8002668: 4b18 ldr r3, [pc, #96] ; (80026cc ) + 800266a: 69db ldr r3, [r3, #28] + 800266c: 4a17 ldr r2, [pc, #92] ; (80026cc ) + 800266e: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 + 8002672: 61d3 str r3, [r2, #28] + + I2C2->CR2 &= ~I2C_CR2_FREQ; //clear bits before set + 8002674: 4b16 ldr r3, [pc, #88] ; (80026d0 ) + 8002676: 889b ldrh r3, [r3, #4] + 8002678: b29b uxth r3, r3 + 800267a: 4a15 ldr r2, [pc, #84] ; (80026d0 ) + 800267c: f023 033f bic.w r3, r3, #63 ; 0x3f + 8002680: b29b uxth r3, r3 + 8002682: 8093 strh r3, [r2, #4] + I2C2->CR2 |= (uint16_t)10; //10 MHz periph clock + 8002684: 4b12 ldr r3, [pc, #72] ; (80026d0 ) + 8002686: 889b ldrh r3, [r3, #4] + 8002688: b29b uxth r3, r3 + 800268a: 4a11 ldr r2, [pc, #68] ; (80026d0 ) + 800268c: f043 030a orr.w r3, r3, #10 + 8002690: b29b uxth r3, r3 + 8002692: 8093 strh r3, [r2, #4] + + //Stndard mode + I2C2->CCR |= (uint16_t)180; //CCR = TSCL/(2 * TPCLK1); TSCL = 1 / 100kHz standard mode freq; TPCLK1 = 1 / APB1 clock 36 MHz + 8002694: 4b0e ldr r3, [pc, #56] ; (80026d0 ) + 8002696: 8b9b ldrh r3, [r3, #28] + 8002698: b29b uxth r3, r3 + 800269a: 4a0d ldr r2, [pc, #52] ; (80026d0 ) + 800269c: f043 03b4 orr.w r3, r3, #180 ; 0xb4 + 80026a0: b29b uxth r3, r3 + 80026a2: 8393 strh r3, [r2, #28] + I2C2->TRISE |= (uint16_t)37; //TRISE = (Tr max/TPCLK1)+1; Tr max = 1000nS for standard mode + 80026a4: 4b0a ldr r3, [pc, #40] ; (80026d0 ) + 80026a6: 8c1b ldrh r3, [r3, #32] + 80026a8: b29b uxth r3, r3 + 80026aa: 4a09 ldr r2, [pc, #36] ; (80026d0 ) + 80026ac: f043 0325 orr.w r3, r3, #37 ; 0x25 + 80026b0: b29b uxth r3, r3 + 80026b2: 8413 strh r3, [r2, #32] + + I2C2->CR1 |= I2C_CR1_PE; //enable i2c2 + 80026b4: 4b06 ldr r3, [pc, #24] ; (80026d0 ) + 80026b6: 881b ldrh r3, [r3, #0] + 80026b8: b29b uxth r3, r3 + 80026ba: 4a05 ldr r2, [pc, #20] ; (80026d0 ) + 80026bc: f043 0301 orr.w r3, r3, #1 + 80026c0: b29b uxth r3, r3 + 80026c2: 8013 strh r3, [r2, #0] +} + 80026c4: bf00 nop + 80026c6: 46bd mov sp, r7 + 80026c8: bc80 pop {r7} + 80026ca: 4770 bx lr + 80026cc: 40021000 .word 0x40021000 + 80026d0: 40005800 .word 0x40005800 + +080026d4 : +uint8_t device_number; + + + +void init_lrns(void) +{ + 80026d4: b580 push {r7, lr} + 80026d6: b082 sub sp, #8 + 80026d8: af00 add r7, sp, #0 + //Clear mem + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 80026da: 2301 movs r3, #1 + 80026dc: 71fb strb r3, [r7, #7] + 80026de: e017 b.n 8002710 + { + memset(&gps_air[dev], 0, sizeof(gps_air[dev])); + 80026e0: 79fa ldrb r2, [r7, #7] + 80026e2: 4613 mov r3, r2 + 80026e4: 009b lsls r3, r3, #2 + 80026e6: 4413 add r3, r2 + 80026e8: 009b lsls r3, r3, #2 + 80026ea: 4a2d ldr r2, [pc, #180] ; (80027a0 ) + 80026ec: 4413 add r3, r2 + 80026ee: 2214 movs r2, #20 + 80026f0: 2100 movs r1, #0 + 80026f2: 4618 mov r0, r3 + 80026f4: f007 f93b bl 800996e + memset(&gps_rel[dev], 0, sizeof(gps_rel[dev])); + 80026f8: 79fb ldrb r3, [r7, #7] + 80026fa: 00db lsls r3, r3, #3 + 80026fc: 4a29 ldr r2, [pc, #164] ; (80027a4 ) + 80026fe: 4413 add r3, r2 + 8002700: 2208 movs r2, #8 + 8002702: 2100 movs r1, #0 + 8002704: 4618 mov r0, r3 + 8002706: f007 f932 bl 800996e + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 800270a: 79fb ldrb r3, [r7, #7] + 800270c: 3301 adds r3, #1 + 800270e: 71fb strb r3, [r7, #7] + 8002710: 79fb ldrb r3, [r7, #7] + 8002712: 2b06 cmp r3, #6 + 8002714: d9e4 bls.n 80026e0 + } + + //Get external things + p_settings = get_settings(); + 8002716: f006 f90f bl 8008938 + 800271a: 4602 mov r2, r0 + 800271c: 4b22 ldr r3, [pc, #136] ; (80027a8 ) + 800271e: 601a str r2, [r3, #0] + p_gps_num = get_gps_num(); + 8002720: f7ff ff96 bl 8002650 + 8002724: 4602 mov r2, r0 + 8002726: 4b21 ldr r3, [pc, #132] ; (80027ac ) + 8002728: 601a str r2, [r3, #0] + p_air_packet_tx = get_air_packet_tx(); + 800272a: f006 fb6b bl 8008e04 + 800272e: 4602 mov r2, r0 + 8002730: 4b1f ldr r3, [pc, #124] ; (80027b0 ) + 8002732: 601a str r2, [r3, #0] + p_air_packet_rx = get_air_packet_rx(); + 8002734: f006 fb70 bl 8008e18 + 8002738: 4602 mov r2, r0 + 800273a: 4b1e ldr r3, [pc, #120] ; (80027b4 ) + 800273c: 601a str r2, [r3, #0] + + //This device number + device_number = p_settings->device_number; + 800273e: 4b1a ldr r3, [pc, #104] ; (80027a8 ) + 8002740: 681b ldr r3, [r3, #0] + 8002742: 781a ldrb r2, [r3, #0] + 8002744: 4b1c ldr r3, [pc, #112] ; (80027b8 ) + 8002746: 701a strb r2, [r3, #0] + + //Exist flag + dev_aux[device_number].exist_flag = 1; + 8002748: 4b1b ldr r3, [pc, #108] ; (80027b8 ) + 800274a: 781b ldrb r3, [r3, #0] + 800274c: 4619 mov r1, r3 + 800274e: 4a1b ldr r2, [pc, #108] ; (80027bc ) + 8002750: 460b mov r3, r1 + 8002752: 005b lsls r3, r3, #1 + 8002754: 440b add r3, r1 + 8002756: 00db lsls r3, r3, #3 + 8002758: 4413 add r3, r2 + 800275a: 2201 movs r2, #1 + 800275c: 701a strb r2, [r3, #0] + + //ID + gps_air[device_number].device_id[0] = p_settings->device_id[0]; //note: ID loads only once at startup + 800275e: 4b12 ldr r3, [pc, #72] ; (80027a8 ) + 8002760: 681b ldr r3, [r3, #0] + 8002762: 4a15 ldr r2, [pc, #84] ; (80027b8 ) + 8002764: 7812 ldrb r2, [r2, #0] + 8002766: 4611 mov r1, r2 + 8002768: 7858 ldrb r0, [r3, #1] + 800276a: 4a0d ldr r2, [pc, #52] ; (80027a0 ) + 800276c: 460b mov r3, r1 + 800276e: 009b lsls r3, r3, #2 + 8002770: 440b add r3, r1 + 8002772: 009b lsls r3, r3, #2 + 8002774: 4413 add r3, r2 + 8002776: 4602 mov r2, r0 + 8002778: 701a strb r2, [r3, #0] + gps_air[device_number].device_id[1] = p_settings->device_id[1]; + 800277a: 4b0b ldr r3, [pc, #44] ; (80027a8 ) + 800277c: 681b ldr r3, [r3, #0] + 800277e: 4a0e ldr r2, [pc, #56] ; (80027b8 ) + 8002780: 7812 ldrb r2, [r2, #0] + 8002782: 4611 mov r1, r2 + 8002784: 7898 ldrb r0, [r3, #2] + 8002786: 4a06 ldr r2, [pc, #24] ; (80027a0 ) + 8002788: 460b mov r3, r1 + 800278a: 009b lsls r3, r3, #2 + 800278c: 440b add r3, r1 + 800278e: 009b lsls r3, r3, #2 + 8002790: 4413 add r3, r2 + 8002792: 3301 adds r3, #1 + 8002794: 4602 mov r2, r0 + 8002796: 701a strb r2, [r3, #0] +} + 8002798: bf00 nop + 800279a: 3708 adds r7, #8 + 800279c: 46bd mov sp, r7 + 800279e: bd80 pop {r7, pc} + 80027a0: 20000740 .word 0x20000740 + 80027a4: 20000700 .word 0x20000700 + 80027a8: 2000061c .word 0x2000061c + 80027ac: 20000614 .word 0x20000614 + 80027b0: 2000073c .word 0x2000073c + 80027b4: 20000618 .word 0x20000618 + 80027b8: 20000738 .word 0x20000738 + 80027bc: 20000620 .word 0x20000620 + +080027c0 : + + + +//Set this device flags +void set_device_flags(uint8_t parameter_to_set, uint8_t parameter_value) +{ + 80027c0: b480 push {r7} + 80027c2: b085 sub sp, #20 + 80027c4: af00 add r7, sp, #0 + 80027c6: 4603 mov r3, r0 + 80027c8: 460a mov r2, r1 + 80027ca: 71fb strb r3, [r7, #7] + 80027cc: 4613 mov r3, r2 + 80027ce: 71bb strb r3, [r7, #6] + uint8_t mask; + uint8_t pos; + + switch (parameter_to_set) + 80027d0: 79fb ldrb r3, [r7, #7] + 80027d2: 3b01 subs r3, #1 + 80027d4: 2b03 cmp r3, #3 + 80027d6: d81f bhi.n 8002818 + 80027d8: a201 add r2, pc, #4 ; (adr r2, 80027e0 ) + 80027da: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80027de: bf00 nop + 80027e0: 080027f1 .word 0x080027f1 + 80027e4: 080027fb .word 0x080027fb + 80027e8: 08002805 .word 0x08002805 + 80027ec: 0800280f .word 0x0800280f + { + case FLAGS_BATTERY: + mask = FLAGS_BATTERY_MASK; + 80027f0: 2307 movs r3, #7 + 80027f2: 73fb strb r3, [r7, #15] + pos = FLAGS_BATTERY_POS; + 80027f4: 2300 movs r3, #0 + 80027f6: 73bb strb r3, [r7, #14] + break; + 80027f8: e00e b.n 8002818 + + case FLAGS_GPS_FIX: + mask = FLAGS_GPS_FIX_MASK; + 80027fa: 2308 movs r3, #8 + 80027fc: 73fb strb r3, [r7, #15] + pos = FLAGS_GPS_FIX_POS; + 80027fe: 2303 movs r3, #3 + 8002800: 73bb strb r3, [r7, #14] + break; + 8002802: e009 b.n 8002818 + + case FLAGS_PDOP: + mask = FLAGS_PDOP_MASK; + 8002804: 2310 movs r3, #16 + 8002806: 73fb strb r3, [r7, #15] + pos = FLAGS_PDOP_POS; + 8002808: 2304 movs r3, #4 + 800280a: 73bb strb r3, [r7, #14] + break; + 800280c: e004 b.n 8002818 + + case FLAGS_ALARM: + mask = FLAGS_ALARM_MASK; + 800280e: 2320 movs r3, #32 + 8002810: 73fb strb r3, [r7, #15] + pos = FLAGS_ALARM_POS; + 8002812: 2305 movs r3, #5 + 8002814: 73bb strb r3, [r7, #14] + break; + 8002816: bf00 nop + } + + gps_air[device_number].flags &= ~mask; //clear bits + 8002818: 4b26 ldr r3, [pc, #152] ; (80028b4 ) + 800281a: 781b ldrb r3, [r3, #0] + 800281c: 4619 mov r1, r3 + 800281e: 4a26 ldr r2, [pc, #152] ; (80028b8 ) + 8002820: 460b mov r3, r1 + 8002822: 009b lsls r3, r3, #2 + 8002824: 440b add r3, r1 + 8002826: 009b lsls r3, r3, #2 + 8002828: 4413 add r3, r2 + 800282a: 3302 adds r3, #2 + 800282c: 781b ldrb r3, [r3, #0] + 800282e: b25a sxtb r2, r3 + 8002830: f997 300f ldrsb.w r3, [r7, #15] + 8002834: 43db mvns r3, r3 + 8002836: b25b sxtb r3, r3 + 8002838: 4013 ands r3, r2 + 800283a: b25a sxtb r2, r3 + 800283c: 4b1d ldr r3, [pc, #116] ; (80028b4 ) + 800283e: 781b ldrb r3, [r3, #0] + 8002840: 4619 mov r1, r3 + 8002842: b2d0 uxtb r0, r2 + 8002844: 4a1c ldr r2, [pc, #112] ; (80028b8 ) + 8002846: 460b mov r3, r1 + 8002848: 009b lsls r3, r3, #2 + 800284a: 440b add r3, r1 + 800284c: 009b lsls r3, r3, #2 + 800284e: 4413 add r3, r2 + 8002850: 3302 adds r3, #2 + 8002852: 4602 mov r2, r0 + 8002854: 701a strb r2, [r3, #0] + parameter_value &= (mask >> pos); //clear non-masked bits + 8002856: 7bfa ldrb r2, [r7, #15] + 8002858: 7bbb ldrb r3, [r7, #14] + 800285a: fa42 f303 asr.w r3, r2, r3 + 800285e: b25a sxtb r2, r3 + 8002860: f997 3006 ldrsb.w r3, [r7, #6] + 8002864: 4013 ands r3, r2 + 8002866: b25b sxtb r3, r3 + 8002868: 71bb strb r3, [r7, #6] + gps_air[device_number].flags |= (parameter_value << pos); //add to flags + 800286a: 4b12 ldr r3, [pc, #72] ; (80028b4 ) + 800286c: 781b ldrb r3, [r3, #0] + 800286e: 4619 mov r1, r3 + 8002870: 4a11 ldr r2, [pc, #68] ; (80028b8 ) + 8002872: 460b mov r3, r1 + 8002874: 009b lsls r3, r3, #2 + 8002876: 440b add r3, r1 + 8002878: 009b lsls r3, r3, #2 + 800287a: 4413 add r3, r2 + 800287c: 3302 adds r3, #2 + 800287e: 781b ldrb r3, [r3, #0] + 8002880: b25a sxtb r2, r3 + 8002882: 79b9 ldrb r1, [r7, #6] + 8002884: 7bbb ldrb r3, [r7, #14] + 8002886: fa01 f303 lsl.w r3, r1, r3 + 800288a: b25b sxtb r3, r3 + 800288c: 4313 orrs r3, r2 + 800288e: b25a sxtb r2, r3 + 8002890: 4b08 ldr r3, [pc, #32] ; (80028b4 ) + 8002892: 781b ldrb r3, [r3, #0] + 8002894: 4619 mov r1, r3 + 8002896: b2d0 uxtb r0, r2 + 8002898: 4a07 ldr r2, [pc, #28] ; (80028b8 ) + 800289a: 460b mov r3, r1 + 800289c: 009b lsls r3, r3, #2 + 800289e: 440b add r3, r1 + 80028a0: 009b lsls r3, r3, #2 + 80028a2: 4413 add r3, r2 + 80028a4: 3302 adds r3, #2 + 80028a6: 4602 mov r2, r0 + 80028a8: 701a strb r2, [r3, #0] +} + 80028aa: bf00 nop + 80028ac: 3714 adds r7, #20 + 80028ae: 46bd mov sp, r7 + 80028b0: bc80 pop {r7} + 80028b2: 4770 bx lr + 80028b4: 20000738 .word 0x20000738 + 80028b8: 20000740 .word 0x20000740 + +080028bc : + + + +//Get any device flags +uint8_t get_device_flags(uint8_t dev_num, uint8_t parameter_to_get) +{ + 80028bc: b480 push {r7} + 80028be: b085 sub sp, #20 + 80028c0: af00 add r7, sp, #0 + 80028c2: 4603 mov r3, r0 + 80028c4: 460a mov r2, r1 + 80028c6: 71fb strb r3, [r7, #7] + 80028c8: 4613 mov r3, r2 + 80028ca: 71bb strb r3, [r7, #6] + uint8_t mask; + uint8_t pos; + + switch (parameter_to_get) + 80028cc: 79bb ldrb r3, [r7, #6] + 80028ce: 3b01 subs r3, #1 + 80028d0: 2b03 cmp r3, #3 + 80028d2: d81f bhi.n 8002914 + 80028d4: a201 add r2, pc, #4 ; (adr r2, 80028dc ) + 80028d6: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80028da: bf00 nop + 80028dc: 080028ed .word 0x080028ed + 80028e0: 080028f7 .word 0x080028f7 + 80028e4: 08002901 .word 0x08002901 + 80028e8: 0800290b .word 0x0800290b + { + case FLAGS_BATTERY: + mask = FLAGS_BATTERY_MASK; + 80028ec: 2307 movs r3, #7 + 80028ee: 73fb strb r3, [r7, #15] + pos = FLAGS_BATTERY_POS; + 80028f0: 2300 movs r3, #0 + 80028f2: 73bb strb r3, [r7, #14] + break; + 80028f4: e00e b.n 8002914 + + case FLAGS_GPS_FIX: + mask = FLAGS_GPS_FIX_MASK; + 80028f6: 2308 movs r3, #8 + 80028f8: 73fb strb r3, [r7, #15] + pos = FLAGS_GPS_FIX_POS; + 80028fa: 2303 movs r3, #3 + 80028fc: 73bb strb r3, [r7, #14] + break; + 80028fe: e009 b.n 8002914 + + case FLAGS_PDOP: + mask = FLAGS_PDOP_MASK; + 8002900: 2310 movs r3, #16 + 8002902: 73fb strb r3, [r7, #15] + pos = FLAGS_PDOP_POS; + 8002904: 2304 movs r3, #4 + 8002906: 73bb strb r3, [r7, #14] + break; + 8002908: e004 b.n 8002914 + + case FLAGS_ALARM: + mask = FLAGS_ALARM_MASK; + 800290a: 2320 movs r3, #32 + 800290c: 73fb strb r3, [r7, #15] + pos = FLAGS_ALARM_POS; + 800290e: 2305 movs r3, #5 + 8002910: 73bb strb r3, [r7, #14] + break; + 8002912: bf00 nop + } + + return (gps_air[dev_num].flags & mask) >> pos; + 8002914: 79fa ldrb r2, [r7, #7] + 8002916: 490a ldr r1, [pc, #40] ; (8002940 ) + 8002918: 4613 mov r3, r2 + 800291a: 009b lsls r3, r3, #2 + 800291c: 4413 add r3, r2 + 800291e: 009b lsls r3, r3, #2 + 8002920: 440b add r3, r1 + 8002922: 3302 adds r3, #2 + 8002924: 781a ldrb r2, [r3, #0] + 8002926: 7bfb ldrb r3, [r7, #15] + 8002928: 4013 ands r3, r2 + 800292a: b2db uxtb r3, r3 + 800292c: 461a mov r2, r3 + 800292e: 7bbb ldrb r3, [r7, #14] + 8002930: fa42 f303 asr.w r3, r2, r3 + 8002934: b2db uxtb r3, r3 +} + 8002936: 4618 mov r0, r3 + 8002938: 3714 adds r7, #20 + 800293a: 46bd mov sp, r7 + 800293c: bc80 pop {r7} + 800293e: 4770 bx lr + 8002940: 20000740 .word 0x20000740 + +08002944 : + + + +//Check alarm status of each device and make red led on if any alarm exist +uint8_t check_alarms(void) +{ + 8002944: b580 push {r7, lr} + 8002946: b082 sub sp, #8 + 8002948: af00 add r7, sp, #0 + uint8_t led_status = 0; + 800294a: 2300 movs r3, #0 + 800294c: 71fb strb r3, [r7, #7] + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 800294e: 2301 movs r3, #1 + 8002950: 71bb strb r3, [r7, #6] + 8002952: e00c b.n 800296e + { + if (get_device_flags(dev, FLAGS_ALARM) == FLAG_ALARM_ON) + 8002954: 79bb ldrb r3, [r7, #6] + 8002956: 2104 movs r1, #4 + 8002958: 4618 mov r0, r3 + 800295a: f7ff ffaf bl 80028bc + 800295e: 4603 mov r3, r0 + 8002960: 2b01 cmp r3, #1 + 8002962: d101 bne.n 8002968 + { + led_status = 1; + 8002964: 2301 movs r3, #1 + 8002966: 71fb strb r3, [r7, #7] + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8002968: 79bb ldrb r3, [r7, #6] + 800296a: 3301 adds r3, #1 + 800296c: 71bb strb r3, [r7, #6] + 800296e: 79bb ldrb r3, [r7, #6] + 8002970: 2b06 cmp r3, #6 + 8002972: d9ef bls.n 8002954 + } + } + + if (led_status == 1) + 8002974: 79fb ldrb r3, [r7, #7] + 8002976: 2b01 cmp r3, #1 + 8002978: d103 bne.n 8002982 + { + led_red_on(); + 800297a: f7ff f917 bl 8001bac + return 1; + 800297e: 2301 movs r3, #1 + 8002980: e002 b.n 8002988 + } + else + { + led_red_off(); + 8002982: f7ff f91f bl 8001bc4 + return 0; + 8002986: 2300 movs r3, #0 + } +} + 8002988: 4618 mov r0, r3 + 800298a: 3708 adds r7, #8 + 800298c: 46bd mov sp, r7 + 800298e: bd80 pop {r7, pc} + +08002990 : + + + +void calc_timeout(uint32_t current_uptime) +{ + 8002990: b480 push {r7} + 8002992: b085 sub sp, #20 + 8002994: af00 add r7, sp, #0 + 8002996: 6078 str r0, [r7, #4] + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8002998: 2301 movs r3, #1 + 800299a: 73fb strb r3, [r7, #15] + 800299c: e020 b.n 80029e0 + { + if (dev_aux[dev].exist_flag == 1) + 800299e: 7bfa ldrb r2, [r7, #15] + 80029a0: 4913 ldr r1, [pc, #76] ; (80029f0 ) + 80029a2: 4613 mov r3, r2 + 80029a4: 005b lsls r3, r3, #1 + 80029a6: 4413 add r3, r2 + 80029a8: 00db lsls r3, r3, #3 + 80029aa: 440b add r3, r1 + 80029ac: 781b ldrb r3, [r3, #0] + 80029ae: 2b01 cmp r3, #1 + 80029b0: d113 bne.n 80029da + { + dev_aux[dev].timeout = current_uptime - dev_aux[dev].timestamp; + 80029b2: 7bfa ldrb r2, [r7, #15] + 80029b4: 490e ldr r1, [pc, #56] ; (80029f0 ) + 80029b6: 4613 mov r3, r2 + 80029b8: 005b lsls r3, r3, #1 + 80029ba: 4413 add r3, r2 + 80029bc: 00db lsls r3, r3, #3 + 80029be: 440b add r3, r1 + 80029c0: 3304 adds r3, #4 + 80029c2: 681b ldr r3, [r3, #0] + 80029c4: 7bfa ldrb r2, [r7, #15] + 80029c6: 6879 ldr r1, [r7, #4] + 80029c8: 1ac9 subs r1, r1, r3 + 80029ca: 4809 ldr r0, [pc, #36] ; (80029f0 ) + 80029cc: 4613 mov r3, r2 + 80029ce: 005b lsls r3, r3, #1 + 80029d0: 4413 add r3, r2 + 80029d2: 00db lsls r3, r3, #3 + 80029d4: 4403 add r3, r0 + 80029d6: 3308 adds r3, #8 + 80029d8: 6019 str r1, [r3, #0] + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 80029da: 7bfb ldrb r3, [r7, #15] + 80029dc: 3301 adds r3, #1 + 80029de: 73fb strb r3, [r7, #15] + 80029e0: 7bfb ldrb r3, [r7, #15] + 80029e2: 2b06 cmp r3, #6 + 80029e4: d9db bls.n 800299e + } + } +} + 80029e6: bf00 nop + 80029e8: 3714 adds r7, #20 + 80029ea: 46bd mov sp, r7 + 80029ec: bc80 pop {r7} + 80029ee: 4770 bx lr + 80029f0: 20000620 .word 0x20000620 + +080029f4 : + + + +//Check devices timeout and set flags if needed +uint8_t check_timeout(void) +{ + 80029f4: b480 push {r7} + 80029f6: b083 sub sp, #12 + 80029f8: af00 add r7, sp, #0 + uint8_t timeout_status = 0; + 80029fa: 2300 movs r3, #0 + 80029fc: 71fb strb r3, [r7, #7] + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 80029fe: 2301 movs r3, #1 + 8002a00: 71bb strb r3, [r7, #6] + 8002a02: e037 b.n 8002a74 + { + if (dev_aux[dev].memory_point_flag == 0) //no timeout alarm for memory points + 8002a04: 79ba ldrb r2, [r7, #6] + 8002a06: 4922 ldr r1, [pc, #136] ; (8002a90 ) + 8002a08: 4613 mov r3, r2 + 8002a0a: 005b lsls r3, r3, #1 + 8002a0c: 4413 add r3, r2 + 8002a0e: 00db lsls r3, r3, #3 + 8002a10: 440b add r3, r1 + 8002a12: 330e adds r3, #14 + 8002a14: 781b ldrb r3, [r3, #0] + 8002a16: 2b00 cmp r3, #0 + 8002a18: d129 bne.n 8002a6e + { + if (p_settings->timeout_threshold.as_integer != TIMEOUT_ALARM_DISABLED) + 8002a1a: 4b1e ldr r3, [pc, #120] ; (8002a94 ) + 8002a1c: 681b ldr r3, [r3, #0] + 8002a1e: 88db ldrh r3, [r3, #6] + 8002a20: 2b00 cmp r3, #0 + 8002a22: d024 beq.n 8002a6e + { + if (dev_aux[dev].timeout > p_settings->timeout_threshold.as_integer) + 8002a24: 79ba ldrb r2, [r7, #6] + 8002a26: 491a ldr r1, [pc, #104] ; (8002a90 ) + 8002a28: 4613 mov r3, r2 + 8002a2a: 005b lsls r3, r3, #1 + 8002a2c: 4413 add r3, r2 + 8002a2e: 00db lsls r3, r3, #3 + 8002a30: 440b add r3, r1 + 8002a32: 3308 adds r3, #8 + 8002a34: 681b ldr r3, [r3, #0] + 8002a36: 4a17 ldr r2, [pc, #92] ; (8002a94 ) + 8002a38: 6812 ldr r2, [r2, #0] + 8002a3a: 88d2 ldrh r2, [r2, #6] + 8002a3c: 4293 cmp r3, r2 + 8002a3e: d90c bls.n 8002a5a + { + dev_aux[dev].timeout_flag = 1; + 8002a40: 79ba ldrb r2, [r7, #6] + 8002a42: 4913 ldr r1, [pc, #76] ; (8002a90 ) + 8002a44: 4613 mov r3, r2 + 8002a46: 005b lsls r3, r3, #1 + 8002a48: 4413 add r3, r2 + 8002a4a: 00db lsls r3, r3, #3 + 8002a4c: 440b add r3, r1 + 8002a4e: 330c adds r3, #12 + 8002a50: 2201 movs r2, #1 + 8002a52: 701a strb r2, [r3, #0] + timeout_status = 1; + 8002a54: 2301 movs r3, #1 + 8002a56: 71fb strb r3, [r7, #7] + 8002a58: e009 b.n 8002a6e + } + else + { + dev_aux[dev].timeout_flag = 0; + 8002a5a: 79ba ldrb r2, [r7, #6] + 8002a5c: 490c ldr r1, [pc, #48] ; (8002a90 ) + 8002a5e: 4613 mov r3, r2 + 8002a60: 005b lsls r3, r3, #1 + 8002a62: 4413 add r3, r2 + 8002a64: 00db lsls r3, r3, #3 + 8002a66: 440b add r3, r1 + 8002a68: 330c adds r3, #12 + 8002a6a: 2200 movs r2, #0 + 8002a6c: 701a strb r2, [r3, #0] + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8002a6e: 79bb ldrb r3, [r7, #6] + 8002a70: 3301 adds r3, #1 + 8002a72: 71bb strb r3, [r7, #6] + 8002a74: 79bb ldrb r3, [r7, #6] + 8002a76: 2b06 cmp r3, #6 + 8002a78: d9c4 bls.n 8002a04 + } + } + } + } + + if (timeout_status == 1) + 8002a7a: 79fb ldrb r3, [r7, #7] + 8002a7c: 2b01 cmp r3, #1 + 8002a7e: d101 bne.n 8002a84 + { + return 1; + 8002a80: 2301 movs r3, #1 + 8002a82: e000 b.n 8002a86 + } + else + { + return 0; + 8002a84: 2300 movs r3, #0 + } +} + 8002a86: 4618 mov r0, r3 + 8002a88: 370c adds r7, #12 + 8002a8a: 46bd mov sp, r7 + 8002a8c: bc80 pop {r7} + 8002a8e: 4770 bx lr + 8002a90: 20000620 .word 0x20000620 + 8002a94: 2000061c .word 0x2000061c + +08002a98 : + + + +uint8_t check_fence(void) +{ + 8002a98: b480 push {r7} + 8002a9a: b083 sub sp, #12 + 8002a9c: af00 add r7, sp, #0 + uint8_t fence_status = 0; + 8002a9e: 2300 movs r3, #0 + 8002aa0: 71fb strb r3, [r7, #7] + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8002aa2: 2301 movs r3, #1 + 8002aa4: 71bb strb r3, [r7, #6] + 8002aa6: e02c b.n 8002b02 + { + if (dev_aux[dev].exist_flag) + 8002aa8: 79ba ldrb r2, [r7, #6] + 8002aaa: 491d ldr r1, [pc, #116] ; (8002b20 ) + 8002aac: 4613 mov r3, r2 + 8002aae: 005b lsls r3, r3, #1 + 8002ab0: 4413 add r3, r2 + 8002ab2: 00db lsls r3, r3, #3 + 8002ab4: 440b add r3, r1 + 8002ab6: 781b ldrb r3, [r3, #0] + 8002ab8: 2b00 cmp r3, #0 + 8002aba: d01f beq.n 8002afc + { + if (gps_rel[dev].distance > p_settings->fence_threshold.as_integer) + 8002abc: 79bb ldrb r3, [r7, #6] + 8002abe: 4a19 ldr r2, [pc, #100] ; (8002b24 ) + 8002ac0: f852 3033 ldr.w r3, [r2, r3, lsl #3] + 8002ac4: 4a18 ldr r2, [pc, #96] ; (8002b28 ) + 8002ac6: 6812 ldr r2, [r2, #0] + 8002ac8: 8912 ldrh r2, [r2, #8] + 8002aca: 4293 cmp r3, r2 + 8002acc: d90c bls.n 8002ae8 + { + dev_aux[dev].fence_flag = 1; + 8002ace: 79ba ldrb r2, [r7, #6] + 8002ad0: 4913 ldr r1, [pc, #76] ; (8002b20 ) + 8002ad2: 4613 mov r3, r2 + 8002ad4: 005b lsls r3, r3, #1 + 8002ad6: 4413 add r3, r2 + 8002ad8: 00db lsls r3, r3, #3 + 8002ada: 440b add r3, r1 + 8002adc: 330d adds r3, #13 + 8002ade: 2201 movs r2, #1 + 8002ae0: 701a strb r2, [r3, #0] + fence_status = 1; + 8002ae2: 2301 movs r3, #1 + 8002ae4: 71fb strb r3, [r7, #7] + 8002ae6: e009 b.n 8002afc + } + else + { + dev_aux[dev].fence_flag = 0; + 8002ae8: 79ba ldrb r2, [r7, #6] + 8002aea: 490d ldr r1, [pc, #52] ; (8002b20 ) + 8002aec: 4613 mov r3, r2 + 8002aee: 005b lsls r3, r3, #1 + 8002af0: 4413 add r3, r2 + 8002af2: 00db lsls r3, r3, #3 + 8002af4: 440b add r3, r1 + 8002af6: 330d adds r3, #13 + 8002af8: 2200 movs r2, #0 + 8002afa: 701a strb r2, [r3, #0] + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8002afc: 79bb ldrb r3, [r7, #6] + 8002afe: 3301 adds r3, #1 + 8002b00: 71bb strb r3, [r7, #6] + 8002b02: 79bb ldrb r3, [r7, #6] + 8002b04: 2b06 cmp r3, #6 + 8002b06: d9cf bls.n 8002aa8 + } + } + } + + if (fence_status == 1) + 8002b08: 79fb ldrb r3, [r7, #7] + 8002b0a: 2b01 cmp r3, #1 + 8002b0c: d101 bne.n 8002b12 + { + return 1; + 8002b0e: 2301 movs r3, #1 + 8002b10: e000 b.n 8002b14 + } + else + { + return 0; + 8002b12: 2300 movs r3, #0 + } +} + 8002b14: 4618 mov r0, r3 + 8002b16: 370c adds r7, #12 + 8002b18: 46bd mov sp, r7 + 8002b1a: bc80 pop {r7} + 8002b1c: 4770 bx lr + 8002b1e: bf00 nop + 8002b20: 20000620 .word 0x20000620 + 8002b24: 20000700 .word 0x20000700 + 8002b28: 2000061c .word 0x2000061c + +08002b2c : + + + +void process_all_devices(void) +{ + 8002b2c: b580 push {r7, lr} + 8002b2e: b082 sub sp, #8 + 8002b30: af00 add r7, sp, #0 + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8002b32: 2301 movs r3, #1 + 8002b34: 71fb strb r3, [r7, #7] + 8002b36: e010 b.n 8002b5a + { + if (dev_aux[dev].exist_flag == 1) //process mem points too + 8002b38: 79fa ldrb r2, [r7, #7] + 8002b3a: 490b ldr r1, [pc, #44] ; (8002b68 ) + 8002b3c: 4613 mov r3, r2 + 8002b3e: 005b lsls r3, r3, #1 + 8002b40: 4413 add r3, r2 + 8002b42: 00db lsls r3, r3, #3 + 8002b44: 440b add r3, r1 + 8002b46: 781b ldrb r3, [r3, #0] + 8002b48: 2b01 cmp r3, #1 + 8002b4a: d103 bne.n 8002b54 + { + calc_relative_position(dev); + 8002b4c: 79fb ldrb r3, [r7, #7] + 8002b4e: 4618 mov r0, r3 + 8002b50: f000 faa6 bl 80030a0 + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8002b54: 79fb ldrb r3, [r7, #7] + 8002b56: 3301 adds r3, #1 + 8002b58: 71fb strb r3, [r7, #7] + 8002b5a: 79fb ldrb r3, [r7, #7] + 8002b5c: 2b06 cmp r3, #6 + 8002b5e: d9eb bls.n 8002b38 + } + } +} + 8002b60: bf00 nop + 8002b62: 3708 adds r7, #8 + 8002b64: 46bd mov sp, r7 + 8002b66: bd80 pop {r7, pc} + 8002b68: 20000620 .word 0x20000620 + +08002b6c : + + + +//Update gps_air structure with coordinates of this device in order to transmit them further +void gps_air_update_my_data(uint32_t uptime) +{ + 8002b6c: b590 push {r4, r7, lr} + 8002b6e: b083 sub sp, #12 + 8002b70: af00 add r7, sp, #0 + 8002b72: 6078 str r0, [r7, #4] + + //Timestamp + dev_aux[device_number].timestamp = uptime; + 8002b74: 4b44 ldr r3, [pc, #272] ; (8002c88 ) + 8002b76: 781b ldrb r3, [r3, #0] + 8002b78: 4619 mov r1, r3 + 8002b7a: 4a44 ldr r2, [pc, #272] ; (8002c8c ) + 8002b7c: 460b mov r3, r1 + 8002b7e: 005b lsls r3, r3, #1 + 8002b80: 440b add r3, r1 + 8002b82: 00db lsls r3, r3, #3 + 8002b84: 4413 add r3, r2 + 8002b86: 3304 adds r3, #4 + 8002b88: 687a ldr r2, [r7, #4] + 8002b8a: 601a str r2, [r3, #0] + + + //Flags + if (p_gps_num->mode == GPS_POSITION_3DFIX) + 8002b8c: 4b40 ldr r3, [pc, #256] ; (8002c90 ) + 8002b8e: 681b ldr r3, [r3, #0] + 8002b90: f893 3037 ldrb.w r3, [r3, #55] ; 0x37 + 8002b94: 2b03 cmp r3, #3 + 8002b96: d104 bne.n 8002ba2 + { + set_device_flags(FLAGS_GPS_FIX, FLAG_GPS_FIX_3D); + 8002b98: 2101 movs r1, #1 + 8002b9a: 2002 movs r0, #2 + 8002b9c: f7ff fe10 bl 80027c0 + 8002ba0: e003 b.n 8002baa + } + else + { + set_device_flags(FLAGS_GPS_FIX, FLAG_GPS_FIX_2D); + 8002ba2: 2100 movs r1, #0 + 8002ba4: 2002 movs r0, #2 + 8002ba6: f7ff fe0b bl 80027c0 + } + + if (p_gps_num->pdop <= PDOP_THRESHOLD) + 8002baa: 4b39 ldr r3, [pc, #228] ; (8002c90 ) + 8002bac: 681b ldr r3, [r3, #0] + 8002bae: 6b9b ldr r3, [r3, #56] ; 0x38 + 8002bb0: 4938 ldr r1, [pc, #224] ; (8002c94 ) + 8002bb2: 4618 mov r0, r3 + 8002bb4: f7fe fa96 bl 80010e4 <__aeabi_fcmple> + 8002bb8: 4603 mov r3, r0 + 8002bba: 2b00 cmp r3, #0 + 8002bbc: d004 beq.n 8002bc8 + { + set_device_flags(FLAGS_PDOP, FLAG_PDOP_GOOD); + 8002bbe: 2101 movs r1, #1 + 8002bc0: 2003 movs r0, #3 + 8002bc2: f7ff fdfd bl 80027c0 + 8002bc6: e003 b.n 8002bd0 + } + else + { + set_device_flags(FLAGS_PDOP, FLAG_PDOP_BAD); + 8002bc8: 2100 movs r1, #0 + 8002bca: 2003 movs r0, #3 + 8002bcc: f7ff fdf8 bl 80027c0 + } + + //Latitude & Longitude + gps_air[device_number].latitude.as_float = p_gps_num->latitude.in_deg; + 8002bd0: 4b2f ldr r3, [pc, #188] ; (8002c90 ) + 8002bd2: 681b ldr r3, [r3, #0] + 8002bd4: 4a2c ldr r2, [pc, #176] ; (8002c88 ) + 8002bd6: 7812 ldrb r2, [r2, #0] + 8002bd8: 4610 mov r0, r2 + 8002bda: 689a ldr r2, [r3, #8] + 8002bdc: 492e ldr r1, [pc, #184] ; (8002c98 ) + 8002bde: 4603 mov r3, r0 + 8002be0: 009b lsls r3, r3, #2 + 8002be2: 4403 add r3, r0 + 8002be4: 009b lsls r3, r3, #2 + 8002be6: 440b add r3, r1 + 8002be8: 3304 adds r3, #4 + 8002bea: 601a str r2, [r3, #0] + gps_air[device_number].longitude.as_float = p_gps_num->longitude.in_deg; + 8002bec: 4b28 ldr r3, [pc, #160] ; (8002c90 ) + 8002bee: 681b ldr r3, [r3, #0] + 8002bf0: 4a25 ldr r2, [pc, #148] ; (8002c88 ) + 8002bf2: 7812 ldrb r2, [r2, #0] + 8002bf4: 4610 mov r0, r2 + 8002bf6: 699a ldr r2, [r3, #24] + 8002bf8: 4927 ldr r1, [pc, #156] ; (8002c98 ) + 8002bfa: 4603 mov r3, r0 + 8002bfc: 009b lsls r3, r3, #2 + 8002bfe: 4403 add r3, r0 + 8002c00: 009b lsls r3, r3, #2 + 8002c02: 440b add r3, r1 + 8002c04: 3308 adds r3, #8 + 8002c06: 601a str r2, [r3, #0] + + //Altitude + gps_air[device_number].altitude.as_integer = (int16_t)p_gps_num->altitude; + 8002c08: 4b21 ldr r3, [pc, #132] ; (8002c90 ) + 8002c0a: 681b ldr r3, [r3, #0] + 8002c0c: 6b1a ldr r2, [r3, #48] ; 0x30 + 8002c0e: 4b1e ldr r3, [pc, #120] ; (8002c88 ) + 8002c10: 781b ldrb r3, [r3, #0] + 8002c12: 461c mov r4, r3 + 8002c14: 4610 mov r0, r2 + 8002c16: f7fe fa83 bl 8001120 <__aeabi_f2iz> + 8002c1a: 4603 mov r3, r0 + 8002c1c: b219 sxth r1, r3 + 8002c1e: 4a1e ldr r2, [pc, #120] ; (8002c98 ) + 8002c20: 4623 mov r3, r4 + 8002c22: 009b lsls r3, r3, #2 + 8002c24: 4423 add r3, r4 + 8002c26: 009b lsls r3, r3, #2 + 8002c28: 4413 add r3, r2 + 8002c2a: 330c adds r3, #12 + 8002c2c: 460a mov r2, r1 + 8002c2e: 801a strh r2, [r3, #0] + + //Speed + gps_air[device_number].speed = (uint8_t)p_gps_num->speed; + 8002c30: 4b17 ldr r3, [pc, #92] ; (8002c90 ) + 8002c32: 681b ldr r3, [r3, #0] + 8002c34: 6a9a ldr r2, [r3, #40] ; 0x28 + 8002c36: 4b14 ldr r3, [pc, #80] ; (8002c88 ) + 8002c38: 781b ldrb r3, [r3, #0] + 8002c3a: 461c mov r4, r3 + 8002c3c: 4610 mov r0, r2 + 8002c3e: f7fe fa95 bl 800116c <__aeabi_f2uiz> + 8002c42: 4603 mov r3, r0 + 8002c44: b2d9 uxtb r1, r3 + 8002c46: 4a14 ldr r2, [pc, #80] ; (8002c98 ) + 8002c48: 4623 mov r3, r4 + 8002c4a: 009b lsls r3, r3, #2 + 8002c4c: 4423 add r3, r4 + 8002c4e: 009b lsls r3, r3, #2 + 8002c50: 4413 add r3, r2 + 8002c52: 330e adds r3, #14 + 8002c54: 460a mov r2, r1 + 8002c56: 701a strb r2, [r3, #0] + + //Course + gps_air[device_number].course.as_integer = (uint16_t)p_gps_num->course; + 8002c58: 4b0d ldr r3, [pc, #52] ; (8002c90 ) + 8002c5a: 681b ldr r3, [r3, #0] + 8002c5c: 6ada ldr r2, [r3, #44] ; 0x2c + 8002c5e: 4b0a ldr r3, [pc, #40] ; (8002c88 ) + 8002c60: 781b ldrb r3, [r3, #0] + 8002c62: 461c mov r4, r3 + 8002c64: 4610 mov r0, r2 + 8002c66: f7fe fa81 bl 800116c <__aeabi_f2uiz> + 8002c6a: 4603 mov r3, r0 + 8002c6c: b299 uxth r1, r3 + 8002c6e: 4a0a ldr r2, [pc, #40] ; (8002c98 ) + 8002c70: 4623 mov r3, r4 + 8002c72: 009b lsls r3, r3, #2 + 8002c74: 4423 add r3, r4 + 8002c76: 009b lsls r3, r3, #2 + 8002c78: 4413 add r3, r2 + 8002c7a: 3310 adds r3, #16 + 8002c7c: 460a mov r2, r1 + 8002c7e: 801a strh r2, [r3, #0] +} + 8002c80: bf00 nop + 8002c82: 370c adds r7, #12 + 8002c84: 46bd mov sp, r7 + 8002c86: bd90 pop {r4, r7, pc} + 8002c88: 20000738 .word 0x20000738 + 8002c8c: 20000620 .word 0x20000620 + 8002c90: 20000614 .word 0x20000614 + 8002c94: 40c00000 .word 0x40c00000 + 8002c98: 20000740 .word 0x20000740 + +08002c9c : + + + +//Copy gps_air struct data to the TX air packet +void fill_air_packet_with_struct_data(void) +{ + 8002c9c: b480 push {r7} + 8002c9e: af00 add r7, sp, #0 + p_air_packet_tx[PACKET_DEVICE_NUMBER_POS] = device_number; //this device number + 8002ca0: 4b80 ldr r3, [pc, #512] ; (8002ea4 ) + 8002ca2: 681b ldr r3, [r3, #0] + 8002ca4: 4a80 ldr r2, [pc, #512] ; (8002ea8 ) + 8002ca6: 7812 ldrb r2, [r2, #0] + 8002ca8: 701a strb r2, [r3, #0] + p_air_packet_tx[PACKET_DEVICE_ID_POS] = gps_air[device_number].device_id[0]; + 8002caa: 4b7f ldr r3, [pc, #508] ; (8002ea8 ) + 8002cac: 781b ldrb r3, [r3, #0] + 8002cae: 4618 mov r0, r3 + 8002cb0: 4b7c ldr r3, [pc, #496] ; (8002ea4 ) + 8002cb2: 681b ldr r3, [r3, #0] + 8002cb4: 1c5a adds r2, r3, #1 + 8002cb6: 497d ldr r1, [pc, #500] ; (8002eac ) + 8002cb8: 4603 mov r3, r0 + 8002cba: 009b lsls r3, r3, #2 + 8002cbc: 4403 add r3, r0 + 8002cbe: 009b lsls r3, r3, #2 + 8002cc0: 440b add r3, r1 + 8002cc2: 781b ldrb r3, [r3, #0] + 8002cc4: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_DEVICE_ID_POS + 1] = gps_air[device_number].device_id[1]; + 8002cc6: 4b78 ldr r3, [pc, #480] ; (8002ea8 ) + 8002cc8: 781b ldrb r3, [r3, #0] + 8002cca: 4618 mov r0, r3 + 8002ccc: 4b75 ldr r3, [pc, #468] ; (8002ea4 ) + 8002cce: 681b ldr r3, [r3, #0] + 8002cd0: 1c9a adds r2, r3, #2 + 8002cd2: 4976 ldr r1, [pc, #472] ; (8002eac ) + 8002cd4: 4603 mov r3, r0 + 8002cd6: 009b lsls r3, r3, #2 + 8002cd8: 4403 add r3, r0 + 8002cda: 009b lsls r3, r3, #2 + 8002cdc: 440b add r3, r1 + 8002cde: 3301 adds r3, #1 + 8002ce0: 781b ldrb r3, [r3, #0] + 8002ce2: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_FLAGS_POS] = gps_air[device_number].flags; + 8002ce4: 4b70 ldr r3, [pc, #448] ; (8002ea8 ) + 8002ce6: 781b ldrb r3, [r3, #0] + 8002ce8: 4618 mov r0, r3 + 8002cea: 4b6e ldr r3, [pc, #440] ; (8002ea4 ) + 8002cec: 681b ldr r3, [r3, #0] + 8002cee: 1cda adds r2, r3, #3 + 8002cf0: 496e ldr r1, [pc, #440] ; (8002eac ) + 8002cf2: 4603 mov r3, r0 + 8002cf4: 009b lsls r3, r3, #2 + 8002cf6: 4403 add r3, r0 + 8002cf8: 009b lsls r3, r3, #2 + 8002cfa: 440b add r3, r1 + 8002cfc: 3302 adds r3, #2 + 8002cfe: 781b ldrb r3, [r3, #0] + 8002d00: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_LATITUDE_POS] = gps_air[device_number].latitude.as_array[0]; + 8002d02: 4b69 ldr r3, [pc, #420] ; (8002ea8 ) + 8002d04: 781b ldrb r3, [r3, #0] + 8002d06: 4618 mov r0, r3 + 8002d08: 4b66 ldr r3, [pc, #408] ; (8002ea4 ) + 8002d0a: 681b ldr r3, [r3, #0] + 8002d0c: 1d1a adds r2, r3, #4 + 8002d0e: 4967 ldr r1, [pc, #412] ; (8002eac ) + 8002d10: 4603 mov r3, r0 + 8002d12: 009b lsls r3, r3, #2 + 8002d14: 4403 add r3, r0 + 8002d16: 009b lsls r3, r3, #2 + 8002d18: 440b add r3, r1 + 8002d1a: 3304 adds r3, #4 + 8002d1c: 781b ldrb r3, [r3, #0] + 8002d1e: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_LATITUDE_POS + 1] = gps_air[device_number].latitude.as_array[1]; + 8002d20: 4b61 ldr r3, [pc, #388] ; (8002ea8 ) + 8002d22: 781b ldrb r3, [r3, #0] + 8002d24: 4618 mov r0, r3 + 8002d26: 4b5f ldr r3, [pc, #380] ; (8002ea4 ) + 8002d28: 681b ldr r3, [r3, #0] + 8002d2a: 1d5a adds r2, r3, #5 + 8002d2c: 495f ldr r1, [pc, #380] ; (8002eac ) + 8002d2e: 4603 mov r3, r0 + 8002d30: 009b lsls r3, r3, #2 + 8002d32: 4403 add r3, r0 + 8002d34: 009b lsls r3, r3, #2 + 8002d36: 440b add r3, r1 + 8002d38: 3305 adds r3, #5 + 8002d3a: 781b ldrb r3, [r3, #0] + 8002d3c: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_LATITUDE_POS + 2] = gps_air[device_number].latitude.as_array[2]; + 8002d3e: 4b5a ldr r3, [pc, #360] ; (8002ea8 ) + 8002d40: 781b ldrb r3, [r3, #0] + 8002d42: 4618 mov r0, r3 + 8002d44: 4b57 ldr r3, [pc, #348] ; (8002ea4 ) + 8002d46: 681b ldr r3, [r3, #0] + 8002d48: 1d9a adds r2, r3, #6 + 8002d4a: 4958 ldr r1, [pc, #352] ; (8002eac ) + 8002d4c: 4603 mov r3, r0 + 8002d4e: 009b lsls r3, r3, #2 + 8002d50: 4403 add r3, r0 + 8002d52: 009b lsls r3, r3, #2 + 8002d54: 440b add r3, r1 + 8002d56: 3306 adds r3, #6 + 8002d58: 781b ldrb r3, [r3, #0] + 8002d5a: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_LATITUDE_POS + 3] = gps_air[device_number].latitude.as_array[3]; + 8002d5c: 4b52 ldr r3, [pc, #328] ; (8002ea8 ) + 8002d5e: 781b ldrb r3, [r3, #0] + 8002d60: 4618 mov r0, r3 + 8002d62: 4b50 ldr r3, [pc, #320] ; (8002ea4 ) + 8002d64: 681b ldr r3, [r3, #0] + 8002d66: 1dda adds r2, r3, #7 + 8002d68: 4950 ldr r1, [pc, #320] ; (8002eac ) + 8002d6a: 4603 mov r3, r0 + 8002d6c: 009b lsls r3, r3, #2 + 8002d6e: 4403 add r3, r0 + 8002d70: 009b lsls r3, r3, #2 + 8002d72: 440b add r3, r1 + 8002d74: 3307 adds r3, #7 + 8002d76: 781b ldrb r3, [r3, #0] + 8002d78: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_LONGITUDE_POS] = gps_air[device_number].longitude.as_array[0]; + 8002d7a: 4b4b ldr r3, [pc, #300] ; (8002ea8 ) + 8002d7c: 781b ldrb r3, [r3, #0] + 8002d7e: 4618 mov r0, r3 + 8002d80: 4b48 ldr r3, [pc, #288] ; (8002ea4 ) + 8002d82: 681b ldr r3, [r3, #0] + 8002d84: f103 0208 add.w r2, r3, #8 + 8002d88: 4948 ldr r1, [pc, #288] ; (8002eac ) + 8002d8a: 4603 mov r3, r0 + 8002d8c: 009b lsls r3, r3, #2 + 8002d8e: 4403 add r3, r0 + 8002d90: 009b lsls r3, r3, #2 + 8002d92: 440b add r3, r1 + 8002d94: 3308 adds r3, #8 + 8002d96: 781b ldrb r3, [r3, #0] + 8002d98: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_LONGITUDE_POS + 1] = gps_air[device_number].longitude.as_array[1]; + 8002d9a: 4b43 ldr r3, [pc, #268] ; (8002ea8 ) + 8002d9c: 781b ldrb r3, [r3, #0] + 8002d9e: 4618 mov r0, r3 + 8002da0: 4b40 ldr r3, [pc, #256] ; (8002ea4 ) + 8002da2: 681b ldr r3, [r3, #0] + 8002da4: f103 0209 add.w r2, r3, #9 + 8002da8: 4940 ldr r1, [pc, #256] ; (8002eac ) + 8002daa: 4603 mov r3, r0 + 8002dac: 009b lsls r3, r3, #2 + 8002dae: 4403 add r3, r0 + 8002db0: 009b lsls r3, r3, #2 + 8002db2: 440b add r3, r1 + 8002db4: 3309 adds r3, #9 + 8002db6: 781b ldrb r3, [r3, #0] + 8002db8: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_LONGITUDE_POS + 2] = gps_air[device_number].longitude.as_array[2]; + 8002dba: 4b3b ldr r3, [pc, #236] ; (8002ea8 ) + 8002dbc: 781b ldrb r3, [r3, #0] + 8002dbe: 4618 mov r0, r3 + 8002dc0: 4b38 ldr r3, [pc, #224] ; (8002ea4 ) + 8002dc2: 681b ldr r3, [r3, #0] + 8002dc4: f103 020a add.w r2, r3, #10 + 8002dc8: 4938 ldr r1, [pc, #224] ; (8002eac ) + 8002dca: 4603 mov r3, r0 + 8002dcc: 009b lsls r3, r3, #2 + 8002dce: 4403 add r3, r0 + 8002dd0: 009b lsls r3, r3, #2 + 8002dd2: 440b add r3, r1 + 8002dd4: 330a adds r3, #10 + 8002dd6: 781b ldrb r3, [r3, #0] + 8002dd8: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_LONGITUDE_POS + 3] = gps_air[device_number].longitude.as_array[3]; + 8002dda: 4b33 ldr r3, [pc, #204] ; (8002ea8 ) + 8002ddc: 781b ldrb r3, [r3, #0] + 8002dde: 4618 mov r0, r3 + 8002de0: 4b30 ldr r3, [pc, #192] ; (8002ea4 ) + 8002de2: 681b ldr r3, [r3, #0] + 8002de4: f103 020b add.w r2, r3, #11 + 8002de8: 4930 ldr r1, [pc, #192] ; (8002eac ) + 8002dea: 4603 mov r3, r0 + 8002dec: 009b lsls r3, r3, #2 + 8002dee: 4403 add r3, r0 + 8002df0: 009b lsls r3, r3, #2 + 8002df2: 440b add r3, r1 + 8002df4: 330b adds r3, #11 + 8002df6: 781b ldrb r3, [r3, #0] + 8002df8: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_ALTITUDE_POS] = gps_air[device_number].altitude.as_array[0]; + 8002dfa: 4b2b ldr r3, [pc, #172] ; (8002ea8 ) + 8002dfc: 781b ldrb r3, [r3, #0] + 8002dfe: 4618 mov r0, r3 + 8002e00: 4b28 ldr r3, [pc, #160] ; (8002ea4 ) + 8002e02: 681b ldr r3, [r3, #0] + 8002e04: f103 020c add.w r2, r3, #12 + 8002e08: 4928 ldr r1, [pc, #160] ; (8002eac ) + 8002e0a: 4603 mov r3, r0 + 8002e0c: 009b lsls r3, r3, #2 + 8002e0e: 4403 add r3, r0 + 8002e10: 009b lsls r3, r3, #2 + 8002e12: 440b add r3, r1 + 8002e14: 330c adds r3, #12 + 8002e16: 781b ldrb r3, [r3, #0] + 8002e18: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_ALTITUDE_POS + 1] = gps_air[device_number].altitude.as_array[1]; + 8002e1a: 4b23 ldr r3, [pc, #140] ; (8002ea8 ) + 8002e1c: 781b ldrb r3, [r3, #0] + 8002e1e: 4618 mov r0, r3 + 8002e20: 4b20 ldr r3, [pc, #128] ; (8002ea4 ) + 8002e22: 681b ldr r3, [r3, #0] + 8002e24: f103 020d add.w r2, r3, #13 + 8002e28: 4920 ldr r1, [pc, #128] ; (8002eac ) + 8002e2a: 4603 mov r3, r0 + 8002e2c: 009b lsls r3, r3, #2 + 8002e2e: 4403 add r3, r0 + 8002e30: 009b lsls r3, r3, #2 + 8002e32: 440b add r3, r1 + 8002e34: 330d adds r3, #13 + 8002e36: 781b ldrb r3, [r3, #0] + 8002e38: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_SPEED_POS] = gps_air[device_number].speed; + 8002e3a: 4b1b ldr r3, [pc, #108] ; (8002ea8 ) + 8002e3c: 781b ldrb r3, [r3, #0] + 8002e3e: 4618 mov r0, r3 + 8002e40: 4b18 ldr r3, [pc, #96] ; (8002ea4 ) + 8002e42: 681b ldr r3, [r3, #0] + 8002e44: f103 020e add.w r2, r3, #14 + 8002e48: 4918 ldr r1, [pc, #96] ; (8002eac ) + 8002e4a: 4603 mov r3, r0 + 8002e4c: 009b lsls r3, r3, #2 + 8002e4e: 4403 add r3, r0 + 8002e50: 009b lsls r3, r3, #2 + 8002e52: 440b add r3, r1 + 8002e54: 330e adds r3, #14 + 8002e56: 781b ldrb r3, [r3, #0] + 8002e58: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_COURSE_POS] = gps_air[device_number].course.as_array[0]; + 8002e5a: 4b13 ldr r3, [pc, #76] ; (8002ea8 ) + 8002e5c: 781b ldrb r3, [r3, #0] + 8002e5e: 4618 mov r0, r3 + 8002e60: 4b10 ldr r3, [pc, #64] ; (8002ea4 ) + 8002e62: 681b ldr r3, [r3, #0] + 8002e64: f103 020f add.w r2, r3, #15 + 8002e68: 4910 ldr r1, [pc, #64] ; (8002eac ) + 8002e6a: 4603 mov r3, r0 + 8002e6c: 009b lsls r3, r3, #2 + 8002e6e: 4403 add r3, r0 + 8002e70: 009b lsls r3, r3, #2 + 8002e72: 440b add r3, r1 + 8002e74: 3310 adds r3, #16 + 8002e76: 781b ldrb r3, [r3, #0] + 8002e78: 7013 strb r3, [r2, #0] + p_air_packet_tx[PACKET_COURSE_POS + 1] = gps_air[device_number].course.as_array[1]; + 8002e7a: 4b0b ldr r3, [pc, #44] ; (8002ea8 ) + 8002e7c: 781b ldrb r3, [r3, #0] + 8002e7e: 4618 mov r0, r3 + 8002e80: 4b08 ldr r3, [pc, #32] ; (8002ea4 ) + 8002e82: 681b ldr r3, [r3, #0] + 8002e84: f103 0210 add.w r2, r3, #16 + 8002e88: 4908 ldr r1, [pc, #32] ; (8002eac ) + 8002e8a: 4603 mov r3, r0 + 8002e8c: 009b lsls r3, r3, #2 + 8002e8e: 4403 add r3, r0 + 8002e90: 009b lsls r3, r3, #2 + 8002e92: 440b add r3, r1 + 8002e94: 3311 adds r3, #17 + 8002e96: 781b ldrb r3, [r3, #0] + 8002e98: 7013 strb r3, [r2, #0] +} + 8002e9a: bf00 nop + 8002e9c: 46bd mov sp, r7 + 8002e9e: bc80 pop {r7} + 8002ea0: 4770 bx lr + 8002ea2: bf00 nop + 8002ea4: 2000073c .word 0x2000073c + 8002ea8: 20000738 .word 0x20000738 + 8002eac: 20000740 .word 0x20000740 + +08002eb0 : + + + +//Copy RX air packet data to the gps_air struct +uint8_t fill_struct_with_air_packet_data(uint32_t uptime) +{ + 8002eb0: b480 push {r7} + 8002eb2: b085 sub sp, #20 + 8002eb4: af00 add r7, sp, #0 + 8002eb6: 6078 str r0, [r7, #4] + uint8_t rx_device = p_air_packet_rx[PACKET_DEVICE_NUMBER_POS]; //extract device number from received packet + 8002eb8: 4b76 ldr r3, [pc, #472] ; (8003094 ) + 8002eba: 681b ldr r3, [r3, #0] + 8002ebc: 781b ldrb r3, [r3, #0] + 8002ebe: 73fb strb r3, [r7, #15] + + dev_aux[rx_device].exist_flag = 1; + 8002ec0: 7bfa ldrb r2, [r7, #15] + 8002ec2: 4975 ldr r1, [pc, #468] ; (8003098 ) + 8002ec4: 4613 mov r3, r2 + 8002ec6: 005b lsls r3, r3, #1 + 8002ec8: 4413 add r3, r2 + 8002eca: 00db lsls r3, r3, #3 + 8002ecc: 440b add r3, r1 + 8002ece: 2201 movs r2, #1 + 8002ed0: 701a strb r2, [r3, #0] + dev_aux[rx_device].timestamp = uptime; + 8002ed2: 7bfa ldrb r2, [r7, #15] + 8002ed4: 4970 ldr r1, [pc, #448] ; (8003098 ) + 8002ed6: 4613 mov r3, r2 + 8002ed8: 005b lsls r3, r3, #1 + 8002eda: 4413 add r3, r2 + 8002edc: 00db lsls r3, r3, #3 + 8002ede: 440b add r3, r1 + 8002ee0: 3304 adds r3, #4 + 8002ee2: 687a ldr r2, [r7, #4] + 8002ee4: 601a str r2, [r3, #0] + gps_air[rx_device].device_id[0] = p_air_packet_rx[PACKET_DEVICE_ID_POS]; + 8002ee6: 4b6b ldr r3, [pc, #428] ; (8003094 ) + 8002ee8: 681b ldr r3, [r3, #0] + 8002eea: 3301 adds r3, #1 + 8002eec: 7bfa ldrb r2, [r7, #15] + 8002eee: 7818 ldrb r0, [r3, #0] + 8002ef0: 496a ldr r1, [pc, #424] ; (800309c ) + 8002ef2: 4613 mov r3, r2 + 8002ef4: 009b lsls r3, r3, #2 + 8002ef6: 4413 add r3, r2 + 8002ef8: 009b lsls r3, r3, #2 + 8002efa: 440b add r3, r1 + 8002efc: 4602 mov r2, r0 + 8002efe: 701a strb r2, [r3, #0] + gps_air[rx_device].device_id[1] = p_air_packet_rx[PACKET_DEVICE_ID_POS + 1]; + 8002f00: 4b64 ldr r3, [pc, #400] ; (8003094 ) + 8002f02: 681b ldr r3, [r3, #0] + 8002f04: 3302 adds r3, #2 + 8002f06: 7bfa ldrb r2, [r7, #15] + 8002f08: 7818 ldrb r0, [r3, #0] + 8002f0a: 4964 ldr r1, [pc, #400] ; (800309c ) + 8002f0c: 4613 mov r3, r2 + 8002f0e: 009b lsls r3, r3, #2 + 8002f10: 4413 add r3, r2 + 8002f12: 009b lsls r3, r3, #2 + 8002f14: 440b add r3, r1 + 8002f16: 3301 adds r3, #1 + 8002f18: 4602 mov r2, r0 + 8002f1a: 701a strb r2, [r3, #0] + gps_air[rx_device].flags = p_air_packet_rx[PACKET_FLAGS_POS]; + 8002f1c: 4b5d ldr r3, [pc, #372] ; (8003094 ) + 8002f1e: 681b ldr r3, [r3, #0] + 8002f20: 7bfa ldrb r2, [r7, #15] + 8002f22: 78d8 ldrb r0, [r3, #3] + 8002f24: 495d ldr r1, [pc, #372] ; (800309c ) + 8002f26: 4613 mov r3, r2 + 8002f28: 009b lsls r3, r3, #2 + 8002f2a: 4413 add r3, r2 + 8002f2c: 009b lsls r3, r3, #2 + 8002f2e: 440b add r3, r1 + 8002f30: 3302 adds r3, #2 + 8002f32: 4602 mov r2, r0 + 8002f34: 701a strb r2, [r3, #0] + gps_air[rx_device].latitude.as_array[0] = p_air_packet_rx[PACKET_LATITUDE_POS]; + 8002f36: 4b57 ldr r3, [pc, #348] ; (8003094 ) + 8002f38: 681b ldr r3, [r3, #0] + 8002f3a: 7bfa ldrb r2, [r7, #15] + 8002f3c: 7918 ldrb r0, [r3, #4] + 8002f3e: 4957 ldr r1, [pc, #348] ; (800309c ) + 8002f40: 4613 mov r3, r2 + 8002f42: 009b lsls r3, r3, #2 + 8002f44: 4413 add r3, r2 + 8002f46: 009b lsls r3, r3, #2 + 8002f48: 440b add r3, r1 + 8002f4a: 3304 adds r3, #4 + 8002f4c: 4602 mov r2, r0 + 8002f4e: 701a strb r2, [r3, #0] + gps_air[rx_device].latitude.as_array[1] = p_air_packet_rx[PACKET_LATITUDE_POS + 1]; + 8002f50: 4b50 ldr r3, [pc, #320] ; (8003094 ) + 8002f52: 681b ldr r3, [r3, #0] + 8002f54: 7bfa ldrb r2, [r7, #15] + 8002f56: 7958 ldrb r0, [r3, #5] + 8002f58: 4950 ldr r1, [pc, #320] ; (800309c ) + 8002f5a: 4613 mov r3, r2 + 8002f5c: 009b lsls r3, r3, #2 + 8002f5e: 4413 add r3, r2 + 8002f60: 009b lsls r3, r3, #2 + 8002f62: 440b add r3, r1 + 8002f64: 3305 adds r3, #5 + 8002f66: 4602 mov r2, r0 + 8002f68: 701a strb r2, [r3, #0] + gps_air[rx_device].latitude.as_array[2] = p_air_packet_rx[PACKET_LATITUDE_POS + 2]; + 8002f6a: 4b4a ldr r3, [pc, #296] ; (8003094 ) + 8002f6c: 681b ldr r3, [r3, #0] + 8002f6e: 7bfa ldrb r2, [r7, #15] + 8002f70: 7998 ldrb r0, [r3, #6] + 8002f72: 494a ldr r1, [pc, #296] ; (800309c ) + 8002f74: 4613 mov r3, r2 + 8002f76: 009b lsls r3, r3, #2 + 8002f78: 4413 add r3, r2 + 8002f7a: 009b lsls r3, r3, #2 + 8002f7c: 440b add r3, r1 + 8002f7e: 3306 adds r3, #6 + 8002f80: 4602 mov r2, r0 + 8002f82: 701a strb r2, [r3, #0] + gps_air[rx_device].latitude.as_array[3] = p_air_packet_rx[PACKET_LATITUDE_POS + 3]; + 8002f84: 4b43 ldr r3, [pc, #268] ; (8003094 ) + 8002f86: 681b ldr r3, [r3, #0] + 8002f88: 7bfa ldrb r2, [r7, #15] + 8002f8a: 79d8 ldrb r0, [r3, #7] + 8002f8c: 4943 ldr r1, [pc, #268] ; (800309c ) + 8002f8e: 4613 mov r3, r2 + 8002f90: 009b lsls r3, r3, #2 + 8002f92: 4413 add r3, r2 + 8002f94: 009b lsls r3, r3, #2 + 8002f96: 440b add r3, r1 + 8002f98: 3307 adds r3, #7 + 8002f9a: 4602 mov r2, r0 + 8002f9c: 701a strb r2, [r3, #0] + gps_air[rx_device].longitude.as_array[0] = p_air_packet_rx[PACKET_LONGITUDE_POS]; + 8002f9e: 4b3d ldr r3, [pc, #244] ; (8003094 ) + 8002fa0: 681b ldr r3, [r3, #0] + 8002fa2: 7bfa ldrb r2, [r7, #15] + 8002fa4: 7a18 ldrb r0, [r3, #8] + 8002fa6: 493d ldr r1, [pc, #244] ; (800309c ) + 8002fa8: 4613 mov r3, r2 + 8002faa: 009b lsls r3, r3, #2 + 8002fac: 4413 add r3, r2 + 8002fae: 009b lsls r3, r3, #2 + 8002fb0: 440b add r3, r1 + 8002fb2: 3308 adds r3, #8 + 8002fb4: 4602 mov r2, r0 + 8002fb6: 701a strb r2, [r3, #0] + gps_air[rx_device].longitude.as_array[1] = p_air_packet_rx[PACKET_LONGITUDE_POS + 1]; + 8002fb8: 4b36 ldr r3, [pc, #216] ; (8003094 ) + 8002fba: 681b ldr r3, [r3, #0] + 8002fbc: 7bfa ldrb r2, [r7, #15] + 8002fbe: 7a58 ldrb r0, [r3, #9] + 8002fc0: 4936 ldr r1, [pc, #216] ; (800309c ) + 8002fc2: 4613 mov r3, r2 + 8002fc4: 009b lsls r3, r3, #2 + 8002fc6: 4413 add r3, r2 + 8002fc8: 009b lsls r3, r3, #2 + 8002fca: 440b add r3, r1 + 8002fcc: 3309 adds r3, #9 + 8002fce: 4602 mov r2, r0 + 8002fd0: 701a strb r2, [r3, #0] + gps_air[rx_device].longitude.as_array[2] = p_air_packet_rx[PACKET_LONGITUDE_POS + 2]; + 8002fd2: 4b30 ldr r3, [pc, #192] ; (8003094 ) + 8002fd4: 681b ldr r3, [r3, #0] + 8002fd6: 7bfa ldrb r2, [r7, #15] + 8002fd8: 7a98 ldrb r0, [r3, #10] + 8002fda: 4930 ldr r1, [pc, #192] ; (800309c ) + 8002fdc: 4613 mov r3, r2 + 8002fde: 009b lsls r3, r3, #2 + 8002fe0: 4413 add r3, r2 + 8002fe2: 009b lsls r3, r3, #2 + 8002fe4: 440b add r3, r1 + 8002fe6: 330a adds r3, #10 + 8002fe8: 4602 mov r2, r0 + 8002fea: 701a strb r2, [r3, #0] + gps_air[rx_device].longitude.as_array[3] = p_air_packet_rx[PACKET_LONGITUDE_POS + 3]; + 8002fec: 4b29 ldr r3, [pc, #164] ; (8003094 ) + 8002fee: 681b ldr r3, [r3, #0] + 8002ff0: 7bfa ldrb r2, [r7, #15] + 8002ff2: 7ad8 ldrb r0, [r3, #11] + 8002ff4: 4929 ldr r1, [pc, #164] ; (800309c ) + 8002ff6: 4613 mov r3, r2 + 8002ff8: 009b lsls r3, r3, #2 + 8002ffa: 4413 add r3, r2 + 8002ffc: 009b lsls r3, r3, #2 + 8002ffe: 440b add r3, r1 + 8003000: 330b adds r3, #11 + 8003002: 4602 mov r2, r0 + 8003004: 701a strb r2, [r3, #0] + gps_air[rx_device].altitude.as_array[0] = p_air_packet_rx[PACKET_ALTITUDE_POS]; + 8003006: 4b23 ldr r3, [pc, #140] ; (8003094 ) + 8003008: 681b ldr r3, [r3, #0] + 800300a: 7bfa ldrb r2, [r7, #15] + 800300c: 7b18 ldrb r0, [r3, #12] + 800300e: 4923 ldr r1, [pc, #140] ; (800309c ) + 8003010: 4613 mov r3, r2 + 8003012: 009b lsls r3, r3, #2 + 8003014: 4413 add r3, r2 + 8003016: 009b lsls r3, r3, #2 + 8003018: 440b add r3, r1 + 800301a: 330c adds r3, #12 + 800301c: 4602 mov r2, r0 + 800301e: 701a strb r2, [r3, #0] + gps_air[rx_device].altitude.as_array[1] = p_air_packet_rx[PACKET_ALTITUDE_POS + 1]; + 8003020: 4b1c ldr r3, [pc, #112] ; (8003094 ) + 8003022: 681b ldr r3, [r3, #0] + 8003024: 7bfa ldrb r2, [r7, #15] + 8003026: 7b58 ldrb r0, [r3, #13] + 8003028: 491c ldr r1, [pc, #112] ; (800309c ) + 800302a: 4613 mov r3, r2 + 800302c: 009b lsls r3, r3, #2 + 800302e: 4413 add r3, r2 + 8003030: 009b lsls r3, r3, #2 + 8003032: 440b add r3, r1 + 8003034: 330d adds r3, #13 + 8003036: 4602 mov r2, r0 + 8003038: 701a strb r2, [r3, #0] + gps_air[rx_device].speed = p_air_packet_rx[PACKET_SPEED_POS]; + 800303a: 4b16 ldr r3, [pc, #88] ; (8003094 ) + 800303c: 681b ldr r3, [r3, #0] + 800303e: 7bfa ldrb r2, [r7, #15] + 8003040: 7b98 ldrb r0, [r3, #14] + 8003042: 4916 ldr r1, [pc, #88] ; (800309c ) + 8003044: 4613 mov r3, r2 + 8003046: 009b lsls r3, r3, #2 + 8003048: 4413 add r3, r2 + 800304a: 009b lsls r3, r3, #2 + 800304c: 440b add r3, r1 + 800304e: 330e adds r3, #14 + 8003050: 4602 mov r2, r0 + 8003052: 701a strb r2, [r3, #0] + gps_air[rx_device].course.as_array[0] = p_air_packet_rx[PACKET_COURSE_POS]; + 8003054: 4b0f ldr r3, [pc, #60] ; (8003094 ) + 8003056: 681b ldr r3, [r3, #0] + 8003058: 7bfa ldrb r2, [r7, #15] + 800305a: 7bd8 ldrb r0, [r3, #15] + 800305c: 490f ldr r1, [pc, #60] ; (800309c ) + 800305e: 4613 mov r3, r2 + 8003060: 009b lsls r3, r3, #2 + 8003062: 4413 add r3, r2 + 8003064: 009b lsls r3, r3, #2 + 8003066: 440b add r3, r1 + 8003068: 3310 adds r3, #16 + 800306a: 4602 mov r2, r0 + 800306c: 701a strb r2, [r3, #0] + gps_air[rx_device].course.as_array[1] = p_air_packet_rx[PACKET_COURSE_POS + 1]; + 800306e: 4b09 ldr r3, [pc, #36] ; (8003094 ) + 8003070: 681b ldr r3, [r3, #0] + 8003072: 7bfa ldrb r2, [r7, #15] + 8003074: 7c18 ldrb r0, [r3, #16] + 8003076: 4909 ldr r1, [pc, #36] ; (800309c ) + 8003078: 4613 mov r3, r2 + 800307a: 009b lsls r3, r3, #2 + 800307c: 4413 add r3, r2 + 800307e: 009b lsls r3, r3, #2 + 8003080: 440b add r3, r1 + 8003082: 3311 adds r3, #17 + 8003084: 4602 mov r2, r0 + 8003086: 701a strb r2, [r3, #0] + + return rx_device; + 8003088: 7bfb ldrb r3, [r7, #15] +} + 800308a: 4618 mov r0, r3 + 800308c: 3714 adds r7, #20 + 800308e: 46bd mov sp, r7 + 8003090: bc80 pop {r7} + 8003092: 4770 bx lr + 8003094: 20000618 .word 0x20000618 + 8003098: 20000620 .word 0x20000620 + 800309c: 20000740 .word 0x20000740 + +080030a0 : +// Heart of the device <3 +//Calculates distance between two GPS points (using haversine formula) +//Calculates heading between two GPS points (loxodrome, or rhumb line) +//Calculates altitude difference +void calc_relative_position(uint8_t another_device) +{ + 80030a0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 80030a4: b08f sub sp, #60 ; 0x3c + 80030a6: af00 add r7, sp, #0 + 80030a8: 4603 mov r3, r0 + 80030aa: 71fb strb r3, [r7, #7] + double lat1, lat2, lon1, lon2; + double distance, heading; + + //my position + lat1 = p_gps_num->latitude.in_rad; + 80030ac: 4bc6 ldr r3, [pc, #792] ; (80033c8 ) + 80030ae: 681b ldr r3, [r3, #0] + 80030b0: f103 0410 add.w r4, r3, #16 + 80030b4: e9d4 3400 ldrd r3, r4, [r4] + 80030b8: e9c7 3406 strd r3, r4, [r7, #24] + lon1 = p_gps_num->longitude.in_rad; + 80030bc: 4bc2 ldr r3, [pc, #776] ; (80033c8 ) + 80030be: 681b ldr r3, [r3, #0] + 80030c0: f103 0420 add.w r4, r3, #32 + 80030c4: e9d4 3400 ldrd r3, r4, [r4] + 80030c8: e9c7 3404 strd r3, r4, [r7, #16] + + //position of the device to calculate relative position + lat2 = gps_air[another_device].latitude.as_float * deg_to_rad; + 80030cc: 79fa ldrb r2, [r7, #7] + 80030ce: 49bf ldr r1, [pc, #764] ; (80033cc ) + 80030d0: 4613 mov r3, r2 + 80030d2: 009b lsls r3, r3, #2 + 80030d4: 4413 add r3, r2 + 80030d6: 009b lsls r3, r3, #2 + 80030d8: 440b add r3, r1 + 80030da: 3304 adds r3, #4 + 80030dc: 681b ldr r3, [r3, #0] + 80030de: 4618 mov r0, r3 + 80030e0: f7fd f9aa bl 8000438 <__aeabi_f2d> + 80030e4: a4ae add r4, pc, #696 ; (adr r4, 80033a0 ) + 80030e6: e9d4 3400 ldrd r3, r4, [r4] + 80030ea: 461a mov r2, r3 + 80030ec: 4623 mov r3, r4 + 80030ee: f7fd f9fb bl 80004e8 <__aeabi_dmul> + 80030f2: 4603 mov r3, r0 + 80030f4: 460c mov r4, r1 + 80030f6: e9c7 340c strd r3, r4, [r7, #48] ; 0x30 + lon2 = gps_air[another_device].longitude.as_float * deg_to_rad; + 80030fa: 79fa ldrb r2, [r7, #7] + 80030fc: 49b3 ldr r1, [pc, #716] ; (80033cc ) + 80030fe: 4613 mov r3, r2 + 8003100: 009b lsls r3, r3, #2 + 8003102: 4413 add r3, r2 + 8003104: 009b lsls r3, r3, #2 + 8003106: 440b add r3, r1 + 8003108: 3308 adds r3, #8 + 800310a: 681b ldr r3, [r3, #0] + 800310c: 4618 mov r0, r3 + 800310e: f7fd f993 bl 8000438 <__aeabi_f2d> + 8003112: a4a3 add r4, pc, #652 ; (adr r4, 80033a0 ) + 8003114: e9d4 3400 ldrd r3, r4, [r4] + 8003118: 461a mov r2, r3 + 800311a: 4623 mov r3, r4 + 800311c: f7fd f9e4 bl 80004e8 <__aeabi_dmul> + 8003120: 4603 mov r3, r0 + 8003122: 460c mov r4, r1 + 8003124: e9c7 340a strd r3, r4, [r7, #40] ; 0x28 + + if (lat1 == lat2) + 8003128: e9d7 230c ldrd r2, r3, [r7, #48] ; 0x30 + 800312c: e9d7 0106 ldrd r0, r1, [r7, #24] + 8003130: f7fd fc42 bl 80009b8 <__aeabi_dcmpeq> + 8003134: 4603 mov r3, r0 + 8003136: 2b00 cmp r3, #0 + 8003138: d00a beq.n 8003150 + { + lat2 += 0.00000001; //slightly shift the position + 800313a: a39b add r3, pc, #620 ; (adr r3, 80033a8 ) + 800313c: e9d3 2300 ldrd r2, r3, [r3] + 8003140: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 + 8003144: f7fd f81a bl 800017c <__adddf3> + 8003148: 4603 mov r3, r0 + 800314a: 460c mov r4, r1 + 800314c: e9c7 340c strd r3, r4, [r7, #48] ; 0x30 + } + + if (lon1 == lon2) + 8003150: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 + 8003154: e9d7 0104 ldrd r0, r1, [r7, #16] + 8003158: f7fd fc2e bl 80009b8 <__aeabi_dcmpeq> + 800315c: 4603 mov r3, r0 + 800315e: 2b00 cmp r3, #0 + 8003160: d00a beq.n 8003178 + { + lon2 += 0.00000001; //slightly shift the position + 8003162: a391 add r3, pc, #580 ; (adr r3, 80033a8 ) + 8003164: e9d3 2300 ldrd r2, r3, [r3] + 8003168: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28 + 800316c: f7fd f806 bl 800017c <__adddf3> + 8003170: 4603 mov r3, r0 + 8003172: 460c mov r4, r1 + 8003174: e9c7 340a strd r3, r4, [r7, #40] ; 0x28 + } + + distance = twice_mean_earth_radius * + asin( sqrt( pow(sin((lat2 - lat1) / 2), 2) + + 8003178: e9d7 2306 ldrd r2, r3, [r7, #24] + 800317c: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 + 8003180: f7fc fffa bl 8000178 <__aeabi_dsub> + 8003184: 4603 mov r3, r0 + 8003186: 460c mov r4, r1 + 8003188: 4618 mov r0, r3 + 800318a: 4621 mov r1, r4 + 800318c: f04f 0200 mov.w r2, #0 + 8003190: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8003194: f7fd fad2 bl 800073c <__aeabi_ddiv> + 8003198: 4603 mov r3, r0 + 800319a: 460c mov r4, r1 + 800319c: 4618 mov r0, r3 + 800319e: 4621 mov r1, r4 + 80031a0: f006 fdb2 bl 8009d08 + 80031a4: f04f 0200 mov.w r2, #0 + 80031a8: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 80031ac: f006 fede bl 8009f6c + 80031b0: 4604 mov r4, r0 + 80031b2: 460d mov r5, r1 + cos(lat2) * cos(lat1) * pow(sin((lon2 - lon1) / 2), 2))); + 80031b4: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 + 80031b8: f006 fd6c bl 8009c94 + 80031bc: 4680 mov r8, r0 + 80031be: 4689 mov r9, r1 + 80031c0: e9d7 0106 ldrd r0, r1, [r7, #24] + 80031c4: f006 fd66 bl 8009c94 + 80031c8: 4602 mov r2, r0 + 80031ca: 460b mov r3, r1 + 80031cc: 4640 mov r0, r8 + 80031ce: 4649 mov r1, r9 + 80031d0: f7fd f98a bl 80004e8 <__aeabi_dmul> + 80031d4: 4602 mov r2, r0 + 80031d6: 460b mov r3, r1 + 80031d8: 4690 mov r8, r2 + 80031da: 4699 mov r9, r3 + 80031dc: e9d7 2304 ldrd r2, r3, [r7, #16] + 80031e0: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28 + 80031e4: f7fc ffc8 bl 8000178 <__aeabi_dsub> + 80031e8: 4602 mov r2, r0 + 80031ea: 460b mov r3, r1 + 80031ec: 4610 mov r0, r2 + 80031ee: 4619 mov r1, r3 + 80031f0: f04f 0200 mov.w r2, #0 + 80031f4: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 80031f8: f7fd faa0 bl 800073c <__aeabi_ddiv> + 80031fc: 4602 mov r2, r0 + 80031fe: 460b mov r3, r1 + 8003200: 4610 mov r0, r2 + 8003202: 4619 mov r1, r3 + 8003204: f006 fd80 bl 8009d08 + 8003208: f04f 0200 mov.w r2, #0 + 800320c: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8003210: f006 feac bl 8009f6c + 8003214: 4602 mov r2, r0 + 8003216: 460b mov r3, r1 + 8003218: 4640 mov r0, r8 + 800321a: 4649 mov r1, r9 + 800321c: f7fd f964 bl 80004e8 <__aeabi_dmul> + 8003220: 4602 mov r2, r0 + 8003222: 460b mov r3, r1 + asin( sqrt( pow(sin((lat2 - lat1) / 2), 2) + + 8003224: 4620 mov r0, r4 + 8003226: 4629 mov r1, r5 + 8003228: f7fc ffa8 bl 800017c <__adddf3> + 800322c: 4603 mov r3, r0 + 800322e: 460c mov r4, r1 + 8003230: 4618 mov r0, r3 + 8003232: 4621 mov r1, r4 + 8003234: f006 fff6 bl 800a224 + 8003238: 4603 mov r3, r0 + 800323a: 460c mov r4, r1 + 800323c: 4618 mov r0, r3 + 800323e: 4621 mov r1, r4 + 8003240: f006 fdc6 bl 8009dd0 + distance = twice_mean_earth_radius * + 8003244: a45a add r4, pc, #360 ; (adr r4, 80033b0 ) + 8003246: e9d4 3400 ldrd r3, r4, [r4] + 800324a: 461a mov r2, r3 + 800324c: 4623 mov r3, r4 + 800324e: f7fd f94b bl 80004e8 <__aeabi_dmul> + 8003252: 4603 mov r3, r0 + 8003254: 460c mov r4, r1 + 8003256: e9c7 3402 strd r3, r4, [r7, #8] + + heading = atan((lon2 - lon1) / + 800325a: e9d7 2304 ldrd r2, r3, [r7, #16] + 800325e: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28 + 8003262: f7fc ff89 bl 8000178 <__aeabi_dsub> + 8003266: 4603 mov r3, r0 + 8003268: 460c mov r4, r1 + 800326a: 461d mov r5, r3 + 800326c: 4626 mov r6, r4 + log(tan(pi_div_by_4 + lat2 / 2) / tan(pi_div_by_4 + lat1 / 2))); + 800326e: f04f 0200 mov.w r2, #0 + 8003272: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8003276: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 + 800327a: f7fd fa5f bl 800073c <__aeabi_ddiv> + 800327e: 4603 mov r3, r0 + 8003280: 460c mov r4, r1 + 8003282: 4618 mov r0, r3 + 8003284: 4621 mov r1, r4 + 8003286: a44c add r4, pc, #304 ; (adr r4, 80033b8 ) + 8003288: e9d4 3400 ldrd r3, r4, [r4] + 800328c: 461a mov r2, r3 + 800328e: 4623 mov r3, r4 + 8003290: f7fc ff74 bl 800017c <__adddf3> + 8003294: 4603 mov r3, r0 + 8003296: 460c mov r4, r1 + 8003298: 4618 mov r0, r3 + 800329a: 4621 mov r1, r4 + 800329c: f006 fd6e bl 8009d7c + 80032a0: 4680 mov r8, r0 + 80032a2: 4689 mov r9, r1 + 80032a4: f04f 0200 mov.w r2, #0 + 80032a8: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 80032ac: e9d7 0106 ldrd r0, r1, [r7, #24] + 80032b0: f7fd fa44 bl 800073c <__aeabi_ddiv> + 80032b4: 4603 mov r3, r0 + 80032b6: 460c mov r4, r1 + 80032b8: 4618 mov r0, r3 + 80032ba: 4621 mov r1, r4 + 80032bc: a43e add r4, pc, #248 ; (adr r4, 80033b8 ) + 80032be: e9d4 3400 ldrd r3, r4, [r4] + 80032c2: 461a mov r2, r3 + 80032c4: 4623 mov r3, r4 + 80032c6: f7fc ff59 bl 800017c <__adddf3> + 80032ca: 4603 mov r3, r0 + 80032cc: 460c mov r4, r1 + 80032ce: 4618 mov r0, r3 + 80032d0: 4621 mov r1, r4 + 80032d2: f006 fd53 bl 8009d7c + 80032d6: 4603 mov r3, r0 + 80032d8: 460c mov r4, r1 + 80032da: 461a mov r2, r3 + 80032dc: 4623 mov r3, r4 + 80032de: 4640 mov r0, r8 + 80032e0: 4649 mov r1, r9 + 80032e2: f7fd fa2b bl 800073c <__aeabi_ddiv> + 80032e6: 4603 mov r3, r0 + 80032e8: 460c mov r4, r1 + 80032ea: 4618 mov r0, r3 + 80032ec: 4621 mov r1, r4 + 80032ee: f006 fdc3 bl 8009e78 + 80032f2: 4603 mov r3, r0 + 80032f4: 460c mov r4, r1 + heading = atan((lon2 - lon1) / + 80032f6: 461a mov r2, r3 + 80032f8: 4623 mov r3, r4 + 80032fa: 4628 mov r0, r5 + 80032fc: 4631 mov r1, r6 + 80032fe: f7fd fa1d bl 800073c <__aeabi_ddiv> + 8003302: 4603 mov r3, r0 + 8003304: 460c mov r4, r1 + 8003306: 4618 mov r0, r3 + 8003308: 4621 mov r1, r4 + 800330a: f006 fb39 bl 8009980 + 800330e: e9c7 0108 strd r0, r1, [r7, #32] + + + if ((lat2 > lat1) && (lon2 > lon1)) + 8003312: e9d7 2306 ldrd r2, r3, [r7, #24] + 8003316: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 + 800331a: f7fd fb75 bl 8000a08 <__aeabi_dcmpgt> + 800331e: 4603 mov r3, r0 + 8003320: 2b00 cmp r3, #0 + 8003322: d016 beq.n 8003352 + 8003324: e9d7 2304 ldrd r2, r3, [r7, #16] + 8003328: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28 + 800332c: f7fd fb6c bl 8000a08 <__aeabi_dcmpgt> + 8003330: 4603 mov r3, r0 + 8003332: 2b00 cmp r3, #0 + 8003334: d00d beq.n 8003352 + { + heading *= rad_to_deg; + 8003336: a422 add r4, pc, #136 ; (adr r4, 80033c0 ) + 8003338: e9d4 3400 ldrd r3, r4, [r4] + 800333c: 461a mov r2, r3 + 800333e: 4623 mov r3, r4 + 8003340: e9d7 0108 ldrd r0, r1, [r7, #32] + 8003344: f7fd f8d0 bl 80004e8 <__aeabi_dmul> + 8003348: 4603 mov r3, r0 + 800334a: 460c mov r4, r1 + 800334c: e9c7 3408 strd r3, r4, [r7, #32] + 8003350: e05d b.n 800340e + } + else if ((lat2 > lat1) && (lon2 < lon1)) + 8003352: e9d7 2306 ldrd r2, r3, [r7, #24] + 8003356: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 + 800335a: f7fd fb55 bl 8000a08 <__aeabi_dcmpgt> + 800335e: 4603 mov r3, r0 + 8003360: 2b00 cmp r3, #0 + 8003362: d037 beq.n 80033d4 + 8003364: e9d7 2304 ldrd r2, r3, [r7, #16] + 8003368: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28 + 800336c: f7fd fb2e bl 80009cc <__aeabi_dcmplt> + 8003370: 4603 mov r3, r0 + 8003372: 2b00 cmp r3, #0 + 8003374: d02e beq.n 80033d4 + { + heading = 360.0 + heading * rad_to_deg; + 8003376: a112 add r1, pc, #72 ; (adr r1, 80033c0 ) + 8003378: e9d1 0100 ldrd r0, r1, [r1] + 800337c: e9d7 2308 ldrd r2, r3, [r7, #32] + 8003380: f7fd f8b2 bl 80004e8 <__aeabi_dmul> + 8003384: 4603 mov r3, r0 + 8003386: 460c mov r4, r1 + 8003388: 4618 mov r0, r3 + 800338a: 4621 mov r1, r4 + 800338c: f04f 0200 mov.w r2, #0 + 8003390: 4b0f ldr r3, [pc, #60] ; (80033d0 ) + 8003392: f7fc fef3 bl 800017c <__adddf3> + 8003396: 4603 mov r3, r0 + 8003398: 460c mov r4, r1 + 800339a: e9c7 3408 strd r3, r4, [r7, #32] + 800339e: e036 b.n 800340e + 80033a0: a2529d3a .word 0xa2529d3a + 80033a4: 3f91df46 .word 0x3f91df46 + 80033a8: e2308c3a .word 0xe2308c3a + 80033ac: 3e45798e .word 0x3e45798e + 80033b0: 00000000 .word 0x00000000 + 80033b4: 41684db0 .word 0x41684db0 + 80033b8: 54442d18 .word 0x54442d18 + 80033bc: 3fe921fb .word 0x3fe921fb + 80033c0: 1a63c1f8 .word 0x1a63c1f8 + 80033c4: 404ca5dc .word 0x404ca5dc + 80033c8: 20000614 .word 0x20000614 + 80033cc: 20000740 .word 0x20000740 + 80033d0: 40768000 .word 0x40768000 + } + else if (lat2 < lat1) + 80033d4: e9d7 2306 ldrd r2, r3, [r7, #24] + 80033d8: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 + 80033dc: f7fd faf6 bl 80009cc <__aeabi_dcmplt> + 80033e0: 4603 mov r3, r0 + 80033e2: 2b00 cmp r3, #0 + 80033e4: d013 beq.n 800340e + { + heading = 180.0 + heading * rad_to_deg; + 80033e6: a12c add r1, pc, #176 ; (adr r1, 8003498 ) + 80033e8: e9d1 0100 ldrd r0, r1, [r1] + 80033ec: e9d7 2308 ldrd r2, r3, [r7, #32] + 80033f0: f7fd f87a bl 80004e8 <__aeabi_dmul> + 80033f4: 4603 mov r3, r0 + 80033f6: 460c mov r4, r1 + 80033f8: 4618 mov r0, r3 + 80033fa: 4621 mov r1, r4 + 80033fc: f04f 0200 mov.w r2, #0 + 8003400: 4b27 ldr r3, [pc, #156] ; (80034a0 ) + 8003402: f7fc febb bl 800017c <__adddf3> + 8003406: 4603 mov r3, r0 + 8003408: 460c mov r4, r1 + 800340a: e9c7 3408 strd r3, r4, [r7, #32] + } + + gps_rel[another_device].distance = (uint32_t)distance; + 800340e: 79fc ldrb r4, [r7, #7] + 8003410: e9d7 0102 ldrd r0, r1, [r7, #8] + 8003414: f7fd fb40 bl 8000a98 <__aeabi_d2uiz> + 8003418: 4602 mov r2, r0 + 800341a: 4b22 ldr r3, [pc, #136] ; (80034a4 ) + 800341c: f843 2034 str.w r2, [r3, r4, lsl #3] + + if (gps_rel[another_device].distance == 0) + 8003420: 79fb ldrb r3, [r7, #7] + 8003422: 4a20 ldr r2, [pc, #128] ; (80034a4 ) + 8003424: f852 3033 ldr.w r3, [r2, r3, lsl #3] + 8003428: 2b00 cmp r3, #0 + 800342a: d106 bne.n 800343a + { + gps_rel[another_device].heading = 0; //if distance is zero then make heading equals zero too + 800342c: 79fb ldrb r3, [r7, #7] + 800342e: 4a1d ldr r2, [pc, #116] ; (80034a4 ) + 8003430: 00db lsls r3, r3, #3 + 8003432: 4413 add r3, r2 + 8003434: 2200 movs r2, #0 + 8003436: 809a strh r2, [r3, #4] + 8003438: e00b b.n 8003452 + } + else + { + gps_rel[another_device].heading = (uint16_t)heading; + 800343a: 79fc ldrb r4, [r7, #7] + 800343c: e9d7 0108 ldrd r0, r1, [r7, #32] + 8003440: f7fd fb2a bl 8000a98 <__aeabi_d2uiz> + 8003444: 4603 mov r3, r0 + 8003446: b299 uxth r1, r3 + 8003448: 4a16 ldr r2, [pc, #88] ; (80034a4 ) + 800344a: 00e3 lsls r3, r4, #3 + 800344c: 4413 add r3, r2 + 800344e: 460a mov r2, r1 + 8003450: 809a strh r2, [r3, #4] + } + + gps_rel[another_device].altitude_diff = gps_air[another_device].altitude.as_integer - (int16_t)p_gps_num->altitude; + 8003452: 79fa ldrb r2, [r7, #7] + 8003454: 4914 ldr r1, [pc, #80] ; (80034a8 ) + 8003456: 4613 mov r3, r2 + 8003458: 009b lsls r3, r3, #2 + 800345a: 4413 add r3, r2 + 800345c: 009b lsls r3, r3, #2 + 800345e: 440b add r3, r1 + 8003460: 330c adds r3, #12 + 8003462: f9b3 3000 ldrsh.w r3, [r3] + 8003466: b29c uxth r4, r3 + 8003468: 4b10 ldr r3, [pc, #64] ; (80034ac ) + 800346a: 681b ldr r3, [r3, #0] + 800346c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800346e: 4618 mov r0, r3 + 8003470: f7fd fe56 bl 8001120 <__aeabi_f2iz> + 8003474: 4603 mov r3, r0 + 8003476: b21b sxth r3, r3 + 8003478: b29b uxth r3, r3 + 800347a: 1ae3 subs r3, r4, r3 + 800347c: b29a uxth r2, r3 + 800347e: 79fb ldrb r3, [r7, #7] + 8003480: b211 sxth r1, r2 + 8003482: 4a08 ldr r2, [pc, #32] ; (80034a4 ) + 8003484: 00db lsls r3, r3, #3 + 8003486: 4413 add r3, r2 + 8003488: 460a mov r2, r1 + 800348a: 80da strh r2, [r3, #6] +} + 800348c: bf00 nop + 800348e: 373c adds r7, #60 ; 0x3c + 8003490: 46bd mov sp, r7 + 8003492: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8003496: bf00 nop + 8003498: 1a63c1f8 .word 0x1a63c1f8 + 800349c: 404ca5dc .word 0x404ca5dc + 80034a0: 40668000 .word 0x40668000 + 80034a4: 20000700 .word 0x20000700 + 80034a8: 20000740 .word 0x20000740 + 80034ac: 20000614 .word 0x20000614 + +080034b0 : + + + +struct gps_air_struct **get_gps_air(void) +{ + 80034b0: b480 push {r7} + 80034b2: b083 sub sp, #12 + 80034b4: af00 add r7, sp, #0 + for (uint8_t i = 0; i <= DEVICES_IN_GROUP; i++) + 80034b6: 2300 movs r3, #0 + 80034b8: 71fb strb r3, [r7, #7] + 80034ba: e00d b.n 80034d8 + { + p_gps_air[i] = &gps_air[i]; + 80034bc: 79fa ldrb r2, [r7, #7] + 80034be: 79f9 ldrb r1, [r7, #7] + 80034c0: 4613 mov r3, r2 + 80034c2: 009b lsls r3, r3, #2 + 80034c4: 4413 add r3, r2 + 80034c6: 009b lsls r3, r3, #2 + 80034c8: 4a08 ldr r2, [pc, #32] ; (80034ec ) + 80034ca: 4413 add r3, r2 + 80034cc: 4a08 ldr r2, [pc, #32] ; (80034f0 ) + 80034ce: f842 3021 str.w r3, [r2, r1, lsl #2] + for (uint8_t i = 0; i <= DEVICES_IN_GROUP; i++) + 80034d2: 79fb ldrb r3, [r7, #7] + 80034d4: 3301 adds r3, #1 + 80034d6: 71fb strb r3, [r7, #7] + 80034d8: 79fb ldrb r3, [r7, #7] + 80034da: 2b06 cmp r3, #6 + 80034dc: d9ee bls.n 80034bc + } + + return &p_gps_air[0]; + 80034de: 4b04 ldr r3, [pc, #16] ; (80034f0 ) +} + 80034e0: 4618 mov r0, r3 + 80034e2: 370c adds r7, #12 + 80034e4: 46bd mov sp, r7 + 80034e6: bc80 pop {r7} + 80034e8: 4770 bx lr + 80034ea: bf00 nop + 80034ec: 20000740 .word 0x20000740 + 80034f0: 200006e4 .word 0x200006e4 + +080034f4 : + + + +struct gps_rel_struct **get_gps_rel(void) +{ + 80034f4: b480 push {r7} + 80034f6: b083 sub sp, #12 + 80034f8: af00 add r7, sp, #0 + for (uint8_t i = 0; i <= DEVICES_IN_GROUP; i++) + 80034fa: 2300 movs r3, #0 + 80034fc: 71fb strb r3, [r7, #7] + 80034fe: e00a b.n 8003516 + { + p_gps_rel[i] = &gps_rel[i]; + 8003500: 79fa ldrb r2, [r7, #7] + 8003502: 79fb ldrb r3, [r7, #7] + 8003504: 00d2 lsls r2, r2, #3 + 8003506: 4908 ldr r1, [pc, #32] ; (8003528 ) + 8003508: 440a add r2, r1 + 800350a: 4908 ldr r1, [pc, #32] ; (800352c ) + 800350c: f841 2023 str.w r2, [r1, r3, lsl #2] + for (uint8_t i = 0; i <= DEVICES_IN_GROUP; i++) + 8003510: 79fb ldrb r3, [r7, #7] + 8003512: 3301 adds r3, #1 + 8003514: 71fb strb r3, [r7, #7] + 8003516: 79fb ldrb r3, [r7, #7] + 8003518: 2b06 cmp r3, #6 + 800351a: d9f1 bls.n 8003500 + } + + return &p_gps_rel[0]; + 800351c: 4b03 ldr r3, [pc, #12] ; (800352c ) +} + 800351e: 4618 mov r0, r3 + 8003520: 370c adds r7, #12 + 8003522: 46bd mov sp, r7 + 8003524: bc80 pop {r7} + 8003526: 4770 bx lr + 8003528: 20000700 .word 0x20000700 + 800352c: 200006c8 .word 0x200006c8 + +08003530 : + + + +struct dev_aux_struct **get_dev_aux(void) +{ + 8003530: b480 push {r7} + 8003532: b083 sub sp, #12 + 8003534: af00 add r7, sp, #0 + for (uint8_t i = 0; i <= DEVICES_IN_GROUP; i++) + 8003536: 2300 movs r3, #0 + 8003538: 71fb strb r3, [r7, #7] + 800353a: e00d b.n 8003558 + { + p_dev_aux[i] = &dev_aux[i]; + 800353c: 79fa ldrb r2, [r7, #7] + 800353e: 79f9 ldrb r1, [r7, #7] + 8003540: 4613 mov r3, r2 + 8003542: 005b lsls r3, r3, #1 + 8003544: 4413 add r3, r2 + 8003546: 00db lsls r3, r3, #3 + 8003548: 4a08 ldr r2, [pc, #32] ; (800356c ) + 800354a: 4413 add r3, r2 + 800354c: 4a08 ldr r2, [pc, #32] ; (8003570 ) + 800354e: f842 3021 str.w r3, [r2, r1, lsl #2] + for (uint8_t i = 0; i <= DEVICES_IN_GROUP; i++) + 8003552: 79fb ldrb r3, [r7, #7] + 8003554: 3301 adds r3, #1 + 8003556: 71fb strb r3, [r7, #7] + 8003558: 79fb ldrb r3, [r7, #7] + 800355a: 2b06 cmp r3, #6 + 800355c: d9ee bls.n 800353c + } + + return &p_dev_aux[0]; + 800355e: 4b04 ldr r3, [pc, #16] ; (8003570 ) +} + 8003560: 4618 mov r0, r3 + 8003562: 370c adds r7, #12 + 8003564: 46bd mov sp, r7 + 8003566: bc80 pop {r7} + 8003568: 4770 bx lr + 800356a: bf00 nop + 800356c: 20000620 .word 0x20000620 + 8003570: 200005f8 .word 0x200005f8 + +08003574 : +#define M24C64_PAGES_TOTAL (256) + + + +uint8_t m24c64_poll(void) +{ + 8003574: b480 push {r7} + 8003576: b083 sub sp, #12 + 8003578: af00 add r7, sp, #0 + uint16_t SR1_tmp; + uint16_t SR2_tmp; + uint8_t attempts = M24C64_POLL_ATTEMPTS; + 800357a: 2364 movs r3, #100 ; 0x64 + 800357c: 717b strb r3, [r7, #5] + + while (attempts) + 800357e: e047 b.n 8003610 + { + //Start + I2C2->CR1 |= I2C_CR1_START; + 8003580: 4b2d ldr r3, [pc, #180] ; (8003638 ) + 8003582: 881b ldrh r3, [r3, #0] + 8003584: b29b uxth r3, r3 + 8003586: 4a2c ldr r2, [pc, #176] ; (8003638 ) + 8003588: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800358c: b29b uxth r3, r3 + 800358e: 8013 strh r3, [r2, #0] + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + 8003590: bf00 nop + 8003592: 4b29 ldr r3, [pc, #164] ; (8003638 ) + 8003594: 8a9b ldrh r3, [r3, #20] + 8003596: b29b uxth r3, r3 + 8003598: f003 0301 and.w r3, r3, #1 + 800359c: 2b00 cmp r3, #0 + 800359e: d0f8 beq.n 8003592 + { + } + //Clear + SR1_tmp = I2C2->SR1; + 80035a0: 4b25 ldr r3, [pc, #148] ; (8003638 ) + 80035a2: 8a9b ldrh r3, [r3, #20] + 80035a4: 807b strh r3, [r7, #2] + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_WRITE_MODE; + 80035a6: 4b24 ldr r3, [pc, #144] ; (8003638 ) + 80035a8: 22a0 movs r2, #160 ; 0xa0 + 80035aa: 821a strh r2, [r3, #16] + //Wait for address end of transmission or NAK reception + do + { + SR1_tmp = I2C2->SR1; + 80035ac: 4b22 ldr r3, [pc, #136] ; (8003638 ) + 80035ae: 8a9b ldrh r3, [r3, #20] + 80035b0: 807b strh r3, [r7, #2] + } + while (!(SR1_tmp & I2C_SR1_ADDR) && !(SR1_tmp & I2C_SR1_AF)); //"ADDR is not set after a NACK reception" + 80035b2: 887b ldrh r3, [r7, #2] + 80035b4: f003 0302 and.w r3, r3, #2 + 80035b8: 2b00 cmp r3, #0 + 80035ba: d104 bne.n 80035c6 + 80035bc: 887b ldrh r3, [r7, #2] + 80035be: f403 6380 and.w r3, r3, #1024 ; 0x400 + 80035c2: 2b00 cmp r3, #0 + 80035c4: d0f2 beq.n 80035ac + //Clear + SR1_tmp = I2C2->SR1; + 80035c6: 4b1c ldr r3, [pc, #112] ; (8003638 ) + 80035c8: 8a9b ldrh r3, [r3, #20] + 80035ca: 807b strh r3, [r7, #2] + SR2_tmp = I2C2->SR2; + 80035cc: 4b1a ldr r3, [pc, #104] ; (8003638 ) + 80035ce: 8b1b ldrh r3, [r3, #24] + 80035d0: 80fb strh r3, [r7, #6] + + //Check acknowledge failure + if (SR1_tmp & I2C_SR1_AF) + 80035d2: 887b ldrh r3, [r7, #2] + 80035d4: f403 6380 and.w r3, r3, #1024 ; 0x400 + 80035d8: 2b00 cmp r3, #0 + 80035da: d007 beq.n 80035ec + { + //no acknowledge is returned, slave is busy + I2C2->SR1 = ~(I2C_SR1_AF); //write 0 to clear AF bit + 80035dc: 4b16 ldr r3, [pc, #88] ; (8003638 ) + 80035de: f64f 32ff movw r2, #64511 ; 0xfbff + 80035e2: 829a strh r2, [r3, #20] + + attempts--; //slave is not ready, decrement attmepts counter + 80035e4: 797b ldrb r3, [r7, #5] + 80035e6: 3b01 subs r3, #1 + 80035e8: 717b strb r3, [r7, #5] + 80035ea: e011 b.n 8003610 + } + else if (SR1_tmp & I2C_SR1_ADDR) + 80035ec: 887b ldrh r3, [r7, #2] + 80035ee: f003 0302 and.w r3, r3, #2 + 80035f2: 2b00 cmp r3, #0 + 80035f4: d009 beq.n 800360a + { + //Stop + I2C2->CR1 |= I2C_CR1_STOP; + 80035f6: 4b10 ldr r3, [pc, #64] ; (8003638 ) + 80035f8: 881b ldrh r3, [r3, #0] + 80035fa: b29b uxth r3, r3 + 80035fc: 4a0e ldr r2, [pc, #56] ; (8003638 ) + 80035fe: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8003602: b29b uxth r3, r3 + 8003604: 8013 strh r3, [r2, #0] + + return 1; //slave is ready + 8003606: 2301 movs r3, #1 + 8003608: e011 b.n 800362e + } + else + { + attempts--; //??? + 800360a: 797b ldrb r3, [r7, #5] + 800360c: 3b01 subs r3, #1 + 800360e: 717b strb r3, [r7, #5] + while (attempts) + 8003610: 797b ldrb r3, [r7, #5] + 8003612: 2b00 cmp r3, #0 + 8003614: d1b4 bne.n 8003580 + } + } + + SR2_tmp = SR2_tmp + 1; + 8003616: 88fb ldrh r3, [r7, #6] + 8003618: 3301 adds r3, #1 + 800361a: 80fb strh r3, [r7, #6] + + //Stop before end + I2C2->CR1 |= I2C_CR1_STOP; + 800361c: 4b06 ldr r3, [pc, #24] ; (8003638 ) + 800361e: 881b ldrh r3, [r3, #0] + 8003620: b29b uxth r3, r3 + 8003622: 4a05 ldr r2, [pc, #20] ; (8003638 ) + 8003624: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8003628: b29b uxth r3, r3 + 800362a: 8013 strh r3, [r2, #0] + + return 0; //end of attmepts, slave is busy or absent + 800362c: 2300 movs r3, #0 +} + 800362e: 4618 mov r0, r3 + 8003630: 370c adds r7, #12 + 8003632: 46bd mov sp, r7 + 8003634: bc80 pop {r7} + 8003636: 4770 bx lr + 8003638: 40005800 .word 0x40005800 + +0800363c : + + + +uint8_t m24c64_read_byte(uint16_t memory_address) +{ + 800363c: b580 push {r7, lr} + 800363e: b084 sub sp, #16 + 8003640: af00 add r7, sp, #0 + 8003642: 4603 mov r3, r0 + 8003644: 80fb strh r3, [r7, #6] + uint8_t result = 0; + 8003646: 2300 movs r3, #0 + 8003648: 73fb strb r3, [r7, #15] + + if (m24c64_poll()) + 800364a: f7ff ff93 bl 8003574 + 800364e: 4603 mov r3, r0 + 8003650: 2b00 cmp r3, #0 + 8003652: f000 8084 beq.w 800375e + { + uint16_t SR_tmp; + + //Start + I2C2->CR1 |= I2C_CR1_START; + 8003656: 4b45 ldr r3, [pc, #276] ; (800376c ) + 8003658: 881b ldrh r3, [r3, #0] + 800365a: b29b uxth r3, r3 + 800365c: 4a43 ldr r2, [pc, #268] ; (800376c ) + 800365e: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003662: b29b uxth r3, r3 + 8003664: 8013 strh r3, [r2, #0] + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + 8003666: bf00 nop + 8003668: 4b40 ldr r3, [pc, #256] ; (800376c ) + 800366a: 8a9b ldrh r3, [r3, #20] + 800366c: b29b uxth r3, r3 + 800366e: f003 0301 and.w r3, r3, #1 + 8003672: 2b00 cmp r3, #0 + 8003674: d0f8 beq.n 8003668 + { + } + //Clear + SR_tmp = I2C2->SR1; + 8003676: 4b3d ldr r3, [pc, #244] ; (800376c ) + 8003678: 8a9b ldrh r3, [r3, #20] + 800367a: 81bb strh r3, [r7, #12] + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_WRITE_MODE; + 800367c: 4b3b ldr r3, [pc, #236] ; (800376c ) + 800367e: 22a0 movs r2, #160 ; 0xa0 + 8003680: 821a strh r2, [r3, #16] + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + 8003682: bf00 nop + 8003684: 4b39 ldr r3, [pc, #228] ; (800376c ) + 8003686: 8a9b ldrh r3, [r3, #20] + 8003688: b29b uxth r3, r3 + 800368a: f003 0302 and.w r3, r3, #2 + 800368e: 2b00 cmp r3, #0 + 8003690: d0f8 beq.n 8003684 + { + } + //Clear + SR_tmp = I2C2->SR1; + 8003692: 4b36 ldr r3, [pc, #216] ; (800376c ) + 8003694: 8a9b ldrh r3, [r3, #20] + 8003696: 81bb strh r3, [r7, #12] + SR_tmp = I2C2->SR2; + 8003698: 4b34 ldr r3, [pc, #208] ; (800376c ) + 800369a: 8b1b ldrh r3, [r3, #24] + 800369c: 81bb strh r3, [r7, #12] + + //Memory address high byte + I2C2->DR = (uint8_t)(memory_address >> 8); + 800369e: 88fb ldrh r3, [r7, #6] + 80036a0: 0a1b lsrs r3, r3, #8 + 80036a2: b29b uxth r3, r3 + 80036a4: b2da uxtb r2, r3 + 80036a6: 4b31 ldr r3, [pc, #196] ; (800376c ) + 80036a8: b292 uxth r2, r2 + 80036aa: 821a strh r2, [r3, #16] + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + 80036ac: bf00 nop + 80036ae: 4b2f ldr r3, [pc, #188] ; (800376c ) + 80036b0: 8a9b ldrh r3, [r3, #20] + 80036b2: b29b uxth r3, r3 + 80036b4: f003 0380 and.w r3, r3, #128 ; 0x80 + 80036b8: 2b00 cmp r3, #0 + 80036ba: d0f8 beq.n 80036ae + { + } + + //Memory address low byte + I2C2->DR = (uint8_t)memory_address; + 80036bc: 88fb ldrh r3, [r7, #6] + 80036be: b2da uxtb r2, r3 + 80036c0: 4b2a ldr r3, [pc, #168] ; (800376c ) + 80036c2: b292 uxth r2, r2 + 80036c4: 821a strh r2, [r3, #16] + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + 80036c6: bf00 nop + 80036c8: 4b28 ldr r3, [pc, #160] ; (800376c ) + 80036ca: 8a9b ldrh r3, [r3, #20] + 80036cc: b29b uxth r3, r3 + 80036ce: f003 0380 and.w r3, r3, #128 ; 0x80 + 80036d2: 2b00 cmp r3, #0 + 80036d4: d0f8 beq.n 80036c8 + { + } + + + //Start (restart actually) + I2C2->CR1 |= I2C_CR1_START; + 80036d6: 4b25 ldr r3, [pc, #148] ; (800376c ) + 80036d8: 881b ldrh r3, [r3, #0] + 80036da: b29b uxth r3, r3 + 80036dc: 4a23 ldr r2, [pc, #140] ; (800376c ) + 80036de: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80036e2: b29b uxth r3, r3 + 80036e4: 8013 strh r3, [r2, #0] + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + 80036e6: bf00 nop + 80036e8: 4b20 ldr r3, [pc, #128] ; (800376c ) + 80036ea: 8a9b ldrh r3, [r3, #20] + 80036ec: b29b uxth r3, r3 + 80036ee: f003 0301 and.w r3, r3, #1 + 80036f2: 2b00 cmp r3, #0 + 80036f4: d0f8 beq.n 80036e8 + { + } + //Clear + SR_tmp = I2C2->SR1; + 80036f6: 4b1d ldr r3, [pc, #116] ; (800376c ) + 80036f8: 8a9b ldrh r3, [r3, #20] + 80036fa: 81bb strh r3, [r7, #12] + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_READ_MODE; + 80036fc: 4b1b ldr r3, [pc, #108] ; (800376c ) + 80036fe: 22a1 movs r2, #161 ; 0xa1 + 8003700: 821a strh r2, [r3, #16] + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + 8003702: bf00 nop + 8003704: 4b19 ldr r3, [pc, #100] ; (800376c ) + 8003706: 8a9b ldrh r3, [r3, #20] + 8003708: b29b uxth r3, r3 + 800370a: f003 0302 and.w r3, r3, #2 + 800370e: 2b00 cmp r3, #0 + 8003710: d0f8 beq.n 8003704 + { + } + //Clear + SR_tmp = I2C2->SR1; + 8003712: 4b16 ldr r3, [pc, #88] ; (800376c ) + 8003714: 8a9b ldrh r3, [r3, #20] + 8003716: 81bb strh r3, [r7, #12] + SR_tmp = I2C2->SR2; + 8003718: 4b14 ldr r3, [pc, #80] ; (800376c ) + 800371a: 8b1b ldrh r3, [r3, #24] + 800371c: 81bb strh r3, [r7, #12] + + //NACK next byte + I2C2->CR1 &= ~I2C_CR1_ACK; + 800371e: 4b13 ldr r3, [pc, #76] ; (800376c ) + 8003720: 881b ldrh r3, [r3, #0] + 8003722: b29b uxth r3, r3 + 8003724: 4a11 ldr r2, [pc, #68] ; (800376c ) + 8003726: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 800372a: b29b uxth r3, r3 + 800372c: 8013 strh r3, [r2, #0] + //Stop + I2C2->CR1 |= I2C_CR1_STOP; + 800372e: 4b0f ldr r3, [pc, #60] ; (800376c ) + 8003730: 881b ldrh r3, [r3, #0] + 8003732: b29b uxth r3, r3 + 8003734: 4a0d ldr r2, [pc, #52] ; (800376c ) + 8003736: f443 7300 orr.w r3, r3, #512 ; 0x200 + 800373a: b29b uxth r3, r3 + 800373c: 8013 strh r3, [r2, #0] + //Wait for data register not empty + while (!(I2C2->SR1 & I2C_SR1_RXNE)) + 800373e: bf00 nop + 8003740: 4b0a ldr r3, [pc, #40] ; (800376c ) + 8003742: 8a9b ldrh r3, [r3, #20] + 8003744: b29b uxth r3, r3 + 8003746: f003 0340 and.w r3, r3, #64 ; 0x40 + 800374a: 2b00 cmp r3, #0 + 800374c: d0f8 beq.n 8003740 + { + } + + SR_tmp = SR_tmp + 1; + 800374e: 89bb ldrh r3, [r7, #12] + 8003750: 3301 adds r3, #1 + 8003752: 81bb strh r3, [r7, #12] + + //Read requested byte + result = I2C2->DR; + 8003754: 4b05 ldr r3, [pc, #20] ; (800376c ) + 8003756: 8a1b ldrh r3, [r3, #16] + 8003758: b29b uxth r3, r3 + 800375a: 73fb strb r3, [r7, #15] + 800375c: e001 b.n 8003762 + } + else + { + result = 0; + 800375e: 2300 movs r3, #0 + 8003760: 73fb strb r3, [r7, #15] + } + + return result; + 8003762: 7bfb ldrb r3, [r7, #15] +} + 8003764: 4618 mov r0, r3 + 8003766: 3710 adds r7, #16 + 8003768: 46bd mov sp, r7 + 800376a: bd80 pop {r7, pc} + 800376c: 40005800 .word 0x40005800 + +08003770 : +} + + + +void m24c64_read_page(uint8_t data_array[], uint8_t page_address) +{ + 8003770: b580 push {r7, lr} + 8003772: b084 sub sp, #16 + 8003774: af00 add r7, sp, #0 + 8003776: 6078 str r0, [r7, #4] + 8003778: 460b mov r3, r1 + 800377a: 70fb strb r3, [r7, #3] + if (m24c64_poll()) + 800377c: f7ff fefa bl 8003574 + 8003780: 4603 mov r3, r0 + 8003782: 2b00 cmp r3, #0 + 8003784: f000 80b1 beq.w 80038ea + { + uint8_t SR_tmp; + uint16_t memory_address = page_address * M24C64_PAGE_SIZE; + 8003788: 78fb ldrb r3, [r7, #3] + 800378a: b29b uxth r3, r3 + 800378c: 015b lsls r3, r3, #5 + 800378e: 81bb strh r3, [r7, #12] + + //Start + I2C2->CR1 |= I2C_CR1_START; + 8003790: 4b58 ldr r3, [pc, #352] ; (80038f4 ) + 8003792: 881b ldrh r3, [r3, #0] + 8003794: b29b uxth r3, r3 + 8003796: 4a57 ldr r2, [pc, #348] ; (80038f4 ) + 8003798: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800379c: b29b uxth r3, r3 + 800379e: 8013 strh r3, [r2, #0] + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + 80037a0: bf00 nop + 80037a2: 4b54 ldr r3, [pc, #336] ; (80038f4 ) + 80037a4: 8a9b ldrh r3, [r3, #20] + 80037a6: b29b uxth r3, r3 + 80037a8: f003 0301 and.w r3, r3, #1 + 80037ac: 2b00 cmp r3, #0 + 80037ae: d0f8 beq.n 80037a2 + { + } + //Clear + SR_tmp = I2C2->SR1; + 80037b0: 4b50 ldr r3, [pc, #320] ; (80038f4 ) + 80037b2: 8a9b ldrh r3, [r3, #20] + 80037b4: b29b uxth r3, r3 + 80037b6: 72fb strb r3, [r7, #11] + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_WRITE_MODE; + 80037b8: 4b4e ldr r3, [pc, #312] ; (80038f4 ) + 80037ba: 22a0 movs r2, #160 ; 0xa0 + 80037bc: 821a strh r2, [r3, #16] + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + 80037be: bf00 nop + 80037c0: 4b4c ldr r3, [pc, #304] ; (80038f4 ) + 80037c2: 8a9b ldrh r3, [r3, #20] + 80037c4: b29b uxth r3, r3 + 80037c6: f003 0302 and.w r3, r3, #2 + 80037ca: 2b00 cmp r3, #0 + 80037cc: d0f8 beq.n 80037c0 + { + } + //Clear + SR_tmp = I2C2->SR1; + 80037ce: 4b49 ldr r3, [pc, #292] ; (80038f4 ) + 80037d0: 8a9b ldrh r3, [r3, #20] + 80037d2: b29b uxth r3, r3 + 80037d4: 72fb strb r3, [r7, #11] + SR_tmp = I2C2->SR2; + 80037d6: 4b47 ldr r3, [pc, #284] ; (80038f4 ) + 80037d8: 8b1b ldrh r3, [r3, #24] + 80037da: b29b uxth r3, r3 + 80037dc: 72fb strb r3, [r7, #11] + + //Memory address high byte + I2C2->DR = (uint8_t)(memory_address >> 8); + 80037de: 89bb ldrh r3, [r7, #12] + 80037e0: 0a1b lsrs r3, r3, #8 + 80037e2: b29b uxth r3, r3 + 80037e4: b2da uxtb r2, r3 + 80037e6: 4b43 ldr r3, [pc, #268] ; (80038f4 ) + 80037e8: b292 uxth r2, r2 + 80037ea: 821a strh r2, [r3, #16] + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + 80037ec: bf00 nop + 80037ee: 4b41 ldr r3, [pc, #260] ; (80038f4 ) + 80037f0: 8a9b ldrh r3, [r3, #20] + 80037f2: b29b uxth r3, r3 + 80037f4: f003 0380 and.w r3, r3, #128 ; 0x80 + 80037f8: 2b00 cmp r3, #0 + 80037fa: d0f8 beq.n 80037ee + { + } + + //Memory address low byte + I2C2->DR = (uint8_t)memory_address; + 80037fc: 89bb ldrh r3, [r7, #12] + 80037fe: b2da uxtb r2, r3 + 8003800: 4b3c ldr r3, [pc, #240] ; (80038f4 ) + 8003802: b292 uxth r2, r2 + 8003804: 821a strh r2, [r3, #16] + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + 8003806: bf00 nop + 8003808: 4b3a ldr r3, [pc, #232] ; (80038f4 ) + 800380a: 8a9b ldrh r3, [r3, #20] + 800380c: b29b uxth r3, r3 + 800380e: f003 0380 and.w r3, r3, #128 ; 0x80 + 8003812: 2b00 cmp r3, #0 + 8003814: d0f8 beq.n 8003808 + { + } + + + //Start (restart actually) + I2C2->CR1 |= I2C_CR1_START; + 8003816: 4b37 ldr r3, [pc, #220] ; (80038f4 ) + 8003818: 881b ldrh r3, [r3, #0] + 800381a: b29b uxth r3, r3 + 800381c: 4a35 ldr r2, [pc, #212] ; (80038f4 ) + 800381e: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003822: b29b uxth r3, r3 + 8003824: 8013 strh r3, [r2, #0] + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + 8003826: bf00 nop + 8003828: 4b32 ldr r3, [pc, #200] ; (80038f4 ) + 800382a: 8a9b ldrh r3, [r3, #20] + 800382c: b29b uxth r3, r3 + 800382e: f003 0301 and.w r3, r3, #1 + 8003832: 2b00 cmp r3, #0 + 8003834: d0f8 beq.n 8003828 + { + } + //Clear + SR_tmp = I2C2->SR1; + 8003836: 4b2f ldr r3, [pc, #188] ; (80038f4 ) + 8003838: 8a9b ldrh r3, [r3, #20] + 800383a: b29b uxth r3, r3 + 800383c: 72fb strb r3, [r7, #11] + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_READ_MODE; + 800383e: 4b2d ldr r3, [pc, #180] ; (80038f4 ) + 8003840: 22a1 movs r2, #161 ; 0xa1 + 8003842: 821a strh r2, [r3, #16] + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + 8003844: bf00 nop + 8003846: 4b2b ldr r3, [pc, #172] ; (80038f4 ) + 8003848: 8a9b ldrh r3, [r3, #20] + 800384a: b29b uxth r3, r3 + 800384c: f003 0302 and.w r3, r3, #2 + 8003850: 2b00 cmp r3, #0 + 8003852: d0f8 beq.n 8003846 + { + } + //Clear + SR_tmp = I2C2->SR1; + 8003854: 4b27 ldr r3, [pc, #156] ; (80038f4 ) + 8003856: 8a9b ldrh r3, [r3, #20] + 8003858: b29b uxth r3, r3 + 800385a: 72fb strb r3, [r7, #11] + SR_tmp = I2C2->SR2; + 800385c: 4b25 ldr r3, [pc, #148] ; (80038f4 ) + 800385e: 8b1b ldrh r3, [r3, #24] + 8003860: b29b uxth r3, r3 + 8003862: 72fb strb r3, [r7, #11] + + for (uint8_t i = 0; i < M24C64_PAGE_SIZE - 1; i++) + 8003864: 2300 movs r3, #0 + 8003866: 73fb strb r3, [r7, #15] + 8003868: e01a b.n 80038a0 + { + //ACK next byte + I2C2->CR1 |= I2C_CR1_ACK; + 800386a: 4b22 ldr r3, [pc, #136] ; (80038f4 ) + 800386c: 881b ldrh r3, [r3, #0] + 800386e: b29b uxth r3, r3 + 8003870: 4a20 ldr r2, [pc, #128] ; (80038f4 ) + 8003872: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8003876: b29b uxth r3, r3 + 8003878: 8013 strh r3, [r2, #0] + //Wait for data register not empty + while (!(I2C2->SR1 & I2C_SR1_RXNE)) + 800387a: bf00 nop + 800387c: 4b1d ldr r3, [pc, #116] ; (80038f4 ) + 800387e: 8a9b ldrh r3, [r3, #20] + 8003880: b29b uxth r3, r3 + 8003882: f003 0340 and.w r3, r3, #64 ; 0x40 + 8003886: 2b00 cmp r3, #0 + 8003888: d0f8 beq.n 800387c + { + } + + //Read byte + data_array[i] = I2C2->DR; + 800388a: 4b1a ldr r3, [pc, #104] ; (80038f4 ) + 800388c: 8a1b ldrh r3, [r3, #16] + 800388e: b299 uxth r1, r3 + 8003890: 7bfb ldrb r3, [r7, #15] + 8003892: 687a ldr r2, [r7, #4] + 8003894: 4413 add r3, r2 + 8003896: b2ca uxtb r2, r1 + 8003898: 701a strb r2, [r3, #0] + for (uint8_t i = 0; i < M24C64_PAGE_SIZE - 1; i++) + 800389a: 7bfb ldrb r3, [r7, #15] + 800389c: 3301 adds r3, #1 + 800389e: 73fb strb r3, [r7, #15] + 80038a0: 7bfb ldrb r3, [r7, #15] + 80038a2: 2b1e cmp r3, #30 + 80038a4: d9e1 bls.n 800386a + } + + //NACK last byte + I2C2->CR1 &= ~I2C_CR1_ACK; + 80038a6: 4b13 ldr r3, [pc, #76] ; (80038f4 ) + 80038a8: 881b ldrh r3, [r3, #0] + 80038aa: b29b uxth r3, r3 + 80038ac: 4a11 ldr r2, [pc, #68] ; (80038f4 ) + 80038ae: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 80038b2: b29b uxth r3, r3 + 80038b4: 8013 strh r3, [r2, #0] + //Stop + I2C2->CR1 |= I2C_CR1_STOP; + 80038b6: 4b0f ldr r3, [pc, #60] ; (80038f4 ) + 80038b8: 881b ldrh r3, [r3, #0] + 80038ba: b29b uxth r3, r3 + 80038bc: 4a0d ldr r2, [pc, #52] ; (80038f4 ) + 80038be: f443 7300 orr.w r3, r3, #512 ; 0x200 + 80038c2: b29b uxth r3, r3 + 80038c4: 8013 strh r3, [r2, #0] + //Wait for data register not empty + while (!(I2C2->SR1 & I2C_SR1_RXNE)) + 80038c6: bf00 nop + 80038c8: 4b0a ldr r3, [pc, #40] ; (80038f4 ) + 80038ca: 8a9b ldrh r3, [r3, #20] + 80038cc: b29b uxth r3, r3 + 80038ce: f003 0340 and.w r3, r3, #64 ; 0x40 + 80038d2: 2b00 cmp r3, #0 + 80038d4: d0f8 beq.n 80038c8 + { + } + + //Read last byte + data_array[M24C64_PAGE_SIZE - 1] = I2C2->DR; + 80038d6: 4b07 ldr r3, [pc, #28] ; (80038f4 ) + 80038d8: 8a1b ldrh r3, [r3, #16] + 80038da: b29a uxth r2, r3 + 80038dc: 687b ldr r3, [r7, #4] + 80038de: 331f adds r3, #31 + 80038e0: b2d2 uxtb r2, r2 + 80038e2: 701a strb r2, [r3, #0] + + SR_tmp = SR_tmp + 1; + 80038e4: 7afb ldrb r3, [r7, #11] + 80038e6: 3301 adds r3, #1 + 80038e8: 72fb strb r3, [r7, #11] + } +} + 80038ea: bf00 nop + 80038ec: 3710 adds r7, #16 + 80038ee: 46bd mov sp, r7 + 80038f0: bd80 pop {r7, pc} + 80038f2: bf00 nop + 80038f4: 40005800 .word 0x40005800 + +080038f8 : + + + +void m24c64_write_page(uint8_t data_array[], uint8_t page_address) +{ + 80038f8: b580 push {r7, lr} + 80038fa: b084 sub sp, #16 + 80038fc: af00 add r7, sp, #0 + 80038fe: 6078 str r0, [r7, #4] + 8003900: 460b mov r3, r1 + 8003902: 70fb strb r3, [r7, #3] + if (m24c64_poll()) + 8003904: f7ff fe36 bl 8003574 + 8003908: 4603 mov r3, r0 + 800390a: 2b00 cmp r3, #0 + 800390c: d06b beq.n 80039e6 + { + uint8_t SR_tmp = 0; + 800390e: 2300 movs r3, #0 + 8003910: 73bb strb r3, [r7, #14] + uint16_t memory_address = page_address * M24C64_PAGE_SIZE; + 8003912: 78fb ldrb r3, [r7, #3] + 8003914: b29b uxth r3, r3 + 8003916: 015b lsls r3, r3, #5 + 8003918: 81bb strh r3, [r7, #12] + + //Start + I2C2->CR1 |= I2C_CR1_START; + 800391a: 4b35 ldr r3, [pc, #212] ; (80039f0 ) + 800391c: 881b ldrh r3, [r3, #0] + 800391e: b29b uxth r3, r3 + 8003920: 4a33 ldr r2, [pc, #204] ; (80039f0 ) + 8003922: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003926: b29b uxth r3, r3 + 8003928: 8013 strh r3, [r2, #0] + //Wait for start generated + while (!(I2C2->SR1 & I2C_SR1_SB)) + 800392a: bf00 nop + 800392c: 4b30 ldr r3, [pc, #192] ; (80039f0 ) + 800392e: 8a9b ldrh r3, [r3, #20] + 8003930: b29b uxth r3, r3 + 8003932: f003 0301 and.w r3, r3, #1 + 8003936: 2b00 cmp r3, #0 + 8003938: d0f8 beq.n 800392c + { + } + //Clear + SR_tmp = I2C2->SR1; + 800393a: 4b2d ldr r3, [pc, #180] ; (80039f0 ) + 800393c: 8a9b ldrh r3, [r3, #20] + 800393e: b29b uxth r3, r3 + 8003940: 73bb strb r3, [r7, #14] + + //Device address + I2C2->DR = (uint8_t)M24C64_ADDRESS_WRITE_MODE; + 8003942: 4b2b ldr r3, [pc, #172] ; (80039f0 ) + 8003944: 22a0 movs r2, #160 ; 0xa0 + 8003946: 821a strh r2, [r3, #16] + //Wait for address end of transmission + while (!(I2C2->SR1 & I2C_SR1_ADDR)) + 8003948: bf00 nop + 800394a: 4b29 ldr r3, [pc, #164] ; (80039f0 ) + 800394c: 8a9b ldrh r3, [r3, #20] + 800394e: b29b uxth r3, r3 + 8003950: f003 0302 and.w r3, r3, #2 + 8003954: 2b00 cmp r3, #0 + 8003956: d0f8 beq.n 800394a + { + } + //Clear + SR_tmp = I2C2->SR1; + 8003958: 4b25 ldr r3, [pc, #148] ; (80039f0 ) + 800395a: 8a9b ldrh r3, [r3, #20] + 800395c: b29b uxth r3, r3 + 800395e: 73bb strb r3, [r7, #14] + SR_tmp = I2C2->SR2; + 8003960: 4b23 ldr r3, [pc, #140] ; (80039f0 ) + 8003962: 8b1b ldrh r3, [r3, #24] + 8003964: b29b uxth r3, r3 + 8003966: 73bb strb r3, [r7, #14] + + //Memory address high byte + I2C2->DR = (uint8_t)(memory_address >> 8); + 8003968: 89bb ldrh r3, [r7, #12] + 800396a: 0a1b lsrs r3, r3, #8 + 800396c: b29b uxth r3, r3 + 800396e: b2da uxtb r2, r3 + 8003970: 4b1f ldr r3, [pc, #124] ; (80039f0 ) + 8003972: b292 uxth r2, r2 + 8003974: 821a strh r2, [r3, #16] + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + 8003976: bf00 nop + 8003978: 4b1d ldr r3, [pc, #116] ; (80039f0 ) + 800397a: 8a9b ldrh r3, [r3, #20] + 800397c: b29b uxth r3, r3 + 800397e: f003 0380 and.w r3, r3, #128 ; 0x80 + 8003982: 2b00 cmp r3, #0 + 8003984: d0f8 beq.n 8003978 + { + } + + //Memory address low byte + I2C2->DR = (uint8_t)memory_address; + 8003986: 89bb ldrh r3, [r7, #12] + 8003988: b2da uxtb r2, r3 + 800398a: 4b19 ldr r3, [pc, #100] ; (80039f0 ) + 800398c: b292 uxth r2, r2 + 800398e: 821a strh r2, [r3, #16] + //Wait for data register empty + while (!(I2C2->SR1 & I2C_SR1_TXE)) + 8003990: bf00 nop + 8003992: 4b17 ldr r3, [pc, #92] ; (80039f0 ) + 8003994: 8a9b ldrh r3, [r3, #20] + 8003996: b29b uxth r3, r3 + 8003998: f003 0380 and.w r3, r3, #128 ; 0x80 + 800399c: 2b00 cmp r3, #0 + 800399e: d0f8 beq.n 8003992 + { + } + + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 80039a0: 2300 movs r3, #0 + 80039a2: 73fb strb r3, [r7, #15] + 80039a4: e011 b.n 80039ca + { + //Write byte + I2C2->DR = data_array[i]; + 80039a6: 7bfb ldrb r3, [r7, #15] + 80039a8: 687a ldr r2, [r7, #4] + 80039aa: 4413 add r3, r2 + 80039ac: 781a ldrb r2, [r3, #0] + 80039ae: 4b10 ldr r3, [pc, #64] ; (80039f0 ) + 80039b0: b292 uxth r2, r2 + 80039b2: 821a strh r2, [r3, #16] + //Wait byte transfer finish + while (!(I2C2->SR1 & I2C_SR1_BTF)) + 80039b4: bf00 nop + 80039b6: 4b0e ldr r3, [pc, #56] ; (80039f0 ) + 80039b8: 8a9b ldrh r3, [r3, #20] + 80039ba: b29b uxth r3, r3 + 80039bc: f003 0304 and.w r3, r3, #4 + 80039c0: 2b00 cmp r3, #0 + 80039c2: d0f8 beq.n 80039b6 + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 80039c4: 7bfb ldrb r3, [r7, #15] + 80039c6: 3301 adds r3, #1 + 80039c8: 73fb strb r3, [r7, #15] + 80039ca: 7bfb ldrb r3, [r7, #15] + 80039cc: 2b1f cmp r3, #31 + 80039ce: d9ea bls.n 80039a6 + { + } + } + + SR_tmp = SR_tmp + 1; + 80039d0: 7bbb ldrb r3, [r7, #14] + 80039d2: 3301 adds r3, #1 + 80039d4: 73bb strb r3, [r7, #14] + + //Stop + I2C2->CR1 |= I2C_CR1_STOP; + 80039d6: 4b06 ldr r3, [pc, #24] ; (80039f0 ) + 80039d8: 881b ldrh r3, [r3, #0] + 80039da: b29b uxth r3, r3 + 80039dc: 4a04 ldr r2, [pc, #16] ; (80039f0 ) + 80039de: f443 7300 orr.w r3, r3, #512 ; 0x200 + 80039e2: b29b uxth r3, r3 + 80039e4: 8013 strh r3, [r2, #0] + } +} + 80039e6: bf00 nop + 80039e8: 3710 adds r7, #16 + 80039ea: 46bd mov sp, r7 + 80039ec: bd80 pop {r7, pc} + 80039ee: bf00 nop + 80039f0: 40005800 .word 0x40005800 + +080039f4 : + + + +void m24c64_erase_page(uint8_t page_address) +{ + 80039f4: b580 push {r7, lr} + 80039f6: b08c sub sp, #48 ; 0x30 + 80039f8: af00 add r7, sp, #0 + 80039fa: 4603 mov r3, r0 + 80039fc: 71fb strb r3, [r7, #7] + uint8_t empty_page[M24C64_PAGE_SIZE]; + + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 80039fe: 2300 movs r3, #0 + 8003a00: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8003a04: e00c b.n 8003a20 + { + empty_page[i] = M24C64_EMPTY_CELL_VALUE; + 8003a06: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8003a0a: f107 0230 add.w r2, r7, #48 ; 0x30 + 8003a0e: 4413 add r3, r2 + 8003a10: 22ff movs r2, #255 ; 0xff + 8003a12: f803 2c24 strb.w r2, [r3, #-36] + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 8003a16: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8003a1a: 3301 adds r3, #1 + 8003a1c: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8003a20: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8003a24: 2b1f cmp r3, #31 + 8003a26: d9ee bls.n 8003a06 + } + + m24c64_write_page(&empty_page[0], page_address); + 8003a28: 79fa ldrb r2, [r7, #7] + 8003a2a: f107 030c add.w r3, r7, #12 + 8003a2e: 4611 mov r1, r2 + 8003a30: 4618 mov r0, r3 + 8003a32: f7ff ff61 bl 80038f8 +} + 8003a36: bf00 nop + 8003a38: 3730 adds r7, #48 ; 0x30 + 8003a3a: 46bd mov sp, r7 + 8003a3c: bd80 pop {r7, pc} + +08003a3e : + + + +void m24c64_erase_all(void) +{ + 8003a3e: b580 push {r7, lr} + 8003a40: b082 sub sp, #8 + 8003a42: af00 add r7, sp, #0 + for (uint16_t page = 0; page < M24C64_PAGES_TOTAL; page++) + 8003a44: 2300 movs r3, #0 + 8003a46: 80fb strh r3, [r7, #6] + 8003a48: e007 b.n 8003a5a + { + m24c64_erase_page(page); + 8003a4a: 88fb ldrh r3, [r7, #6] + 8003a4c: b2db uxtb r3, r3 + 8003a4e: 4618 mov r0, r3 + 8003a50: f7ff ffd0 bl 80039f4 + for (uint16_t page = 0; page < M24C64_PAGES_TOTAL; page++) + 8003a54: 88fb ldrh r3, [r7, #6] + 8003a56: 3301 adds r3, #1 + 8003a58: 80fb strh r3, [r7, #6] + 8003a5a: 88fb ldrh r3, [r7, #6] + 8003a5c: 2bff cmp r3, #255 ; 0xff + 8003a5e: d9f4 bls.n 8003a4a + } +} + 8003a60: bf00 nop + 8003a62: 3708 adds r7, #8 + 8003a64: 46bd mov sp, r7 + 8003a66: bd80 pop {r7, pc} + +08003a68 <__enable_irq>: +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } + 8003a68: b480 push {r7} + 8003a6a: af00 add r7, sp, #0 + 8003a6c: b662 cpsie i + 8003a6e: bf00 nop + 8003a70: 46bd mov sp, r7 + 8003a72: bc80 pop {r7} + 8003a74: 4770 bx lr + ... + +08003a78
: + + + +//PROGRAM +int main(void) +{ + 8003a78: b580 push {r7, lr} + 8003a7a: b082 sub sp, #8 + 8003a7c: af00 add r7, sp, #0 + gpio_init(); + 8003a7e: f7fd fe51 bl 8001724 + timers_init(); + 8003a82: f005 fd03 bl 800948c + spi1_init(); + 8003a86: f005 f9d1 bl 8008e2c + spi2_init(); + 8003a8a: f005 fa2b bl 8008ee4 + i2c_init(); + 8003a8e: f7fe fde9 bl 8002664 + uart_dma_init(); + 8003a92: f005 fe67 bl 8009764 + settings_load(); + 8003a96: f004 ff59 bl 800894c + ssd1306_init(); + 8003a9a: f005 fab3 bl 8009004 + si4463_init(); + 8003a9e: f005 f819 bl 8008ad4 + ext_int_init(); + 8003aa2: f7fe f845 bl 8001b30 + adc_init(); + 8003aa6: f7fd fc3b bl 8001320 + adc_get_bat_voltage(); + 8003aaa: f7fd fc85 bl 80013b8 + init_lrns(); + 8003aae: f7fe fe11 bl 80026d4 + init_menu(); + 8003ab2: f000 f9cb bl 8003e4c + init_points(); + 8003ab6: f004 f8d3 bl 8007c60 + + p_settings = get_settings(); + 8003aba: f004 ff3d bl 8008938 + 8003abe: 4602 mov r2, r0 + 8003ac0: 4b46 ldr r3, [pc, #280] ; (8003bdc ) + 8003ac2: 601a str r2, [r3, #0] + p_gps_num = get_gps_num(); + 8003ac4: f7fe fdc4 bl 8002650 + 8003ac8: 4602 mov r2, r0 + 8003aca: 4b45 ldr r3, [pc, #276] ; (8003be0 ) + 8003acc: 601a str r2, [r3, #0] + p_send_interval_values = get_send_interval_values(); + 8003ace: f004 ff1f bl 8008910 + 8003ad2: 4602 mov r2, r0 + 8003ad4: 4b43 ldr r3, [pc, #268] ; (8003be4 ) + 8003ad6: 601a str r2, [r3, #0] + + ssd1306_bitmap(&startup_screen[0]); + 8003ad8: 4843 ldr r0, [pc, #268] ; (8003be8 ) + 8003ada: f005 fc77 bl 80093cc + ssd1306_update(); + 8003ade: f005 fad7 bl 8009090 + delay_cyc(5000000); + 8003ae2: 4842 ldr r0, [pc, #264] ; (8003bec ) + 8003ae4: f004 fca0 bl 8008428 + draw_current_menu(); + 8003ae8: f000 fbfe bl 80042e8 + + __enable_irq(); + 8003aec: f7ff ffbc bl 8003a68 <__enable_irq> + make_a_beep(); + 8003af0: f005 fcd8 bl 80094a4 + + while (1) + { + //Scan Keys + change_menu(scan_buttons()); + 8003af4: f7fd fd12 bl 800151c + 8003af8: 4603 mov r3, r0 + 8003afa: 4618 mov r0, r3 + 8003afc: f000 fa0a bl 8003f14 + + + //Parse GPS after PPS interrupt or UART DMA overflow + if (main_flags.gps_ready == 1) + 8003b00: 4b3b ldr r3, [pc, #236] ; (8003bf0 ) + 8003b02: 781b ldrb r3, [r3, #0] + 8003b04: 2b01 cmp r3, #1 + 8003b06: d123 bne.n 8003b50 + { + main_flags.gps_ready = 0; + 8003b08: 4b39 ldr r3, [pc, #228] ; (8003bf0 ) + 8003b0a: 2200 movs r2, #0 + 8003b0c: 701a strb r2, [r3, #0] + + + if (parse_gps() == 1) + 8003b0e: f7fe f925 bl 8001d5c + 8003b12: 4603 mov r3, r0 + 8003b14: 2b01 cmp r3, #1 + 8003b16: d115 bne.n 8003b44 + { + if (main_flags.gps_sync == 1) + 8003b18: 4b35 ldr r3, [pc, #212] ; (8003bf0 ) + 8003b1a: 785b ldrb r3, [r3, #1] + 8003b1c: 2b01 cmp r3, #1 + 8003b1e: d10e bne.n 8003b3e + { + if (get_gps_status() == GPS_DATA_VALID) + 8003b20: f7fe fd76 bl 8002610 + 8003b24: 4603 mov r3, r0 + 8003b26: 2b01 cmp r3, #1 + 8003b28: d107 bne.n 8003b3a + { + gps_air_update_my_data(uptime); + 8003b2a: 4b32 ldr r3, [pc, #200] ; (8003bf4 ) + 8003b2c: 681b ldr r3, [r3, #0] + 8003b2e: 4618 mov r0, r3 + 8003b30: f7ff f81c bl 8002b6c + fill_air_packet_with_struct_data(); //fill air data with coordinates of this device (this occur before first time slot interrupt) + 8003b34: f7ff f8b2 bl 8002c9c + 8003b38: e001 b.n 8003b3e + } + else //if PPS exist but data is invalid (rare situation) + { + timer1_stop_reload(); //stop time slot timer due to nothing to transmitt + 8003b3a: f005 fd43 bl 80095c4 + } + } + + draw_current_menu(); + 8003b3e: f000 fbd3 bl 80042e8 + 8003b42: e005 b.n 8003b50 + } + else if (main_flags.gps_sync == 1) + 8003b44: 4b2a ldr r3, [pc, #168] ; (8003bf0 ) + 8003b46: 785b ldrb r3, [r3, #1] + 8003b48: 2b01 cmp r3, #1 + 8003b4a: d101 bne.n 8003b50 + { + timer1_stop_reload(); //stop time slot timer due to nothing to transmitt + 8003b4c: f005 fd3a bl 80095c4 + } + } + + + //Extract received packet + if (main_flags.rx_ready == 1) + 8003b50: 4b27 ldr r3, [pc, #156] ; (8003bf0 ) + 8003b52: 789b ldrb r3, [r3, #2] + 8003b54: 2b01 cmp r3, #1 + 8003b56: d10c bne.n 8003b72 + { + main_flags.rx_ready = 0; + 8003b58: 4b25 ldr r3, [pc, #148] ; (8003bf0 ) + 8003b5a: 2200 movs r2, #0 + 8003b5c: 709a strb r2, [r3, #2] + + if (si4463_get_rx_packet()) + 8003b5e: f005 f8e7 bl 8008d30 + 8003b62: 4603 mov r3, r0 + 8003b64: 2b00 cmp r3, #0 + 8003b66: d004 beq.n 8003b72 + { + fill_struct_with_air_packet_data(uptime); //parse air data from another device (which has ended TX in the current time_slot) + 8003b68: 4b22 ldr r3, [pc, #136] ; (8003bf4 ) + 8003b6a: 681b ldr r3, [r3, #0] + 8003b6c: 4618 mov r0, r3 + 8003b6e: f7ff f99f bl 8002eb0 + } + } + + + //Checks after receiving packets from all devices; performing beep + if (main_flags.time_slots_end == 1) + 8003b72: 4b1f ldr r3, [pc, #124] ; (8003bf0 ) + 8003b74: 78db ldrb r3, [r3, #3] + 8003b76: 2b01 cmp r3, #1 + 8003b78: d121 bne.n 8003bbe + { + main_flags.time_slots_end = 0; + 8003b7a: 4b1d ldr r3, [pc, #116] ; (8003bf0 ) + 8003b7c: 2200 movs r2, #0 + 8003b7e: 70da strb r2, [r3, #3] + + process_all_devices(); //calculate relative position for each active device + 8003b80: f7fe ffd4 bl 8002b2c + + uint8_t any_alarm_status = 0; + 8003b84: 2300 movs r3, #0 + 8003b86: 71fb strb r3, [r7, #7] + any_alarm_status += check_alarms(); + 8003b88: f7fe fedc bl 8002944 + 8003b8c: 4603 mov r3, r0 + 8003b8e: 461a mov r2, r3 + 8003b90: 79fb ldrb r3, [r7, #7] + 8003b92: 4413 add r3, r2 + 8003b94: 71fb strb r3, [r7, #7] + any_alarm_status += check_timeout(); //check timeout flags and get the result only after the end of the TRX sequence + 8003b96: f7fe ff2d bl 80029f4 + 8003b9a: 4603 mov r3, r0 + 8003b9c: 461a mov r2, r3 + 8003b9e: 79fb ldrb r3, [r7, #7] + 8003ba0: 4413 add r3, r2 + 8003ba2: 71fb strb r3, [r7, #7] + any_alarm_status += check_fence(); + 8003ba4: f7fe ff78 bl 8002a98 + 8003ba8: 4603 mov r3, r0 + 8003baa: 461a mov r2, r3 + 8003bac: 79fb ldrb r3, [r7, #7] + 8003bae: 4413 add r3, r2 + 8003bb0: 71fb strb r3, [r7, #7] + + if (any_alarm_status > 0) + 8003bb2: 79fb ldrb r3, [r7, #7] + 8003bb4: 2b00 cmp r3, #0 + 8003bb6: d09d beq.n 8003af4 + { + make_a_beep(); + 8003bb8: f005 fc74 bl 80094a4 + 8003bbc: e79a b.n 8003af4 + } + + } + else if ((main_flags.battery_low == 1) && (main_flags.gps_sync == 0)) //else check battery low flag + 8003bbe: 4b0c ldr r3, [pc, #48] ; (8003bf0 ) + 8003bc0: 791b ldrb r3, [r3, #4] + 8003bc2: 2b01 cmp r3, #1 + 8003bc4: d196 bne.n 8003af4 + 8003bc6: 4b0a ldr r3, [pc, #40] ; (8003bf0 ) + 8003bc8: 785b ldrb r3, [r3, #1] + 8003bca: 2b00 cmp r3, #0 + 8003bcc: d192 bne.n 8003af4 + { + make_a_beep(); + 8003bce: f005 fc69 bl 80094a4 + main_flags.battery_low = 0; + 8003bd2: 4b07 ldr r3, [pc, #28] ; (8003bf0 ) + 8003bd4: 2200 movs r2, #0 + 8003bd6: 711a strb r2, [r3, #4] + change_menu(scan_buttons()); + 8003bd8: e78c b.n 8003af4 + 8003bda: bf00 nop + 8003bdc: 2000061c .word 0x2000061c + 8003be0: 20000614 .word 0x20000614 + 8003be4: 200007cc .word 0x200007cc + 8003be8: 0800d544 .word 0x0800d544 + 8003bec: 004c4b40 .word 0x004c4b40 + 8003bf0: 20000118 .word 0x20000118 + 8003bf4: 2000010c .word 0x2000010c + +08003bf8 : + + + +//DMA UART RX overflow +void DMA1_Channel5_IRQHandler(void) +{ + 8003bf8: b580 push {r7, lr} + 8003bfa: af00 add r7, sp, #0 + DMA1->IFCR = DMA_IFCR_CGIF5; //clear all interrupt flags for DMA channel 5 + 8003bfc: 4b0b ldr r3, [pc, #44] ; (8003c2c ) + 8003bfe: f44f 3280 mov.w r2, #65536 ; 0x10000 + 8003c02: 605a str r2, [r3, #4] + + uart_dma_stop(); + 8003c04: f005 fe18 bl 8009838 + backup_and_clear_uart_buffer(); + 8003c08: f005 fe36 bl 8009878 + uart_dma_restart(); + 8003c0c: f005 fe22 bl 8009854 + + main_flags.gps_ready = 1; + 8003c10: 4b07 ldr r3, [pc, #28] ; (8003c30 ) + 8003c12: 2201 movs r2, #1 + 8003c14: 701a strb r2, [r3, #0] + main_flags.gps_sync = 0; //no pps signal + 8003c16: 4b06 ldr r3, [pc, #24] ; (8003c30 ) + 8003c18: 2200 movs r2, #0 + 8003c1a: 705a strb r2, [r3, #1] + pps_counter = 0; + 8003c1c: 4b05 ldr r3, [pc, #20] ; (8003c34 ) + 8003c1e: 2200 movs r2, #0 + 8003c20: 601a str r2, [r3, #0] + led_green_off(); + 8003c22: f7fd ffe7 bl 8001bf4 +} + 8003c26: bf00 nop + 8003c28: bd80 pop {r7, pc} + 8003c2a: bf00 nop + 8003c2c: 40020000 .word 0x40020000 + 8003c30: 20000118 .word 0x20000118 + 8003c34: 20000110 .word 0x20000110 + +08003c38 : + + + +//GPS PPS interrupt +void EXTI15_10_IRQHandler(void) +{ + 8003c38: b580 push {r7, lr} + 8003c3a: af00 add r7, sp, #0 + EXTI->PR = EXTI_PR_PR11; //clear interrupt + 8003c3c: 4b25 ldr r3, [pc, #148] ; (8003cd4 ) + 8003c3e: f44f 6200 mov.w r2, #2048 ; 0x800 + 8003c42: 615a str r2, [r3, #20] + timer1_start(); //the first thing to do is start time slot timer right after PPS + 8003c44: f005 fcae bl 80095a4 + + uart_dma_stop(); //fix the data + 8003c48: f005 fdf6 bl 8009838 + backup_and_clear_uart_buffer(); + 8003c4c: f005 fe14 bl 8009878 + uart_dma_restart(); + 8003c50: f005 fe00 bl 8009854 + + pps_counter++; + 8003c54: 4b20 ldr r3, [pc, #128] ; (8003cd8 ) + 8003c56: 681b ldr r3, [r3, #0] + 8003c58: 3301 adds r3, #1 + 8003c5a: 4a1f ldr r2, [pc, #124] ; (8003cd8 ) + 8003c5c: 6013 str r3, [r2, #0] + switch (pps_counter) + 8003c5e: 4b1e ldr r3, [pc, #120] ; (8003cd8 ) + 8003c60: 681b ldr r3, [r3, #0] + 8003c62: 2b01 cmp r3, #1 + 8003c64: d002 beq.n 8003c6c + 8003c66: 2b02 cmp r3, #2 + 8003c68: d009 beq.n 8003c7e + 8003c6a: e011 b.n 8003c90 + { + case 1: //skip first PPS, ignore previous nmea data + timer1_stop_reload(); + 8003c6c: f005 fcaa bl 80095c4 + main_flags.gps_ready = 0; + 8003c70: 4b1a ldr r3, [pc, #104] ; (8003cdc ) + 8003c72: 2200 movs r2, #0 + 8003c74: 701a strb r2, [r3, #0] + main_flags.gps_sync = 0; + 8003c76: 4b19 ldr r3, [pc, #100] ; (8003cdc ) + 8003c78: 2200 movs r2, #0 + 8003c7a: 705a strb r2, [r3, #1] + break; + 8003c7c: e027 b.n 8003cce + + case 2: //skip second PPS, but fix the nmea data acquired after first PPS + timer1_stop_reload(); + 8003c7e: f005 fca1 bl 80095c4 + main_flags.gps_ready = 1; + 8003c82: 4b16 ldr r3, [pc, #88] ; (8003cdc ) + 8003c84: 2201 movs r2, #1 + 8003c86: 701a strb r2, [r3, #0] + main_flags.gps_sync = 0; + 8003c88: 4b14 ldr r3, [pc, #80] ; (8003cdc ) + 8003c8a: 2200 movs r2, #0 + 8003c8c: 705a strb r2, [r3, #1] + break; + 8003c8e: e01e b.n 8003cce + + default: //at the moment, the nmea data, captured after first PPS, is parsed + main_flags.gps_ready = 1; + 8003c90: 4b12 ldr r3, [pc, #72] ; (8003cdc ) + 8003c92: 2201 movs r2, #1 + 8003c94: 701a strb r2, [r3, #0] + main_flags.gps_sync = 1; + 8003c96: 4b11 ldr r3, [pc, #68] ; (8003cdc ) + 8003c98: 2201 movs r2, #1 + 8003c9a: 705a strb r2, [r3, #1] + + if ((p_gps_num->second % p_send_interval_values[p_settings->send_interval_opt]) == 0) //calc division remainder + 8003c9c: 4b10 ldr r3, [pc, #64] ; (8003ce0 ) + 8003c9e: 681b ldr r3, [r3, #0] + 8003ca0: 789b ldrb r3, [r3, #2] + 8003ca2: 4a10 ldr r2, [pc, #64] ; (8003ce4 ) + 8003ca4: 6812 ldr r2, [r2, #0] + 8003ca6: 4910 ldr r1, [pc, #64] ; (8003ce8 ) + 8003ca8: 6809 ldr r1, [r1, #0] + 8003caa: 7949 ldrb r1, [r1, #5] + 8003cac: 440a add r2, r1 + 8003cae: 7812 ldrb r2, [r2, #0] + 8003cb0: fbb3 f1f2 udiv r1, r3, r2 + 8003cb4: fb02 f201 mul.w r2, r2, r1 + 8003cb8: 1a9b subs r3, r3, r2 + 8003cba: b2db uxtb r3, r3 + 8003cbc: 2b00 cmp r3, #0 + 8003cbe: d103 bne.n 8003cc8 + { + main_flags.act_status = 1; //we are ready to show we are in act + 8003cc0: 4b06 ldr r3, [pc, #24] ; (8003cdc ) + 8003cc2: 2201 movs r2, #1 + 8003cc4: 715a strb r2, [r3, #5] + else + { + timer1_stop_reload(); + } + + break; + 8003cc6: e001 b.n 8003ccc + timer1_stop_reload(); + 8003cc8: f005 fc7c bl 80095c4 + break; + 8003ccc: bf00 nop + } +} + 8003cce: bf00 nop + 8003cd0: bd80 pop {r7, pc} + 8003cd2: bf00 nop + 8003cd4: 40010400 .word 0x40010400 + 8003cd8: 20000110 .word 0x20000110 + 8003cdc: 20000118 .word 0x20000118 + 8003ce0: 20000614 .word 0x20000614 + 8003ce4: 200007cc .word 0x200007cc + 8003ce8: 2000061c .word 0x2000061c + +08003cec : + + + +//SI4463 RX interrupt (RX valid or CRC error) +void EXTI9_5_IRQHandler(void) +{ + 8003cec: b480 push {r7} + 8003cee: af00 add r7, sp, #0 + EXTI->PR = EXTI_PR_PR6; //clear interrupt + 8003cf0: 4b04 ldr r3, [pc, #16] ; (8003d04 ) + 8003cf2: 2240 movs r2, #64 ; 0x40 + 8003cf4: 615a str r2, [r3, #20] + + main_flags.rx_ready = 1; + 8003cf6: 4b04 ldr r3, [pc, #16] ; (8003d08 ) + 8003cf8: 2201 movs r2, #1 + 8003cfa: 709a strb r2, [r3, #2] +} + 8003cfc: bf00 nop + 8003cfe: 46bd mov sp, r7 + 8003d00: bc80 pop {r7} + 8003d02: 4770 bx lr + 8003d04: 40010400 .word 0x40010400 + 8003d08: 20000118 .word 0x20000118 + +08003d0c : + +--------------------------------------------------------+ PPS Interrupt, Start Timer1 +*/ + +//Time slot interrupt +void TIM1_UP_IRQHandler(void) +{ + 8003d0c: b580 push {r7, lr} + 8003d0e: af00 add r7, sp, #0 + TIM1->SR &= ~TIM_SR_UIF; //clear interrupt + 8003d10: 4b1b ldr r3, [pc, #108] ; (8003d80 ) + 8003d12: 8a1b ldrh r3, [r3, #16] + 8003d14: b29b uxth r3, r3 + 8003d16: 4a1a ldr r2, [pc, #104] ; (8003d80 ) + 8003d18: f023 0301 bic.w r3, r3, #1 + 8003d1c: b29b uxth r3, r3 + 8003d1e: 8213 strh r3, [r2, #16] + + overflow_counter++; //increment ovf counter (starts from 1) + 8003d20: 4b18 ldr r3, [pc, #96] ; (8003d84 ) + 8003d22: 781b ldrb r3, [r3, #0] + 8003d24: 3301 adds r3, #1 + 8003d26: b2da uxtb r2, r3 + 8003d28: 4b16 ldr r3, [pc, #88] ; (8003d84 ) + 8003d2a: 701a strb r2, [r3, #0] + + if(overflow_counter == (DEVICES_IN_GROUP + 1)) //if interrupt at the end of the last time slot + 8003d2c: 4b15 ldr r3, [pc, #84] ; (8003d84 ) + 8003d2e: 781b ldrb r3, [r3, #0] + 8003d30: 2b07 cmp r3, #7 + 8003d32: d10a bne.n 8003d4a + { + timer1_stop_reload(); + 8003d34: f005 fc46 bl 80095c4 + overflow_counter = 0; + 8003d38: 4b12 ldr r3, [pc, #72] ; (8003d84 ) + 8003d3a: 2200 movs r2, #0 + 8003d3c: 701a strb r2, [r3, #0] + main_flags.time_slots_end = 1; + 8003d3e: 4b12 ldr r3, [pc, #72] ; (8003d88 ) + 8003d40: 2201 movs r2, #1 + 8003d42: 70da strb r2, [r3, #3] + led_green_off(); + 8003d44: f7fd ff56 bl 8001bf4 + 8003d48: e00f b.n 8003d6a + } + else + { + time_slot = overflow_counter; + 8003d4a: 4b0e ldr r3, [pc, #56] ; (8003d84 ) + 8003d4c: 781a ldrb r2, [r3, #0] + 8003d4e: 4b0f ldr r3, [pc, #60] ; (8003d8c ) + 8003d50: 701a strb r2, [r3, #0] + + if (time_slot == p_settings->device_number) + 8003d52: 4b0f ldr r3, [pc, #60] ; (8003d90 ) + 8003d54: 681b ldr r3, [r3, #0] + 8003d56: 781a ldrb r2, [r3, #0] + 8003d58: 4b0c ldr r3, [pc, #48] ; (8003d8c ) + 8003d5a: 781b ldrb r3, [r3, #0] + 8003d5c: 429a cmp r2, r3 + 8003d5e: d102 bne.n 8003d66 + { + si4463_tx_packet(); + 8003d60: f004 ff76 bl 8008c50 + 8003d64: e001 b.n 8003d6a + } + else + { + si4463_start_rx(); + 8003d66: f004 ffbb bl 8008ce0 + } + } + + if (main_flags.act_status == 1) + 8003d6a: 4b07 ldr r3, [pc, #28] ; (8003d88 ) + 8003d6c: 795b ldrb r3, [r3, #5] + 8003d6e: 2b01 cmp r3, #1 + 8003d70: d104 bne.n 8003d7c + { + main_flags.act_status = 0; + 8003d72: 4b05 ldr r3, [pc, #20] ; (8003d88 ) + 8003d74: 2200 movs r2, #0 + 8003d76: 715a strb r2, [r3, #5] + led_green_on(); //make ACT led on only here, after we are shure that gps data is valid (otherwise we would never reach this interrupt) + 8003d78: f7fd ff30 bl 8001bdc + } +} + 8003d7c: bf00 nop + 8003d7e: bd80 pop {r7, pc} + 8003d80: 40012c00 .word 0x40012c00 + 8003d84: 20000114 .word 0x20000114 + 8003d88: 20000118 .word 0x20000118 + 8003d8c: 20000115 .word 0x20000115 + 8003d90: 2000061c .word 0x2000061c + +08003d94 : + + + +//Uptime counter (every 1 second) +void SysTick_Handler(void) +{ + 8003d94: b580 push {r7, lr} + 8003d96: af00 add r7, sp, #0 + uptime++; + 8003d98: 4b09 ldr r3, [pc, #36] ; (8003dc0 ) + 8003d9a: 681b ldr r3, [r3, #0] + 8003d9c: 3301 adds r3, #1 + 8003d9e: 4a08 ldr r2, [pc, #32] ; (8003dc0 ) + 8003da0: 6013 str r3, [r2, #0] + + main_flags.battery_low = adc_get_bat_voltage(); + 8003da2: f7fd fb09 bl 80013b8 + 8003da6: 4603 mov r3, r0 + 8003da8: 461a mov r2, r3 + 8003daa: 4b06 ldr r3, [pc, #24] ; (8003dc4 ) + 8003dac: 711a strb r2, [r3, #4] + + calc_timeout(uptime); //always calculate timeout for each device, even if this function is disabled + 8003dae: 4b04 ldr r3, [pc, #16] ; (8003dc0 ) + 8003db0: 681b ldr r3, [r3, #0] + 8003db2: 4618 mov r0, r3 + 8003db4: f7fe fdec bl 8002990 + check_timeout(); //also check timeout in order to set/reset timeout flags + 8003db8: f7fe fe1c bl 80029f4 +} + 8003dbc: bf00 nop + 8003dbe: bd80 pop {r7, pc} + 8003dc0: 2000010c .word 0x2000010c + 8003dc4: 20000118 .word 0x20000118 + +08003dc8 : + + + +//End of "beep" +void TIM2_IRQHandler(void) +{ + 8003dc8: b580 push {r7, lr} + 8003dca: af00 add r7, sp, #0 + timer2_stop(); + 8003dcc: f005 fc34 bl 8009638 + TIM2->SR &= ~TIM_SR_UIF; //clear gating timer int + 8003dd0: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8003dd4: 8a1b ldrh r3, [r3, #16] + 8003dd6: b29b uxth r3, r3 + 8003dd8: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8003ddc: f023 0301 bic.w r3, r3, #1 + 8003de0: b29b uxth r3, r3 + 8003de2: 8213 strh r3, [r2, #16] + + timer3_stop(); + 8003de4: f005 fc82 bl 80096ec + led_board_off(); + 8003de8: f7fd ff1c bl 8001c24 +} + 8003dec: bf00 nop + 8003dee: bd80 pop {r7, pc} + +08003df0 : + + + +uint32_t get_uptime(void) +{ + 8003df0: b480 push {r7} + 8003df2: af00 add r7, sp, #0 + return uptime; + 8003df4: 4b02 ldr r3, [pc, #8] ; (8003e00 ) + 8003df6: 681b ldr r3, [r3, #0] +} + 8003df8: 4618 mov r0, r3 + 8003dfa: 46bd mov sp, r7 + 8003dfc: bc80 pop {r7} + 8003dfe: 4770 bx lr + 8003e00: 2000010c .word 0x2000010c + +08003e04 : + + + +struct main_flags_struct *get_main_flags(void) +{ + 8003e04: b480 push {r7} + 8003e06: af00 add r7, sp, #0 + return &main_flags; + 8003e08: 4b02 ldr r3, [pc, #8] ; (8003e14 ) +} + 8003e0a: 4618 mov r0, r3 + 8003e0c: 46bd mov sp, r7 + 8003e0e: bc80 pop {r7} + 8003e10: 4770 bx lr + 8003e12: bf00 nop + 8003e14: 20000118 .word 0x20000118 + +08003e18 <__DSB>: +static __INLINE void __DSB() { __ASM volatile ("dsb"); } + 8003e18: b480 push {r7} + 8003e1a: af00 add r7, sp, #0 + 8003e1c: f3bf 8f4f dsb sy + 8003e20: bf00 nop + 8003e22: 46bd mov sp, r7 + 8003e24: bc80 pop {r7} + 8003e26: 4770 bx lr + +08003e28 : + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + 8003e28: b580 push {r7, lr} + 8003e2a: af00 add r7, sp, #0 + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 8003e2c: 4b05 ldr r3, [pc, #20] ; (8003e44 ) + 8003e2e: 68db ldr r3, [r3, #12] + 8003e30: f403 62e0 and.w r2, r3, #1792 ; 0x700 + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + 8003e34: 4903 ldr r1, [pc, #12] ; (8003e44 ) + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 8003e36: 4b04 ldr r3, [pc, #16] ; (8003e48 ) + 8003e38: 4313 orrs r3, r2 + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + 8003e3a: 60cb str r3, [r1, #12] + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + 8003e3c: f7ff ffec bl 8003e18 <__DSB> + while(1); /* wait until reset */ + 8003e40: e7fe b.n 8003e40 + 8003e42: bf00 nop + 8003e44: e000ed00 .word 0xe000ed00 + 8003e48: 05fa0004 .word 0x05fa0004 + +08003e4c : + + + +//Init and show MAIN menu +void init_menu(void) +{ + 8003e4c: b580 push {r7, lr} + 8003e4e: af00 add r7, sp, #0 + p_gps_raw = get_gps_raw(); + 8003e50: f7fe fbf4 bl 800263c + 8003e54: 4602 mov r2, r0 + 8003e56: 4b22 ldr r3, [pc, #136] ; (8003ee0 ) + 8003e58: 601a str r2, [r3, #0] + p_gps_num = get_gps_num(); + 8003e5a: f7fe fbf9 bl 8002650 + 8003e5e: 4602 mov r2, r0 + 8003e60: 4b20 ldr r3, [pc, #128] ; (8003ee4 ) + 8003e62: 601a str r2, [r3, #0] + pp_gps_air = get_gps_air(); + 8003e64: f7ff fb24 bl 80034b0 + 8003e68: 4602 mov r2, r0 + 8003e6a: 4b1f ldr r3, [pc, #124] ; (8003ee8 ) + 8003e6c: 601a str r2, [r3, #0] + pp_gps_rel = get_gps_rel(); + 8003e6e: f7ff fb41 bl 80034f4 + 8003e72: 4602 mov r2, r0 + 8003e74: 4b1d ldr r3, [pc, #116] ; (8003eec ) + 8003e76: 601a str r2, [r3, #0] + pp_dev_aux = get_dev_aux(); + 8003e78: f7ff fb5a bl 8003530 + 8003e7c: 4602 mov r2, r0 + 8003e7e: 4b1c ldr r3, [pc, #112] ; (8003ef0 ) + 8003e80: 601a str r2, [r3, #0] + + pp_memory_slot = get_memory_slot(); + 8003e82: f003 fecd bl 8007c20 + 8003e86: 4602 mov r2, r0 + 8003e88: 4b1a ldr r3, [pc, #104] ; (8003ef4 ) + 8003e8a: 601a str r2, [r3, #0] + + p_settings = get_settings(); + 8003e8c: f004 fd54 bl 8008938 + 8003e90: 4602 mov r2, r0 + 8003e92: 4b19 ldr r3, [pc, #100] ; (8003ef8 ) + 8003e94: 601a str r2, [r3, #0] + settings_copy = *p_settings; + 8003e96: 4b18 ldr r3, [pc, #96] ; (8003ef8 ) + 8003e98: 681a ldr r2, [r3, #0] + 8003e9a: 4b18 ldr r3, [pc, #96] ; (8003efc ) + 8003e9c: 6810 ldr r0, [r2, #0] + 8003e9e: 6851 ldr r1, [r2, #4] + 8003ea0: 6018 str r0, [r3, #0] + 8003ea2: 6059 str r1, [r3, #4] + 8003ea4: 8912 ldrh r2, [r2, #8] + 8003ea6: 811a strh r2, [r3, #8] + + device_number = p_settings->device_number; + 8003ea8: 4b13 ldr r3, [pc, #76] ; (8003ef8 ) + 8003eaa: 681b ldr r3, [r3, #0] + 8003eac: 781a ldrb r2, [r3, #0] + 8003eae: 4b14 ldr r3, [pc, #80] ; (8003f00 ) + 8003eb0: 701a strb r2, [r3, #0] + + p_send_interval_values = get_send_interval_values(); + 8003eb2: f004 fd2d bl 8008910 + 8003eb6: 4602 mov r2, r0 + 8003eb8: 4b12 ldr r3, [pc, #72] ; (8003f04 ) + 8003eba: 601a str r2, [r3, #0] + p_get_tx_power_values = get_tx_power_values(); + 8003ebc: f004 fd32 bl 8008924 + 8003ec0: 4602 mov r2, r0 + 8003ec2: 4b11 ldr r3, [pc, #68] ; (8003f08 ) + 8003ec4: 601a str r2, [r3, #0] + + //init variables + current_each_device = device_number; //set me current + 8003ec6: 4b0e ldr r3, [pc, #56] ; (8003f00 ) + 8003ec8: 781a ldrb r2, [r3, #0] + 8003eca: 4b10 ldr r3, [pc, #64] ; (8003f0c ) + 8003ecc: 701a strb r2, [r3, #0] + current_menu = M_MAIN; + 8003ece: 4b10 ldr r3, [pc, #64] ; (8003f10 ) + 8003ed0: 2201 movs r2, #1 + 8003ed2: 701a strb r2, [r3, #0] + set_current_item(M_MAIN_I_DEVICES); + 8003ed4: 2000 movs r0, #0 + 8003ed6: f000 f9a5 bl 8004224 +} + 8003eda: bf00 nop + 8003edc: bd80 pop {r7, pc} + 8003ede: bf00 nop + 8003ee0: 20000808 .word 0x20000808 + 8003ee4: 20000614 .word 0x20000614 + 8003ee8: 20000804 .word 0x20000804 + 8003eec: 200007d0 .word 0x200007d0 + 8003ef0: 2000083c .word 0x2000083c + 8003ef4: 200007d4 .word 0x200007d4 + 8003ef8: 2000061c .word 0x2000061c + 8003efc: 200007e0 .word 0x200007e0 + 8003f00: 20000738 .word 0x20000738 + 8003f04: 200007cc .word 0x200007cc + 8003f08: 2000080c .word 0x2000080c + 8003f0c: 20000032 .word 0x20000032 + 8003f10: 200007fa .word 0x200007fa + +08003f14 : + + + +//Check for buttons and change menu if needed +void change_menu(uint8_t button_code) +{ + 8003f14: b580 push {r7, lr} + 8003f16: b084 sub sp, #16 + 8003f18: af00 add r7, sp, #0 + 8003f1a: 4603 mov r3, r0 + 8003f1c: 71fb strb r3, [r7, #7] + if (button_code) + 8003f1e: 79fb ldrb r3, [r7, #7] + 8003f20: 2b00 cmp r3, #0 + 8003f22: d051 beq.n 8003fc8 + { + + //search for exclusive operation for this case + for (uint8_t i = 0; menu_exclusive_table[i].current_menu; i++) //until end marker + 8003f24: 2300 movs r3, #0 + 8003f26: 73fb strb r3, [r7, #15] + 8003f28: e019 b.n 8003f5e + { + if (current_menu == menu_exclusive_table[i].current_menu && + 8003f2a: 7bfb ldrb r3, [r7, #15] + 8003f2c: 4a28 ldr r2, [pc, #160] ; (8003fd0 ) + 8003f2e: f812 2033 ldrb.w r2, [r2, r3, lsl #3] + 8003f32: 4b28 ldr r3, [pc, #160] ; (8003fd4 ) + 8003f34: 781b ldrb r3, [r3, #0] + 8003f36: 429a cmp r2, r3 + 8003f38: d10e bne.n 8003f58 + button_code == menu_exclusive_table[i].button_pressed) + 8003f3a: 7bfb ldrb r3, [r7, #15] + 8003f3c: 4a24 ldr r2, [pc, #144] ; (8003fd0 ) + 8003f3e: 00db lsls r3, r3, #3 + 8003f40: 4413 add r3, r2 + 8003f42: 785b ldrb r3, [r3, #1] + if (current_menu == menu_exclusive_table[i].current_menu && + 8003f44: 79fa ldrb r2, [r7, #7] + 8003f46: 429a cmp r2, r3 + 8003f48: d106 bne.n 8003f58 + { + menu_exclusive_table[i].execute_function(); + 8003f4a: 7bfb ldrb r3, [r7, #15] + 8003f4c: 4a20 ldr r2, [pc, #128] ; (8003fd0 ) + 8003f4e: 00db lsls r3, r3, #3 + 8003f50: 4413 add r3, r2 + 8003f52: 685b ldr r3, [r3, #4] + 8003f54: 4798 blx r3 + return; //exit + 8003f56: e037 b.n 8003fc8 + for (uint8_t i = 0; menu_exclusive_table[i].current_menu; i++) //until end marker + 8003f58: 7bfb ldrb r3, [r7, #15] + 8003f5a: 3301 adds r3, #1 + 8003f5c: 73fb strb r3, [r7, #15] + 8003f5e: 7bfb ldrb r3, [r7, #15] + 8003f60: 4a1b ldr r2, [pc, #108] ; (8003fd0 ) + 8003f62: f812 3033 ldrb.w r3, [r2, r3, lsl #3] + 8003f66: 2b00 cmp r3, #0 + 8003f68: d1df bne.n 8003f2a + } + } + + //well, there is no exclusive operations for that case, perform default action + switch (button_code) + 8003f6a: 79fb ldrb r3, [r7, #7] + 8003f6c: 3b01 subs r3, #1 + 8003f6e: 2b09 cmp r3, #9 + 8003f70: d82a bhi.n 8003fc8 + 8003f72: a201 add r2, pc, #4 ; (adr r2, 8003f78 ) + 8003f74: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003f78: 08003fa1 .word 0x08003fa1 + 8003f7c: 08003fc9 .word 0x08003fc9 + 8003f80: 08003fa7 .word 0x08003fa7 + 8003f84: 08003fc9 .word 0x08003fc9 + 8003f88: 08003fad .word 0x08003fad + 8003f8c: 08003fc9 .word 0x08003fc9 + 8003f90: 08003fc9 .word 0x08003fc9 + 8003f94: 08003fb9 .word 0x08003fb9 + 8003f98: 08003fb3 .word 0x08003fb3 + 8003f9c: 08003fbf .word 0x08003fbf + { + case BTN_UP: + scroll_up(); + 8003fa0: f000 f836 bl 8004010 + break; + 8003fa4: e010 b.n 8003fc8 + + case BTN_DOWN: + scroll_down(); + 8003fa6: f000 f852 bl 800404e + break; + 8003faa: e00d b.n 8003fc8 + + case BTN_OK: + switch_forward(); + 8003fac: f000 f86e bl 800408c + break; + 8003fb0: e00a b.n 8003fc8 + + case BTN_ESC: + switch_backward(); + 8003fb2: f000 f8ab bl 800410c + break; + 8003fb6: e007 b.n 8003fc8 + + case BTN_PWR_LONG: + toggle_alarm(); + 8003fb8: f000 f80e bl 8003fd8 + break; + 8003fbc: e004 b.n 8003fc8 + + case BTN_ESC_LONG: + toggle_mute(); + 8003fbe: f005 fa81 bl 80094c4 + draw_current_menu(); + 8003fc2: f000 f991 bl 80042e8 + break; + 8003fc6: bf00 nop + } + + } +} + 8003fc8: 3710 adds r7, #16 + 8003fca: 46bd mov sp, r7 + 8003fcc: bd80 pop {r7, pc} + 8003fce: bf00 nop + 8003fd0: 0800cf48 .word 0x0800cf48 + 8003fd4: 200007fa .word 0x200007fa + +08003fd8 : + + + +//Switch alarm status +void toggle_alarm(void) +{ + 8003fd8: b580 push {r7, lr} + 8003fda: af00 add r7, sp, #0 + if (get_device_flags(device_number, FLAGS_ALARM) == FLAG_ALARM_OFF) + 8003fdc: 4b0b ldr r3, [pc, #44] ; (800400c ) + 8003fde: 781b ldrb r3, [r3, #0] + 8003fe0: 2104 movs r1, #4 + 8003fe2: 4618 mov r0, r3 + 8003fe4: f7fe fc6a bl 80028bc + 8003fe8: 4603 mov r3, r0 + 8003fea: 2b00 cmp r3, #0 + 8003fec: d104 bne.n 8003ff8 + { + set_device_flags(FLAGS_ALARM, FLAG_ALARM_ON); + 8003fee: 2101 movs r1, #1 + 8003ff0: 2004 movs r0, #4 + 8003ff2: f7fe fbe5 bl 80027c0 + 8003ff6: e003 b.n 8004000 + } + else + { + set_device_flags(FLAGS_ALARM, FLAG_ALARM_OFF); + 8003ff8: 2100 movs r1, #0 + 8003ffa: 2004 movs r0, #4 + 8003ffc: f7fe fbe0 bl 80027c0 + } + + check_alarms(); //immediately update alarm indication + 8004000: f7fe fca0 bl 8002944 + draw_current_menu(); + 8004004: f000 f970 bl 80042e8 +} + 8004008: bf00 nop + 800400a: bd80 pop {r7, pc} + 800400c: 20000738 .word 0x20000738 + +08004010 : + + + +//Scroll current menu Up +void scroll_up(void) +{ + 8004010: b580 push {r7, lr} + 8004012: b082 sub sp, #8 + 8004014: af00 add r7, sp, #0 + uint8_t current = get_current_item(); + 8004016: f000 f8a5 bl 8004164 + 800401a: 4603 mov r3, r0 + 800401c: 71fb strb r3, [r7, #7] + uint8_t last = get_last_item(); + 800401e: f000 f8d1 bl 80041c4 + 8004022: 4603 mov r3, r0 + 8004024: 71bb strb r3, [r7, #6] + + if (current == M_ALL_I_FIRST) + 8004026: 79fb ldrb r3, [r7, #7] + 8004028: 2b00 cmp r3, #0 + 800402a: d104 bne.n 8004036 + { + set_current_item(last); + 800402c: 79bb ldrb r3, [r7, #6] + 800402e: 4618 mov r0, r3 + 8004030: f000 f8f8 bl 8004224 + 8004034: e005 b.n 8004042 + } + else + { + set_current_item(current - 1); + 8004036: 79fb ldrb r3, [r7, #7] + 8004038: 3b01 subs r3, #1 + 800403a: b2db uxtb r3, r3 + 800403c: 4618 mov r0, r3 + 800403e: f000 f8f1 bl 8004224 + } + + draw_current_menu(); + 8004042: f000 f951 bl 80042e8 +} + 8004046: bf00 nop + 8004048: 3708 adds r7, #8 + 800404a: 46bd mov sp, r7 + 800404c: bd80 pop {r7, pc} + +0800404e : + + + +//Scroll current menu Down +void scroll_down(void) +{ + 800404e: b580 push {r7, lr} + 8004050: b082 sub sp, #8 + 8004052: af00 add r7, sp, #0 + uint8_t current = get_current_item(); + 8004054: f000 f886 bl 8004164 + 8004058: 4603 mov r3, r0 + 800405a: 71fb strb r3, [r7, #7] + uint8_t last = get_last_item(); + 800405c: f000 f8b2 bl 80041c4 + 8004060: 4603 mov r3, r0 + 8004062: 71bb strb r3, [r7, #6] + + if (current == last) + 8004064: 79fa ldrb r2, [r7, #7] + 8004066: 79bb ldrb r3, [r7, #6] + 8004068: 429a cmp r2, r3 + 800406a: d103 bne.n 8004074 + { + set_current_item(M_ALL_I_FIRST); + 800406c: 2000 movs r0, #0 + 800406e: f000 f8d9 bl 8004224 + 8004072: e005 b.n 8004080 + } + else + { + set_current_item(current + 1); + 8004074: 79fb ldrb r3, [r7, #7] + 8004076: 3301 adds r3, #1 + 8004078: b2db uxtb r3, r3 + 800407a: 4618 mov r0, r3 + 800407c: f000 f8d2 bl 8004224 + } + + draw_current_menu(); + 8004080: f000 f932 bl 80042e8 +} + 8004084: bf00 nop + 8004086: 3708 adds r7, #8 + 8004088: 46bd mov sp, r7 + 800408a: bd80 pop {r7, pc} + +0800408c : + + + +//Switch menu forward by default +void switch_forward(void) +{ + 800408c: b580 push {r7, lr} + 800408e: b082 sub sp, #8 + 8004090: af00 add r7, sp, #0 + for (uint8_t i = 0; menu_forward_table[i].current_menu; i++) + 8004092: 2300 movs r3, #0 + 8004094: 71fb strb r3, [r7, #7] + 8004096: e026 b.n 80040e6 + { + if (current_menu == menu_forward_table[i].current_menu && + 8004098: 79fa ldrb r2, [r7, #7] + 800409a: 491a ldr r1, [pc, #104] ; (8004104 ) + 800409c: 4613 mov r3, r2 + 800409e: 005b lsls r3, r3, #1 + 80040a0: 4413 add r3, r2 + 80040a2: 440b add r3, r1 + 80040a4: 781a ldrb r2, [r3, #0] + 80040a6: 4b18 ldr r3, [pc, #96] ; (8004108 ) + 80040a8: 781b ldrb r3, [r3, #0] + 80040aa: 429a cmp r2, r3 + 80040ac: d118 bne.n 80040e0 + get_current_item() == menu_forward_table[i].current_item) + 80040ae: f000 f859 bl 8004164 + 80040b2: 4603 mov r3, r0 + 80040b4: 4618 mov r0, r3 + 80040b6: 79fa ldrb r2, [r7, #7] + 80040b8: 4912 ldr r1, [pc, #72] ; (8004104 ) + 80040ba: 4613 mov r3, r2 + 80040bc: 005b lsls r3, r3, #1 + 80040be: 4413 add r3, r2 + 80040c0: 440b add r3, r1 + 80040c2: 3301 adds r3, #1 + 80040c4: 781b ldrb r3, [r3, #0] + if (current_menu == menu_forward_table[i].current_menu && + 80040c6: 4298 cmp r0, r3 + 80040c8: d10a bne.n 80040e0 + { + current_menu = menu_forward_table[i].next_menu; + 80040ca: 79fa ldrb r2, [r7, #7] + 80040cc: 490d ldr r1, [pc, #52] ; (8004104 ) + 80040ce: 4613 mov r3, r2 + 80040d0: 005b lsls r3, r3, #1 + 80040d2: 4413 add r3, r2 + 80040d4: 440b add r3, r1 + 80040d6: 3302 adds r3, #2 + 80040d8: 781a ldrb r2, [r3, #0] + 80040da: 4b0b ldr r3, [pc, #44] ; (8004108 ) + 80040dc: 701a strb r2, [r3, #0] + break; + 80040de: e00b b.n 80040f8 + for (uint8_t i = 0; menu_forward_table[i].current_menu; i++) + 80040e0: 79fb ldrb r3, [r7, #7] + 80040e2: 3301 adds r3, #1 + 80040e4: 71fb strb r3, [r7, #7] + 80040e6: 79fa ldrb r2, [r7, #7] + 80040e8: 4906 ldr r1, [pc, #24] ; (8004104 ) + 80040ea: 4613 mov r3, r2 + 80040ec: 005b lsls r3, r3, #1 + 80040ee: 4413 add r3, r2 + 80040f0: 440b add r3, r1 + 80040f2: 781b ldrb r3, [r3, #0] + 80040f4: 2b00 cmp r3, #0 + 80040f6: d1cf bne.n 8004098 + } + } + draw_current_menu(); + 80040f8: f000 f8f6 bl 80042e8 +} + 80040fc: bf00 nop + 80040fe: 3708 adds r7, #8 + 8004100: 46bd mov sp, r7 + 8004102: bd80 pop {r7, pc} + 8004104: 0800d130 .word 0x0800d130 + 8004108: 200007fa .word 0x200007fa + +0800410c : + + + +//Switch menu backward by default +void switch_backward(void) +{ + 800410c: b580 push {r7, lr} + 800410e: b082 sub sp, #8 + 8004110: af00 add r7, sp, #0 + for (uint8_t i = 0; menu_backward_table[i].current_menu; i++) + 8004112: 2300 movs r3, #0 + 8004114: 71fb strb r3, [r7, #7] + 8004116: e015 b.n 8004144 + { + if (current_menu == menu_backward_table[i].current_menu) + 8004118: 79fb ldrb r3, [r7, #7] + 800411a: 4a10 ldr r2, [pc, #64] ; (800415c ) + 800411c: f812 2013 ldrb.w r2, [r2, r3, lsl #1] + 8004120: 4b0f ldr r3, [pc, #60] ; (8004160 ) + 8004122: 781b ldrb r3, [r3, #0] + 8004124: 429a cmp r2, r3 + 8004126: d10a bne.n 800413e + { + set_current_item(M_ALL_I_FIRST); //reset current item before exit + 8004128: 2000 movs r0, #0 + 800412a: f000 f87b bl 8004224 + current_menu = menu_backward_table[i].next_menu; + 800412e: 79fb ldrb r3, [r7, #7] + 8004130: 4a0a ldr r2, [pc, #40] ; (800415c ) + 8004132: 005b lsls r3, r3, #1 + 8004134: 4413 add r3, r2 + 8004136: 785a ldrb r2, [r3, #1] + 8004138: 4b09 ldr r3, [pc, #36] ; (8004160 ) + 800413a: 701a strb r2, [r3, #0] + break; + 800413c: e008 b.n 8004150 + for (uint8_t i = 0; menu_backward_table[i].current_menu; i++) + 800413e: 79fb ldrb r3, [r7, #7] + 8004140: 3301 adds r3, #1 + 8004142: 71fb strb r3, [r7, #7] + 8004144: 79fb ldrb r3, [r7, #7] + 8004146: 4a05 ldr r2, [pc, #20] ; (800415c ) + 8004148: f812 3013 ldrb.w r3, [r2, r3, lsl #1] + 800414c: 2b00 cmp r3, #0 + 800414e: d1e3 bne.n 8004118 + } + } + draw_current_menu(); + 8004150: f000 f8ca bl 80042e8 +} + 8004154: bf00 nop + 8004156: 3708 adds r7, #8 + 8004158: 46bd mov sp, r7 + 800415a: bd80 pop {r7, pc} + 800415c: 0800d16c .word 0x0800d16c + 8004160: 200007fa .word 0x200007fa + +08004164 : + + + +//Get currently selected item in current menu +uint8_t get_current_item(void) +{ + 8004164: b480 push {r7} + 8004166: b083 sub sp, #12 + 8004168: af00 add r7, sp, #0 + for (uint8_t i = 0; item_table[i].curent_menu; i++) + 800416a: 2300 movs r3, #0 + 800416c: 71fb strb r3, [r7, #7] + 800416e: e016 b.n 800419e + { + if (current_menu == item_table[i].curent_menu) + 8004170: 79fa ldrb r2, [r7, #7] + 8004172: 4912 ldr r1, [pc, #72] ; (80041bc ) + 8004174: 4613 mov r3, r2 + 8004176: 005b lsls r3, r3, #1 + 8004178: 4413 add r3, r2 + 800417a: 440b add r3, r1 + 800417c: 781a ldrb r2, [r3, #0] + 800417e: 4b10 ldr r3, [pc, #64] ; (80041c0 ) + 8004180: 781b ldrb r3, [r3, #0] + 8004182: 429a cmp r2, r3 + 8004184: d108 bne.n 8004198 + { + return item_table[i].cur_item; + 8004186: 79fa ldrb r2, [r7, #7] + 8004188: 490c ldr r1, [pc, #48] ; (80041bc ) + 800418a: 4613 mov r3, r2 + 800418c: 005b lsls r3, r3, #1 + 800418e: 4413 add r3, r2 + 8004190: 440b add r3, r1 + 8004192: 3301 adds r3, #1 + 8004194: 781b ldrb r3, [r3, #0] + 8004196: e00c b.n 80041b2 + for (uint8_t i = 0; item_table[i].curent_menu; i++) + 8004198: 79fb ldrb r3, [r7, #7] + 800419a: 3301 adds r3, #1 + 800419c: 71fb strb r3, [r7, #7] + 800419e: 79fa ldrb r2, [r7, #7] + 80041a0: 4906 ldr r1, [pc, #24] ; (80041bc ) + 80041a2: 4613 mov r3, r2 + 80041a4: 005b lsls r3, r3, #1 + 80041a6: 4413 add r3, r2 + 80041a8: 440b add r3, r1 + 80041aa: 781b ldrb r3, [r3, #0] + 80041ac: 2b00 cmp r3, #0 + 80041ae: d1df bne.n 8004170 + } + } + return 0; //automatically return 0 if item not found in item_table[] + 80041b0: 2300 movs r3, #0 +} + 80041b2: 4618 mov r0, r3 + 80041b4: 370c adds r7, #12 + 80041b6: 46bd mov sp, r7 + 80041b8: bc80 pop {r7} + 80041ba: 4770 bx lr + 80041bc: 20000020 .word 0x20000020 + 80041c0: 200007fa .word 0x200007fa + +080041c4 : + + + +//Get last item in current menu +uint8_t get_last_item(void) +{ + 80041c4: b480 push {r7} + 80041c6: b083 sub sp, #12 + 80041c8: af00 add r7, sp, #0 + for (uint8_t i = 0; item_table[i].curent_menu; i++) + 80041ca: 2300 movs r3, #0 + 80041cc: 71fb strb r3, [r7, #7] + 80041ce: e016 b.n 80041fe + { + if (current_menu == item_table[i].curent_menu) + 80041d0: 79fa ldrb r2, [r7, #7] + 80041d2: 4912 ldr r1, [pc, #72] ; (800421c ) + 80041d4: 4613 mov r3, r2 + 80041d6: 005b lsls r3, r3, #1 + 80041d8: 4413 add r3, r2 + 80041da: 440b add r3, r1 + 80041dc: 781a ldrb r2, [r3, #0] + 80041de: 4b10 ldr r3, [pc, #64] ; (8004220 ) + 80041e0: 781b ldrb r3, [r3, #0] + 80041e2: 429a cmp r2, r3 + 80041e4: d108 bne.n 80041f8 + { + return item_table[i].last_item; + 80041e6: 79fa ldrb r2, [r7, #7] + 80041e8: 490c ldr r1, [pc, #48] ; (800421c ) + 80041ea: 4613 mov r3, r2 + 80041ec: 005b lsls r3, r3, #1 + 80041ee: 4413 add r3, r2 + 80041f0: 440b add r3, r1 + 80041f2: 3302 adds r3, #2 + 80041f4: 781b ldrb r3, [r3, #0] + 80041f6: e00c b.n 8004212 + for (uint8_t i = 0; item_table[i].curent_menu; i++) + 80041f8: 79fb ldrb r3, [r7, #7] + 80041fa: 3301 adds r3, #1 + 80041fc: 71fb strb r3, [r7, #7] + 80041fe: 79fa ldrb r2, [r7, #7] + 8004200: 4906 ldr r1, [pc, #24] ; (800421c ) + 8004202: 4613 mov r3, r2 + 8004204: 005b lsls r3, r3, #1 + 8004206: 4413 add r3, r2 + 8004208: 440b add r3, r1 + 800420a: 781b ldrb r3, [r3, #0] + 800420c: 2b00 cmp r3, #0 + 800420e: d1df bne.n 80041d0 + } + } + return 0; //automatically return 0 if item not found in item_table[] + 8004210: 2300 movs r3, #0 +} + 8004212: 4618 mov r0, r3 + 8004214: 370c adds r7, #12 + 8004216: 46bd mov sp, r7 + 8004218: bc80 pop {r7} + 800421a: 4770 bx lr + 800421c: 20000020 .word 0x20000020 + 8004220: 200007fa .word 0x200007fa + +08004224 : + + + +//Set item to be current in current menu +void set_current_item(uint8_t new_value) +{ + 8004224: b480 push {r7} + 8004226: b085 sub sp, #20 + 8004228: af00 add r7, sp, #0 + 800422a: 4603 mov r3, r0 + 800422c: 71fb strb r3, [r7, #7] + for (uint8_t i = 0; item_table[i].curent_menu; i++) + 800422e: 2300 movs r3, #0 + 8004230: 73fb strb r3, [r7, #15] + 8004232: e017 b.n 8004264 + { + if (current_menu == item_table[i].curent_menu) + 8004234: 7bfa ldrb r2, [r7, #15] + 8004236: 4912 ldr r1, [pc, #72] ; (8004280 ) + 8004238: 4613 mov r3, r2 + 800423a: 005b lsls r3, r3, #1 + 800423c: 4413 add r3, r2 + 800423e: 440b add r3, r1 + 8004240: 781a ldrb r2, [r3, #0] + 8004242: 4b10 ldr r3, [pc, #64] ; (8004284 ) + 8004244: 781b ldrb r3, [r3, #0] + 8004246: 429a cmp r2, r3 + 8004248: d109 bne.n 800425e + { + item_table[i].cur_item = new_value; + 800424a: 7bfa ldrb r2, [r7, #15] + 800424c: 490c ldr r1, [pc, #48] ; (8004280 ) + 800424e: 4613 mov r3, r2 + 8004250: 005b lsls r3, r3, #1 + 8004252: 4413 add r3, r2 + 8004254: 440b add r3, r1 + 8004256: 3301 adds r3, #1 + 8004258: 79fa ldrb r2, [r7, #7] + 800425a: 701a strb r2, [r3, #0] + break; + 800425c: e00b b.n 8004276 + for (uint8_t i = 0; item_table[i].curent_menu; i++) + 800425e: 7bfb ldrb r3, [r7, #15] + 8004260: 3301 adds r3, #1 + 8004262: 73fb strb r3, [r7, #15] + 8004264: 7bfa ldrb r2, [r7, #15] + 8004266: 4906 ldr r1, [pc, #24] ; (8004280 ) + 8004268: 4613 mov r3, r2 + 800426a: 005b lsls r3, r3, #1 + 800426c: 4413 add r3, r2 + 800426e: 440b add r3, r1 + 8004270: 781b ldrb r3, [r3, #0] + 8004272: 2b00 cmp r3, #0 + 8004274: d1de bne.n 8004234 + } + } +} + 8004276: bf00 nop + 8004278: 3714 adds r7, #20 + 800427a: 46bd mov sp, r7 + 800427c: bc80 pop {r7} + 800427e: 4770 bx lr + 8004280: 20000020 .word 0x20000020 + 8004284: 200007fa .word 0x200007fa + +08004288 : + + + +//Reset item in any menu +void reset_current_item_in_menu(uint8_t menu) +{ + 8004288: b480 push {r7} + 800428a: b085 sub sp, #20 + 800428c: af00 add r7, sp, #0 + 800428e: 4603 mov r3, r0 + 8004290: 71fb strb r3, [r7, #7] + for (uint8_t i = 0; item_table[i].curent_menu; i++) + 8004292: 2300 movs r3, #0 + 8004294: 73fb strb r3, [r7, #15] + 8004296: e016 b.n 80042c6 + { + if (menu == item_table[i].curent_menu) + 8004298: 7bfa ldrb r2, [r7, #15] + 800429a: 4912 ldr r1, [pc, #72] ; (80042e4 ) + 800429c: 4613 mov r3, r2 + 800429e: 005b lsls r3, r3, #1 + 80042a0: 4413 add r3, r2 + 80042a2: 440b add r3, r1 + 80042a4: 781b ldrb r3, [r3, #0] + 80042a6: 79fa ldrb r2, [r7, #7] + 80042a8: 429a cmp r2, r3 + 80042aa: d109 bne.n 80042c0 + { + item_table[i].cur_item = M_ALL_I_FIRST; + 80042ac: 7bfa ldrb r2, [r7, #15] + 80042ae: 490d ldr r1, [pc, #52] ; (80042e4 ) + 80042b0: 4613 mov r3, r2 + 80042b2: 005b lsls r3, r3, #1 + 80042b4: 4413 add r3, r2 + 80042b6: 440b add r3, r1 + 80042b8: 3301 adds r3, #1 + 80042ba: 2200 movs r2, #0 + 80042bc: 701a strb r2, [r3, #0] + break; + 80042be: e00b b.n 80042d8 + for (uint8_t i = 0; item_table[i].curent_menu; i++) + 80042c0: 7bfb ldrb r3, [r7, #15] + 80042c2: 3301 adds r3, #1 + 80042c4: 73fb strb r3, [r7, #15] + 80042c6: 7bfa ldrb r2, [r7, #15] + 80042c8: 4906 ldr r1, [pc, #24] ; (80042e4 ) + 80042ca: 4613 mov r3, r2 + 80042cc: 005b lsls r3, r3, #1 + 80042ce: 4413 add r3, r2 + 80042d0: 440b add r3, r1 + 80042d2: 781b ldrb r3, [r3, #0] + 80042d4: 2b00 cmp r3, #0 + 80042d6: d1df bne.n 8004298 + } + } +} + 80042d8: bf00 nop + 80042da: 3714 adds r7, #20 + 80042dc: 46bd mov sp, r7 + 80042de: bc80 pop {r7} + 80042e0: 4770 bx lr + 80042e2: bf00 nop + 80042e4: 20000020 .word 0x20000020 + +080042e8 : + + + +//Draw current menu (after scroll) +void draw_current_menu(void) +{ + 80042e8: b580 push {r7, lr} + 80042ea: b082 sub sp, #8 + 80042ec: af00 add r7, sp, #0 + for (uint8_t i = 0; menu_draw_table[i].current; i++) + 80042ee: 2300 movs r3, #0 + 80042f0: 71fb strb r3, [r7, #7] + 80042f2: e011 b.n 8004318 + { + if (current_menu == menu_draw_table[i].current) + 80042f4: 79fb ldrb r3, [r7, #7] + 80042f6: 4a0d ldr r2, [pc, #52] ; (800432c ) + 80042f8: f812 2033 ldrb.w r2, [r2, r3, lsl #3] + 80042fc: 4b0c ldr r3, [pc, #48] ; (8004330 ) + 80042fe: 781b ldrb r3, [r3, #0] + 8004300: 429a cmp r2, r3 + 8004302: d106 bne.n 8004312 + { + menu_draw_table[i].action(); + 8004304: 79fb ldrb r3, [r7, #7] + 8004306: 4a09 ldr r2, [pc, #36] ; (800432c ) + 8004308: 00db lsls r3, r3, #3 + 800430a: 4413 add r3, r2 + 800430c: 685b ldr r3, [r3, #4] + 800430e: 4798 blx r3 + break; + 8004310: e008 b.n 8004324 + for (uint8_t i = 0; menu_draw_table[i].current; i++) + 8004312: 79fb ldrb r3, [r7, #7] + 8004314: 3301 adds r3, #1 + 8004316: 71fb strb r3, [r7, #7] + 8004318: 79fb ldrb r3, [r7, #7] + 800431a: 4a04 ldr r2, [pc, #16] ; (800432c ) + 800431c: f812 3033 ldrb.w r3, [r2, r3, lsl #3] + 8004320: 2b00 cmp r3, #0 + 8004322: d1e7 bne.n 80042f4 + } + } +} + 8004324: bf00 nop + 8004326: 3708 adds r7, #8 + 8004328: 46bd mov sp, r7 + 800432a: bd80 pop {r7, pc} + 800432c: 0800d188 .word 0x0800d188 + 8004330: 200007fa .word 0x200007fa + +08004334 : + + + +//MAIN +void draw_main(void) +{ + 8004334: b580 push {r7, lr} + 8004336: af00 add r7, sp, #0 + #define MAIN_ROW (2) + #define MAIN_COL (1) + + ssd1306_clear(); + 8004338: f004 feca bl 80090d0 + ssd1306_print(0, MAIN_COL, "MENU", 0); + 800433c: 2300 movs r3, #0 + 800433e: 4a21 ldr r2, [pc, #132] ; (80043c4 ) + 8004340: 2101 movs r1, #1 + 8004342: 2000 movs r0, #0 + 8004344: f004 ffcb bl 80092de + ssd1306_print(MAIN_ROW, MAIN_COL, "Devices", 0); + 8004348: 2300 movs r3, #0 + 800434a: 4a1f ldr r2, [pc, #124] ; (80043c8 ) + 800434c: 2101 movs r1, #1 + 800434e: 2002 movs r0, #2 + 8004350: f004 ffc5 bl 80092de + ssd1306_print(MAIN_ROW + 1, MAIN_COL, "Radar", 0); + 8004354: 2300 movs r3, #0 + 8004356: 4a1d ldr r2, [pc, #116] ; (80043cc ) + 8004358: 2101 movs r1, #1 + 800435a: 2003 movs r0, #3 + 800435c: f004 ffbf bl 80092de + ssd1306_print(MAIN_ROW + 2, MAIN_COL, "Points", 0); + 8004360: 2300 movs r3, #0 + 8004362: 4a1b ldr r2, [pc, #108] ; (80043d0 ) + 8004364: 2101 movs r1, #1 + 8004366: 2004 movs r0, #4 + 8004368: f004 ffb9 bl 80092de + ssd1306_print(MAIN_ROW + 3, MAIN_COL, "Settings", 0); + 800436c: 2300 movs r3, #0 + 800436e: 4a19 ldr r2, [pc, #100] ; (80043d4 ) + 8004370: 2101 movs r1, #1 + 8004372: 2005 movs r0, #5 + 8004374: f004 ffb3 bl 80092de + ssd1306_print(MAIN_ROW + 4, MAIN_COL, "Info", 0); + 8004378: 2300 movs r3, #0 + 800437a: 4a17 ldr r2, [pc, #92] ; (80043d8 ) + 800437c: 2101 movs r1, #1 + 800437e: 2006 movs r0, #6 + 8004380: f004 ffad bl 80092de + ssd1306_print(MAIN_ROW + get_current_item(), MAIN_COL - 1, ">", 0); + 8004384: f7ff feee bl 8004164 + 8004388: 4603 mov r3, r0 + 800438a: 3302 adds r3, #2 + 800438c: b2d8 uxtb r0, r3 + 800438e: 2300 movs r3, #0 + 8004390: 4a12 ldr r2, [pc, #72] ; (80043dc ) + 8004392: 2100 movs r1, #0 + 8004394: f004 ffa3 bl 80092de + + ssd1306_char_pos(0, 20, SYMB_NOTE, 0); + 8004398: 2300 movs r3, #0 + 800439a: 228f movs r2, #143 ; 0x8f + 800439c: 2114 movs r1, #20 + 800439e: 2000 movs r0, #0 + 80043a0: f004 ff7e bl 80092a0 + if (get_mute_flag() == 1) + 80043a4: f005 f89e bl 80094e4 + 80043a8: 4603 mov r3, r0 + 80043aa: 2b01 cmp r3, #1 + 80043ac: d105 bne.n 80043ba + { + ssd1306_char_pos(0, 19, '!', 0); + 80043ae: 2300 movs r3, #0 + 80043b0: 2221 movs r2, #33 ; 0x21 + 80043b2: 2113 movs r1, #19 + 80043b4: 2000 movs r0, #0 + 80043b6: f004 ff73 bl 80092a0 + } + + ssd1306_update(); + 80043ba: f004 fe69 bl 8009090 +} + 80043be: bf00 nop + 80043c0: bd80 pop {r7, pc} + 80043c2: bf00 nop + 80043c4: 0800c9e0 .word 0x0800c9e0 + 80043c8: 0800c9e8 .word 0x0800c9e8 + 80043cc: 0800c9f0 .word 0x0800c9f0 + 80043d0: 0800c9f8 .word 0x0800c9f8 + 80043d4: 0800ca00 .word 0x0800ca00 + 80043d8: 0800ca0c .word 0x0800ca0c + 80043dc: 0800ca14 .word 0x0800ca14 + +080043e0 : + + + +//DEVICES +void draw_devices(void) +{ + 80043e0: b590 push {r4, r7, lr} + 80043e2: b083 sub sp, #12 + 80043e4: af00 add r7, sp, #0 + ssd1306_clear(); + 80043e6: f004 fe73 bl 80090d0 + ssd1306_bitmap(&devices_blank[0]); + 80043ea: 48b8 ldr r0, [pc, #736] ; (80046cc ) + 80043ec: f004 ffee bl 80093cc + + //TRX + if (get_main_flags()->gps_sync) + 80043f0: f7ff fd08 bl 8003e04 + 80043f4: 4603 mov r3, r0 + 80043f6: 785b ldrb r3, [r3, #1] + 80043f8: 2b00 cmp r3, #0 + 80043fa: d00b beq.n 8004414 + { + ssd1306_char_pos(0, 18, SYMB_ARROW_UP, 0); + 80043fc: 2300 movs r3, #0 + 80043fe: 2280 movs r2, #128 ; 0x80 + 8004400: 2112 movs r1, #18 + 8004402: 2000 movs r0, #0 + 8004404: f004 ff4c bl 80092a0 + ssd1306_char_pos(0, 19, SYMB_ARROW_DOWN, 0); + 8004408: 2300 movs r3, #0 + 800440a: 2281 movs r2, #129 ; 0x81 + 800440c: 2113 movs r1, #19 + 800440e: 2000 movs r0, #0 + 8004410: f004 ff46 bl 80092a0 + } + + //Sattelites + if (p_gps_raw->time[0] == 0) //if no time received then no sattelites at all + 8004414: 4bae ldr r3, [pc, #696] ; (80046d0 ) + 8004416: 681b ldr r3, [r3, #0] + 8004418: 781b ldrb r3, [r3, #0] + 800441a: 2b00 cmp r3, #0 + 800441c: d106 bne.n 800442c + { + ssd1306_char_pos(0, 20, SYMB_NO_SATT, 0); + 800441e: 2300 movs r3, #0 + 8004420: 2282 movs r2, #130 ; 0x82 + 8004422: 2114 movs r1, #20 + 8004424: 2000 movs r0, #0 + 8004426: f004 ff3b bl 80092a0 + 800442a: e02b b.n 8004484 + } + else + { + if (p_gps_num->mode == GPS_POSITION_3DFIX && p_gps_num->status == GPS_DATA_VALID) + 800442c: 4ba9 ldr r3, [pc, #676] ; (80046d4 ) + 800442e: 681b ldr r3, [r3, #0] + 8004430: f893 3037 ldrb.w r3, [r3, #55] ; 0x37 + 8004434: 2b03 cmp r3, #3 + 8004436: d10c bne.n 8004452 + 8004438: 4ba6 ldr r3, [pc, #664] ; (80046d4 ) + 800443a: 681b ldr r3, [r3, #0] + 800443c: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 + 8004440: 2b01 cmp r3, #1 + 8004442: d106 bne.n 8004452 + { + ssd1306_char_pos(0, 20, SYMB_SATT_3D, 0); //3D when data is valid + 8004444: 2300 movs r3, #0 + 8004446: 2285 movs r2, #133 ; 0x85 + 8004448: 2114 movs r1, #20 + 800444a: 2000 movs r0, #0 + 800444c: f004 ff28 bl 80092a0 + 8004450: e018 b.n 8004484 + } + else if (p_gps_num->mode == GPS_POSITION_2DFIX && p_gps_num->status == GPS_DATA_VALID) + 8004452: 4ba0 ldr r3, [pc, #640] ; (80046d4 ) + 8004454: 681b ldr r3, [r3, #0] + 8004456: f893 3037 ldrb.w r3, [r3, #55] ; 0x37 + 800445a: 2b02 cmp r3, #2 + 800445c: d10c bne.n 8004478 + 800445e: 4b9d ldr r3, [pc, #628] ; (80046d4 ) + 8004460: 681b ldr r3, [r3, #0] + 8004462: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 + 8004466: 2b01 cmp r3, #1 + 8004468: d106 bne.n 8004478 + { + ssd1306_char_pos(0, 20, SYMB_SATT_2D, 0); //2D when data is valid + 800446a: 2300 movs r3, #0 + 800446c: 2284 movs r2, #132 ; 0x84 + 800446e: 2114 movs r1, #20 + 8004470: 2000 movs r0, #0 + 8004472: f004 ff15 bl 80092a0 + 8004476: e005 b.n 8004484 + } + else + { + ssd1306_char_pos(0, 20, SYMB_SATT_1D, 0); //if not 2D or 3D then only time is avaliable + 8004478: 2300 movs r3, #0 + 800447a: 2283 movs r2, #131 ; 0x83 + 800447c: 2114 movs r1, #20 + 800447e: 2000 movs r0, #0 + 8004480: f004 ff0e bl 80092a0 + } + } + + uint8_t icon_col = LCD_LAST_COL; + 8004484: 2314 movs r3, #20 + 8004486: 71fb strb r3, [r7, #7] + + //Battery + switch (get_device_flags(device_number, FLAGS_BATTERY)) + 8004488: 4b93 ldr r3, [pc, #588] ; (80046d8 ) + 800448a: 781b ldrb r3, [r3, #0] + 800448c: 2101 movs r1, #1 + 800448e: 4618 mov r0, r3 + 8004490: f7fe fa14 bl 80028bc + 8004494: 4603 mov r3, r0 + 8004496: 2b04 cmp r3, #4 + 8004498: d839 bhi.n 800450e + 800449a: a201 add r2, pc, #4 ; (adr r2, 80044a0 ) + 800449c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80044a0: 080044fd .word 0x080044fd + 80044a4: 080044eb .word 0x080044eb + 80044a8: 080044d9 .word 0x080044d9 + 80044ac: 080044c7 .word 0x080044c7 + 80044b0: 080044b5 .word 0x080044b5 + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_4OF4, 0); + 80044b4: 79f9 ldrb r1, [r7, #7] + 80044b6: 1e4b subs r3, r1, #1 + 80044b8: 71fb strb r3, [r7, #7] + 80044ba: 2300 movs r3, #0 + 80044bc: 228c movs r2, #140 ; 0x8c + 80044be: 2001 movs r0, #1 + 80044c0: f004 feee bl 80092a0 + break; + 80044c4: e023 b.n 800450e + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_3OF4, 0); + 80044c6: 79f9 ldrb r1, [r7, #7] + 80044c8: 1e4b subs r3, r1, #1 + 80044ca: 71fb strb r3, [r7, #7] + 80044cc: 2300 movs r3, #0 + 80044ce: 228b movs r2, #139 ; 0x8b + 80044d0: 2001 movs r0, #1 + 80044d2: f004 fee5 bl 80092a0 + break; + 80044d6: e01a b.n 800450e + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_2OF4, 0); + 80044d8: 79f9 ldrb r1, [r7, #7] + 80044da: 1e4b subs r3, r1, #1 + 80044dc: 71fb strb r3, [r7, #7] + 80044de: 2300 movs r3, #0 + 80044e0: 228a movs r2, #138 ; 0x8a + 80044e2: 2001 movs r0, #1 + 80044e4: f004 fedc bl 80092a0 + break; + 80044e8: e011 b.n 800450e + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_1OF4, 0); + 80044ea: 79f9 ldrb r1, [r7, #7] + 80044ec: 1e4b subs r3, r1, #1 + 80044ee: 71fb strb r3, [r7, #7] + 80044f0: 2300 movs r3, #0 + 80044f2: 2289 movs r2, #137 ; 0x89 + 80044f4: 2001 movs r0, #1 + 80044f6: f004 fed3 bl 80092a0 + break; + 80044fa: e008 b.n 800450e + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(1, icon_col--, SYMB_BAT_0OF4, 0); + 80044fc: 79f9 ldrb r1, [r7, #7] + 80044fe: 1e4b subs r3, r1, #1 + 8004500: 71fb strb r3, [r7, #7] + 8004502: 2300 movs r3, #0 + 8004504: 2288 movs r2, #136 ; 0x88 + 8004506: 2001 movs r0, #1 + 8004508: f004 feca bl 80092a0 + break; + 800450c: bf00 nop + } + + + + //Timeout + if (pp_dev_aux[device_number]->timeout_flag) + 800450e: 4b73 ldr r3, [pc, #460] ; (80046dc ) + 8004510: 681a ldr r2, [r3, #0] + 8004512: 4b71 ldr r3, [pc, #452] ; (80046d8 ) + 8004514: 781b ldrb r3, [r3, #0] + 8004516: 009b lsls r3, r3, #2 + 8004518: 4413 add r3, r2 + 800451a: 681b ldr r3, [r3, #0] + 800451c: 7b1b ldrb r3, [r3, #12] + 800451e: 2b00 cmp r3, #0 + 8004520: d007 beq.n 8004532 + { + ssd1306_char_pos(1, icon_col--, SYMB_TIMEOUT, 0); + 8004522: 79f9 ldrb r1, [r7, #7] + 8004524: 1e4b subs r3, r1, #1 + 8004526: 71fb strb r3, [r7, #7] + 8004528: 2300 movs r3, #0 + 800452a: 2286 movs r2, #134 ; 0x86 + 800452c: 2001 movs r0, #1 + 800452e: f004 feb7 bl 80092a0 + } + + + + //Alarm + if (get_device_flags(device_number, FLAGS_ALARM) == FLAG_ALARM_ON) + 8004532: 4b69 ldr r3, [pc, #420] ; (80046d8 ) + 8004534: 781b ldrb r3, [r3, #0] + 8004536: 2104 movs r1, #4 + 8004538: 4618 mov r0, r3 + 800453a: f7fe f9bf bl 80028bc + 800453e: 4603 mov r3, r0 + 8004540: 2b01 cmp r3, #1 + 8004542: d107 bne.n 8004554 + { + ssd1306_char_pos(1, icon_col--, SYMB_ALARM, 0); + 8004544: 79f9 ldrb r1, [r7, #7] + 8004546: 1e4b subs r3, r1, #1 + 8004548: 71fb strb r3, [r7, #7] + 800454a: 2300 movs r3, #0 + 800454c: 2287 movs r2, #135 ; 0x87 + 800454e: 2001 movs r0, #1 + 8004550: f004 fea6 bl 80092a0 + } + + + + //Devices + uint8_t another_dev_row = ANOTHER_DEVICE_START_ROW; //start to print another devices from row 3 + 8004554: 2303 movs r3, #3 + 8004556: 71bb strb r3, [r7, #6] + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8004558: 2301 movs r3, #1 + 800455a: 717b strb r3, [r7, #5] + 800455c: e28f b.n 8004a7e + { + if (dev == device_number) //if me + 800455e: 4b5e ldr r3, [pc, #376] ; (80046d8 ) + 8004560: 781b ldrb r3, [r3, #0] + 8004562: 797a ldrb r2, [r7, #5] + 8004564: 429a cmp r2, r3 + 8004566: d168 bne.n 800463a + { + //Number + itoa32(dev, &buf[0]); + 8004568: 797b ldrb r3, [r7, #5] + 800456a: 495d ldr r1, [pc, #372] ; (80046e0 ) + 800456c: 4618 mov r0, r3 + 800456e: f004 f953 bl 8008818 + ssd1306_print(1, 0, &buf[0], 0); + 8004572: 2300 movs r3, #0 + 8004574: 4a5a ldr r2, [pc, #360] ; (80046e0 ) + 8004576: 2100 movs r1, #0 + 8004578: 2001 movs r0, #1 + 800457a: f004 feb0 bl 80092de + + //ID + ssd1306_char_pos(1, 2, p_settings->device_id[0], 0); + 800457e: 4b59 ldr r3, [pc, #356] ; (80046e4 ) + 8004580: 681b ldr r3, [r3, #0] + 8004582: 785a ldrb r2, [r3, #1] + 8004584: 2300 movs r3, #0 + 8004586: 2102 movs r1, #2 + 8004588: 2001 movs r0, #1 + 800458a: f004 fe89 bl 80092a0 + ssd1306_char_pos(1, 3, p_settings->device_id[1], 0); + 800458e: 4b55 ldr r3, [pc, #340] ; (80046e4 ) + 8004590: 681b ldr r3, [r3, #0] + 8004592: 789a ldrb r2, [r3, #2] + 8004594: 2300 movs r3, #0 + 8004596: 2103 movs r1, #3 + 8004598: 2001 movs r0, #1 + 800459a: f004 fe81 bl 80092a0 + + //Speed + if (p_gps_num->speed < 10.0) //if speed is small show x.x format + 800459e: 4b4d ldr r3, [pc, #308] ; (80046d4 ) + 80045a0: 681b ldr r3, [r3, #0] + 80045a2: 6a9b ldr r3, [r3, #40] ; 0x28 + 80045a4: 4950 ldr r1, [pc, #320] ; (80046e8 ) + 80045a6: 4618 mov r0, r3 + 80045a8: f7fc fd92 bl 80010d0 <__aeabi_fcmplt> + 80045ac: 4603 mov r3, r0 + 80045ae: 2b00 cmp r3, #0 + 80045b0: d00e beq.n 80045d0 + { + ftoa32(p_gps_num->speed, 1, &buf[0]); + 80045b2: 4b48 ldr r3, [pc, #288] ; (80046d4 ) + 80045b4: 681b ldr r3, [r3, #0] + 80045b6: 6a9b ldr r3, [r3, #40] ; 0x28 + 80045b8: 4a49 ldr r2, [pc, #292] ; (80046e0 ) + 80045ba: 2101 movs r1, #1 + 80045bc: 4618 mov r0, r3 + 80045be: f003 ffdb bl 8008578 + ssd1306_print_viceversa(1, 7, &buf[0], 0); + 80045c2: 2300 movs r3, #0 + 80045c4: 4a46 ldr r2, [pc, #280] ; (80046e0 ) + 80045c6: 2107 movs r1, #7 + 80045c8: 2001 movs r0, #1 + 80045ca: f004 feab bl 8009324 + 80045ce: e010 b.n 80045f2 + } + else //else show int format + { + itoa32(pp_gps_air[dev]->speed, &buf[0]); + 80045d0: 4b46 ldr r3, [pc, #280] ; (80046ec ) + 80045d2: 681a ldr r2, [r3, #0] + 80045d4: 797b ldrb r3, [r7, #5] + 80045d6: 009b lsls r3, r3, #2 + 80045d8: 4413 add r3, r2 + 80045da: 681b ldr r3, [r3, #0] + 80045dc: 7b9b ldrb r3, [r3, #14] + 80045de: 4940 ldr r1, [pc, #256] ; (80046e0 ) + 80045e0: 4618 mov r0, r3 + 80045e2: f004 f919 bl 8008818 + ssd1306_print_viceversa(1, 7, &buf[0], 0); + 80045e6: 2300 movs r3, #0 + 80045e8: 4a3d ldr r2, [pc, #244] ; (80046e0 ) + 80045ea: 2107 movs r1, #7 + 80045ec: 2001 movs r0, #1 + 80045ee: f004 fe99 bl 8009324 + } + + //Course + itoa32(pp_gps_air[dev]->course.as_integer, &buf[0]); + 80045f2: 4b3e ldr r3, [pc, #248] ; (80046ec ) + 80045f4: 681a ldr r2, [r3, #0] + 80045f6: 797b ldrb r3, [r7, #5] + 80045f8: 009b lsls r3, r3, #2 + 80045fa: 4413 add r3, r2 + 80045fc: 681b ldr r3, [r3, #0] + 80045fe: 8a1b ldrh r3, [r3, #16] + 8004600: 4937 ldr r1, [pc, #220] ; (80046e0 ) + 8004602: 4618 mov r0, r3 + 8004604: f004 f908 bl 8008818 + ssd1306_print_viceversa(1, 11, &buf[0], 0); + 8004608: 2300 movs r3, #0 + 800460a: 4a35 ldr r2, [pc, #212] ; (80046e0 ) + 800460c: 210b movs r1, #11 + 800460e: 2001 movs r0, #1 + 8004610: f004 fe88 bl 8009324 + + //Altitude + itoa32(pp_gps_air[dev]->altitude.as_integer, &buf[0]); + 8004614: 4b35 ldr r3, [pc, #212] ; (80046ec ) + 8004616: 681a ldr r2, [r3, #0] + 8004618: 797b ldrb r3, [r7, #5] + 800461a: 009b lsls r3, r3, #2 + 800461c: 4413 add r3, r2 + 800461e: 681b ldr r3, [r3, #0] + 8004620: f9b3 300c ldrsh.w r3, [r3, #12] + 8004624: 492e ldr r1, [pc, #184] ; (80046e0 ) + 8004626: 4618 mov r0, r3 + 8004628: f004 f8f6 bl 8008818 + ssd1306_print_viceversa(1, 16, &buf[0], 0); + 800462c: 2300 movs r3, #0 + 800462e: 4a2c ldr r2, [pc, #176] ; (80046e0 ) + 8004630: 2110 movs r1, #16 + 8004632: 2001 movs r0, #1 + 8004634: f004 fe76 bl 8009324 + 8004638: e21e b.n 8004a78 + } + else + { + if (pp_dev_aux[dev]->exist_flag == 1) //if not me & exist + 800463a: 4b28 ldr r3, [pc, #160] ; (80046dc ) + 800463c: 681a ldr r2, [r3, #0] + 800463e: 797b ldrb r3, [r7, #5] + 8004640: 009b lsls r3, r3, #2 + 8004642: 4413 add r3, r2 + 8004644: 681b ldr r3, [r3, #0] + 8004646: 781b ldrb r3, [r3, #0] + 8004648: 2b01 cmp r3, #1 + 800464a: f040 8215 bne.w 8004a78 + { + //Number + itoa32(dev, &buf[0]); + 800464e: 797b ldrb r3, [r7, #5] + 8004650: 4923 ldr r1, [pc, #140] ; (80046e0 ) + 8004652: 4618 mov r0, r3 + 8004654: f004 f8e0 bl 8008818 + ssd1306_print(another_dev_row, 0, &buf[0], 0); + 8004658: 79b8 ldrb r0, [r7, #6] + 800465a: 2300 movs r3, #0 + 800465c: 4a20 ldr r2, [pc, #128] ; (80046e0 ) + 800465e: 2100 movs r1, #0 + 8004660: f004 fe3d bl 80092de + + //ID + ssd1306_char_pos(another_dev_row, 2, pp_gps_air[dev]->device_id[0], 0); + 8004664: 4b21 ldr r3, [pc, #132] ; (80046ec ) + 8004666: 681a ldr r2, [r3, #0] + 8004668: 797b ldrb r3, [r7, #5] + 800466a: 009b lsls r3, r3, #2 + 800466c: 4413 add r3, r2 + 800466e: 681b ldr r3, [r3, #0] + 8004670: 781a ldrb r2, [r3, #0] + 8004672: 79b8 ldrb r0, [r7, #6] + 8004674: 2300 movs r3, #0 + 8004676: 2102 movs r1, #2 + 8004678: f004 fe12 bl 80092a0 + ssd1306_char_pos(another_dev_row, 3, pp_gps_air[dev]->device_id[1], 0); + 800467c: 4b1b ldr r3, [pc, #108] ; (80046ec ) + 800467e: 681a ldr r2, [r3, #0] + 8004680: 797b ldrb r3, [r7, #5] + 8004682: 009b lsls r3, r3, #2 + 8004684: 4413 add r3, r2 + 8004686: 681b ldr r3, [r3, #0] + 8004688: 785a ldrb r2, [r3, #1] + 800468a: 79b8 ldrb r0, [r7, #6] + 800468c: 2300 movs r3, #0 + 800468e: 2103 movs r1, #3 + 8004690: f004 fe06 bl 80092a0 + + //Distance + if (pp_gps_rel[dev]->distance < 1000) //1-999 m + 8004694: 4b16 ldr r3, [pc, #88] ; (80046f0 ) + 8004696: 681a ldr r2, [r3, #0] + 8004698: 797b ldrb r3, [r7, #5] + 800469a: 009b lsls r3, r3, #2 + 800469c: 4413 add r3, r2 + 800469e: 681b ldr r3, [r3, #0] + 80046a0: 681b ldr r3, [r3, #0] + 80046a2: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 80046a6: d225 bcs.n 80046f4 + { + itoa32(pp_gps_rel[dev]->distance, &buf[0]); + 80046a8: 4b11 ldr r3, [pc, #68] ; (80046f0 ) + 80046aa: 681a ldr r2, [r3, #0] + 80046ac: 797b ldrb r3, [r7, #5] + 80046ae: 009b lsls r3, r3, #2 + 80046b0: 4413 add r3, r2 + 80046b2: 681b ldr r3, [r3, #0] + 80046b4: 681b ldr r3, [r3, #0] + 80046b6: 490a ldr r1, [pc, #40] ; (80046e0 ) + 80046b8: 4618 mov r0, r3 + 80046ba: f004 f8ad bl 8008818 + ssd1306_print_viceversa(another_dev_row, 7, &buf[0], 0); + 80046be: 79b8 ldrb r0, [r7, #6] + 80046c0: 2300 movs r3, #0 + 80046c2: 4a07 ldr r2, [pc, #28] ; (80046e0 ) + 80046c4: 2107 movs r1, #7 + 80046c6: f004 fe2d bl 8009324 + 80046ca: e083 b.n 80047d4 + 80046cc: 0800d944 .word 0x0800d944 + 80046d0: 20000808 .word 0x20000808 + 80046d4: 20000614 .word 0x20000614 + 80046d8: 20000738 .word 0x20000738 + 80046dc: 2000083c .word 0x2000083c + 80046e0: 20000810 .word 0x20000810 + 80046e4: 2000061c .word 0x2000061c + 80046e8: 41200000 .word 0x41200000 + 80046ec: 20000804 .word 0x20000804 + 80046f0: 200007d0 .word 0x200007d0 + } + else if (pp_gps_rel[dev]->distance < 10000) //1.0-9.9 km + 80046f4: 4bb0 ldr r3, [pc, #704] ; (80049b8 ) + 80046f6: 681a ldr r2, [r3, #0] + 80046f8: 797b ldrb r3, [r7, #5] + 80046fa: 009b lsls r3, r3, #2 + 80046fc: 4413 add r3, r2 + 80046fe: 681b ldr r3, [r3, #0] + 8004700: 681b ldr r3, [r3, #0] + 8004702: f242 720f movw r2, #9999 ; 0x270f + 8004706: 4293 cmp r3, r2 + 8004708: d825 bhi.n 8004756 + { + tmpf = pp_gps_rel[dev]->distance / 1000.0; + 800470a: 4bab ldr r3, [pc, #684] ; (80049b8 ) + 800470c: 681a ldr r2, [r3, #0] + 800470e: 797b ldrb r3, [r7, #5] + 8004710: 009b lsls r3, r3, #2 + 8004712: 4413 add r3, r2 + 8004714: 681b ldr r3, [r3, #0] + 8004716: 681b ldr r3, [r3, #0] + 8004718: 4618 mov r0, r3 + 800471a: f7fb fe6b bl 80003f4 <__aeabi_ui2d> + 800471e: f04f 0200 mov.w r2, #0 + 8004722: 4ba6 ldr r3, [pc, #664] ; (80049bc ) + 8004724: f7fc f80a bl 800073c <__aeabi_ddiv> + 8004728: 4603 mov r3, r0 + 800472a: 460c mov r4, r1 + 800472c: 4618 mov r0, r3 + 800472e: 4621 mov r1, r4 + 8004730: f7fc f9d2 bl 8000ad8 <__aeabi_d2f> + 8004734: 4602 mov r2, r0 + 8004736: 4ba2 ldr r3, [pc, #648] ; (80049c0 ) + 8004738: 601a str r2, [r3, #0] + ftoa32(tmpf, 1, &buf[0]); + 800473a: 4ba1 ldr r3, [pc, #644] ; (80049c0 ) + 800473c: 681b ldr r3, [r3, #0] + 800473e: 4aa1 ldr r2, [pc, #644] ; (80049c4 ) + 8004740: 2101 movs r1, #1 + 8004742: 4618 mov r0, r3 + 8004744: f003 ff18 bl 8008578 + ssd1306_print_viceversa(another_dev_row, 7, &buf[0], 0); + 8004748: 79b8 ldrb r0, [r7, #6] + 800474a: 2300 movs r3, #0 + 800474c: 4a9d ldr r2, [pc, #628] ; (80049c4 ) + 800474e: 2107 movs r1, #7 + 8004750: f004 fde8 bl 8009324 + 8004754: e03e b.n 80047d4 + } + else if (pp_gps_rel[dev]->distance < 100000) //10.-99. km + 8004756: 4b98 ldr r3, [pc, #608] ; (80049b8 ) + 8004758: 681a ldr r2, [r3, #0] + 800475a: 797b ldrb r3, [r7, #5] + 800475c: 009b lsls r3, r3, #2 + 800475e: 4413 add r3, r2 + 8004760: 681b ldr r3, [r3, #0] + 8004762: 681b ldr r3, [r3, #0] + 8004764: 4a98 ldr r2, [pc, #608] ; (80049c8 ) + 8004766: 4293 cmp r3, r2 + 8004768: d82e bhi.n 80047c8 + { + tmpf = pp_gps_rel[dev]->distance / 1000.0; + 800476a: 4b93 ldr r3, [pc, #588] ; (80049b8 ) + 800476c: 681a ldr r2, [r3, #0] + 800476e: 797b ldrb r3, [r7, #5] + 8004770: 009b lsls r3, r3, #2 + 8004772: 4413 add r3, r2 + 8004774: 681b ldr r3, [r3, #0] + 8004776: 681b ldr r3, [r3, #0] + 8004778: 4618 mov r0, r3 + 800477a: f7fb fe3b bl 80003f4 <__aeabi_ui2d> + 800477e: f04f 0200 mov.w r2, #0 + 8004782: 4b8e ldr r3, [pc, #568] ; (80049bc ) + 8004784: f7fb ffda bl 800073c <__aeabi_ddiv> + 8004788: 4603 mov r3, r0 + 800478a: 460c mov r4, r1 + 800478c: 4618 mov r0, r3 + 800478e: 4621 mov r1, r4 + 8004790: f7fc f9a2 bl 8000ad8 <__aeabi_d2f> + 8004794: 4602 mov r2, r0 + 8004796: 4b8a ldr r3, [pc, #552] ; (80049c0 ) + 8004798: 601a str r2, [r3, #0] + itoa32((uint32_t)tmpf, &buf[0]); + 800479a: 4b89 ldr r3, [pc, #548] ; (80049c0 ) + 800479c: 681b ldr r3, [r3, #0] + 800479e: 4618 mov r0, r3 + 80047a0: f7fc fce4 bl 800116c <__aeabi_f2uiz> + 80047a4: 4603 mov r3, r0 + 80047a6: 4987 ldr r1, [pc, #540] ; (80049c4 ) + 80047a8: 4618 mov r0, r3 + 80047aa: f004 f835 bl 8008818 + ssd1306_print_viceversa(another_dev_row, 6, &buf[0], 0); + 80047ae: 79b8 ldrb r0, [r7, #6] + 80047b0: 2300 movs r3, #0 + 80047b2: 4a84 ldr r2, [pc, #528] ; (80049c4 ) + 80047b4: 2106 movs r1, #6 + 80047b6: f004 fdb5 bl 8009324 + ssd1306_char_pos(another_dev_row, 7, '.', 0); + 80047ba: 79b8 ldrb r0, [r7, #6] + 80047bc: 2300 movs r3, #0 + 80047be: 222e movs r2, #46 ; 0x2e + 80047c0: 2107 movs r1, #7 + 80047c2: f004 fd6d bl 80092a0 + 80047c6: e005 b.n 80047d4 + } + else // >100 km + { + ssd1306_print(another_dev_row, 5, "...", 0); + 80047c8: 79b8 ldrb r0, [r7, #6] + 80047ca: 2300 movs r3, #0 + 80047cc: 4a7f ldr r2, [pc, #508] ; (80049cc ) + 80047ce: 2105 movs r1, #5 + 80047d0: f004 fd85 bl 80092de + } + + //Heading + itoa32(pp_gps_rel[dev]->heading, &buf[0]); + 80047d4: 4b78 ldr r3, [pc, #480] ; (80049b8 ) + 80047d6: 681a ldr r2, [r3, #0] + 80047d8: 797b ldrb r3, [r7, #5] + 80047da: 009b lsls r3, r3, #2 + 80047dc: 4413 add r3, r2 + 80047de: 681b ldr r3, [r3, #0] + 80047e0: 889b ldrh r3, [r3, #4] + 80047e2: 4978 ldr r1, [pc, #480] ; (80049c4 ) + 80047e4: 4618 mov r0, r3 + 80047e6: f004 f817 bl 8008818 + ssd1306_print_viceversa(another_dev_row, 11, &buf[0], 0); + 80047ea: 79b8 ldrb r0, [r7, #6] + 80047ec: 2300 movs r3, #0 + 80047ee: 4a75 ldr r2, [pc, #468] ; (80049c4 ) + 80047f0: 210b movs r1, #11 + 80047f2: f004 fd97 bl 8009324 + + //Delta Altitude + tmpi16 = pp_gps_rel[dev]->altitude_diff; + 80047f6: 4b70 ldr r3, [pc, #448] ; (80049b8 ) + 80047f8: 681a ldr r2, [r3, #0] + 80047fa: 797b ldrb r3, [r7, #5] + 80047fc: 009b lsls r3, r3, #2 + 80047fe: 4413 add r3, r2 + 8004800: 681b ldr r3, [r3, #0] + 8004802: f9b3 2006 ldrsh.w r2, [r3, #6] + 8004806: 4b72 ldr r3, [pc, #456] ; (80049d0 ) + 8004808: 801a strh r2, [r3, #0] + if (tmpi16 < 0) + 800480a: 4b71 ldr r3, [pc, #452] ; (80049d0 ) + 800480c: f9b3 3000 ldrsh.w r3, [r3] + 8004810: 2b00 cmp r3, #0 + 8004812: da08 bge.n 8004826 + { + tmpi16 *= -1; + 8004814: 4b6e ldr r3, [pc, #440] ; (80049d0 ) + 8004816: f9b3 3000 ldrsh.w r3, [r3] + 800481a: b29b uxth r3, r3 + 800481c: 425b negs r3, r3 + 800481e: b29b uxth r3, r3 + 8004820: b21a sxth r2, r3 + 8004822: 4b6b ldr r3, [pc, #428] ; (80049d0 ) + 8004824: 801a strh r2, [r3, #0] + } + + if (tmpi16 < 1000) //1-999 m + 8004826: 4b6a ldr r3, [pc, #424] ; (80049d0 ) + 8004828: f9b3 3000 ldrsh.w r3, [r3] + 800482c: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8004830: da12 bge.n 8004858 + { + itoa32(pp_gps_rel[dev]->altitude_diff, &buf[0]); + 8004832: 4b61 ldr r3, [pc, #388] ; (80049b8 ) + 8004834: 681a ldr r2, [r3, #0] + 8004836: 797b ldrb r3, [r7, #5] + 8004838: 009b lsls r3, r3, #2 + 800483a: 4413 add r3, r2 + 800483c: 681b ldr r3, [r3, #0] + 800483e: f9b3 3006 ldrsh.w r3, [r3, #6] + 8004842: 4960 ldr r1, [pc, #384] ; (80049c4 ) + 8004844: 4618 mov r0, r3 + 8004846: f003 ffe7 bl 8008818 + ssd1306_print_viceversa(another_dev_row, 16, &buf[0], 0); + 800484a: 79b8 ldrb r0, [r7, #6] + 800484c: 2300 movs r3, #0 + 800484e: 4a5d ldr r2, [pc, #372] ; (80049c4 ) + 8004850: 2110 movs r1, #16 + 8004852: f004 fd67 bl 8009324 + 8004856: e05c b.n 8004912 + } + else if (tmpi16 < 10000) //1.0-9.9 km + 8004858: 4b5d ldr r3, [pc, #372] ; (80049d0 ) + 800485a: f9b3 3000 ldrsh.w r3, [r3] + 800485e: f242 720f movw r2, #9999 ; 0x270f + 8004862: 4293 cmp r3, r2 + 8004864: dc26 bgt.n 80048b4 + { + tmpf = pp_gps_rel[dev]->altitude_diff / 1000.0; + 8004866: 4b54 ldr r3, [pc, #336] ; (80049b8 ) + 8004868: 681a ldr r2, [r3, #0] + 800486a: 797b ldrb r3, [r7, #5] + 800486c: 009b lsls r3, r3, #2 + 800486e: 4413 add r3, r2 + 8004870: 681b ldr r3, [r3, #0] + 8004872: f9b3 3006 ldrsh.w r3, [r3, #6] + 8004876: 4618 mov r0, r3 + 8004878: f7fb fdcc bl 8000414 <__aeabi_i2d> + 800487c: f04f 0200 mov.w r2, #0 + 8004880: 4b4e ldr r3, [pc, #312] ; (80049bc ) + 8004882: f7fb ff5b bl 800073c <__aeabi_ddiv> + 8004886: 4603 mov r3, r0 + 8004888: 460c mov r4, r1 + 800488a: 4618 mov r0, r3 + 800488c: 4621 mov r1, r4 + 800488e: f7fc f923 bl 8000ad8 <__aeabi_d2f> + 8004892: 4602 mov r2, r0 + 8004894: 4b4a ldr r3, [pc, #296] ; (80049c0 ) + 8004896: 601a str r2, [r3, #0] + ftoa32(tmpf, 1, &buf[0]); + 8004898: 4b49 ldr r3, [pc, #292] ; (80049c0 ) + 800489a: 681b ldr r3, [r3, #0] + 800489c: 4a49 ldr r2, [pc, #292] ; (80049c4 ) + 800489e: 2101 movs r1, #1 + 80048a0: 4618 mov r0, r3 + 80048a2: f003 fe69 bl 8008578 + ssd1306_print_viceversa(another_dev_row, 16, &buf[0], 0); + 80048a6: 79b8 ldrb r0, [r7, #6] + 80048a8: 2300 movs r3, #0 + 80048aa: 4a46 ldr r2, [pc, #280] ; (80049c4 ) + 80048ac: 2110 movs r1, #16 + 80048ae: f004 fd39 bl 8009324 + 80048b2: e02e b.n 8004912 + } + else //10.-99. km + { + tmpf = pp_gps_rel[dev]->altitude_diff / 1000.0; + 80048b4: 4b40 ldr r3, [pc, #256] ; (80049b8 ) + 80048b6: 681a ldr r2, [r3, #0] + 80048b8: 797b ldrb r3, [r7, #5] + 80048ba: 009b lsls r3, r3, #2 + 80048bc: 4413 add r3, r2 + 80048be: 681b ldr r3, [r3, #0] + 80048c0: f9b3 3006 ldrsh.w r3, [r3, #6] + 80048c4: 4618 mov r0, r3 + 80048c6: f7fb fda5 bl 8000414 <__aeabi_i2d> + 80048ca: f04f 0200 mov.w r2, #0 + 80048ce: 4b3b ldr r3, [pc, #236] ; (80049bc ) + 80048d0: f7fb ff34 bl 800073c <__aeabi_ddiv> + 80048d4: 4603 mov r3, r0 + 80048d6: 460c mov r4, r1 + 80048d8: 4618 mov r0, r3 + 80048da: 4621 mov r1, r4 + 80048dc: f7fc f8fc bl 8000ad8 <__aeabi_d2f> + 80048e0: 4602 mov r2, r0 + 80048e2: 4b37 ldr r3, [pc, #220] ; (80049c0 ) + 80048e4: 601a str r2, [r3, #0] + itoa32((int32_t)tmpf, &buf[0]); + 80048e6: 4b36 ldr r3, [pc, #216] ; (80049c0 ) + 80048e8: 681b ldr r3, [r3, #0] + 80048ea: 4618 mov r0, r3 + 80048ec: f7fc fc18 bl 8001120 <__aeabi_f2iz> + 80048f0: 4603 mov r3, r0 + 80048f2: 4934 ldr r1, [pc, #208] ; (80049c4 ) + 80048f4: 4618 mov r0, r3 + 80048f6: f003 ff8f bl 8008818 + ssd1306_char_pos(another_dev_row, 16, '.', 0); + 80048fa: 79b8 ldrb r0, [r7, #6] + 80048fc: 2300 movs r3, #0 + 80048fe: 222e movs r2, #46 ; 0x2e + 8004900: 2110 movs r1, #16 + 8004902: f004 fccd bl 80092a0 + ssd1306_print_viceversa(another_dev_row, 15, &buf[0], 0); + 8004906: 79b8 ldrb r0, [r7, #6] + 8004908: 2300 movs r3, #0 + 800490a: 4a2e ldr r2, [pc, #184] ; (80049c4 ) + 800490c: 210f movs r1, #15 + 800490e: f004 fd09 bl 8009324 + } + + if (pp_gps_rel[dev]->altitude_diff > 0) + 8004912: 4b29 ldr r3, [pc, #164] ; (80049b8 ) + 8004914: 681a ldr r2, [r3, #0] + 8004916: 797b ldrb r3, [r7, #5] + 8004918: 009b lsls r3, r3, #2 + 800491a: 4413 add r3, r2 + 800491c: 681b ldr r3, [r3, #0] + 800491e: f9b3 3006 ldrsh.w r3, [r3, #6] + 8004922: 2b00 cmp r3, #0 + 8004924: dd03 ble.n 800492e + { + ssd1306_char('+', 0); + 8004926: 2100 movs r1, #0 + 8004928: 202b movs r0, #43 ; 0x2b + 800492a: f004 fc75 bl 8009218 + } + + + + uint8_t icon_col = LCD_LAST_COL; + 800492e: 2314 movs r3, #20 + 8004930: 713b strb r3, [r7, #4] + + //Battery + if (pp_dev_aux[dev]->memory_point_flag == 0) //dont show battery icon for memory points + 8004932: 4b28 ldr r3, [pc, #160] ; (80049d4 ) + 8004934: 681a ldr r2, [r3, #0] + 8004936: 797b ldrb r3, [r7, #5] + 8004938: 009b lsls r3, r3, #2 + 800493a: 4413 add r3, r2 + 800493c: 681b ldr r3, [r3, #0] + 800493e: 7b9b ldrb r3, [r3, #14] + 8004940: 2b00 cmp r3, #0 + 8004942: d152 bne.n 80049ea + { + switch (get_device_flags(dev, FLAGS_BATTERY)) + 8004944: 797b ldrb r3, [r7, #5] + 8004946: 2101 movs r1, #1 + 8004948: 4618 mov r0, r3 + 800494a: f7fd ffb7 bl 80028bc + 800494e: 4603 mov r3, r0 + 8004950: 2b04 cmp r3, #4 + 8004952: d84a bhi.n 80049ea + 8004954: a201 add r2, pc, #4 ; (adr r2, 800495c ) + 8004956: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800495a: bf00 nop + 800495c: 080049d9 .word 0x080049d9 + 8004960: 080049a7 .word 0x080049a7 + 8004964: 08004995 .word 0x08004995 + 8004968: 08004983 .word 0x08004983 + 800496c: 08004971 .word 0x08004971 + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_4OF4, 0); + 8004970: 7939 ldrb r1, [r7, #4] + 8004972: 1e4b subs r3, r1, #1 + 8004974: 713b strb r3, [r7, #4] + 8004976: 79b8 ldrb r0, [r7, #6] + 8004978: 2300 movs r3, #0 + 800497a: 228c movs r2, #140 ; 0x8c + 800497c: f004 fc90 bl 80092a0 + break; + 8004980: e033 b.n 80049ea + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_3OF4, 0); + 8004982: 7939 ldrb r1, [r7, #4] + 8004984: 1e4b subs r3, r1, #1 + 8004986: 713b strb r3, [r7, #4] + 8004988: 79b8 ldrb r0, [r7, #6] + 800498a: 2300 movs r3, #0 + 800498c: 228b movs r2, #139 ; 0x8b + 800498e: f004 fc87 bl 80092a0 + break; + 8004992: e02a b.n 80049ea + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_2OF4, 0); + 8004994: 7939 ldrb r1, [r7, #4] + 8004996: 1e4b subs r3, r1, #1 + 8004998: 713b strb r3, [r7, #4] + 800499a: 79b8 ldrb r0, [r7, #6] + 800499c: 2300 movs r3, #0 + 800499e: 228a movs r2, #138 ; 0x8a + 80049a0: f004 fc7e bl 80092a0 + break; + 80049a4: e021 b.n 80049ea + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_1OF4, 0); + 80049a6: 7939 ldrb r1, [r7, #4] + 80049a8: 1e4b subs r3, r1, #1 + 80049aa: 713b strb r3, [r7, #4] + 80049ac: 79b8 ldrb r0, [r7, #6] + 80049ae: 2300 movs r3, #0 + 80049b0: 2289 movs r2, #137 ; 0x89 + 80049b2: f004 fc75 bl 80092a0 + break; + 80049b6: e018 b.n 80049ea + 80049b8: 200007d0 .word 0x200007d0 + 80049bc: 408f4000 .word 0x408f4000 + 80049c0: 200007f4 .word 0x200007f4 + 80049c4: 20000810 .word 0x20000810 + 80049c8: 0001869f .word 0x0001869f + 80049cc: 0800ca18 .word 0x0800ca18 + 80049d0: 200007f8 .word 0x200007f8 + 80049d4: 2000083c .word 0x2000083c + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_BAT_0OF4, 0); + 80049d8: 7939 ldrb r1, [r7, #4] + 80049da: 1e4b subs r3, r1, #1 + 80049dc: 713b strb r3, [r7, #4] + 80049de: 79b8 ldrb r0, [r7, #6] + 80049e0: 2300 movs r3, #0 + 80049e2: 2288 movs r2, #136 ; 0x88 + 80049e4: f004 fc5c bl 80092a0 + break; + 80049e8: bf00 nop + } + } + + + //Timeout + if (pp_dev_aux[dev]->memory_point_flag == 0) //dont show timeout icon for memory points + 80049ea: 4b2a ldr r3, [pc, #168] ; (8004a94 ) + 80049ec: 681a ldr r2, [r3, #0] + 80049ee: 797b ldrb r3, [r7, #5] + 80049f0: 009b lsls r3, r3, #2 + 80049f2: 4413 add r3, r2 + 80049f4: 681b ldr r3, [r3, #0] + 80049f6: 7b9b ldrb r3, [r3, #14] + 80049f8: 2b00 cmp r3, #0 + 80049fa: d110 bne.n 8004a1e + { + if (pp_dev_aux[dev]->timeout_flag) + 80049fc: 4b25 ldr r3, [pc, #148] ; (8004a94 ) + 80049fe: 681a ldr r2, [r3, #0] + 8004a00: 797b ldrb r3, [r7, #5] + 8004a02: 009b lsls r3, r3, #2 + 8004a04: 4413 add r3, r2 + 8004a06: 681b ldr r3, [r3, #0] + 8004a08: 7b1b ldrb r3, [r3, #12] + 8004a0a: 2b00 cmp r3, #0 + 8004a0c: d007 beq.n 8004a1e + { + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_TIMEOUT, 0); + 8004a0e: 7939 ldrb r1, [r7, #4] + 8004a10: 1e4b subs r3, r1, #1 + 8004a12: 713b strb r3, [r7, #4] + 8004a14: 79b8 ldrb r0, [r7, #6] + 8004a16: 2300 movs r3, #0 + 8004a18: 2286 movs r2, #134 ; 0x86 + 8004a1a: f004 fc41 bl 80092a0 + } + } + + + //Fence + if (pp_dev_aux[dev]->fence_flag) + 8004a1e: 4b1d ldr r3, [pc, #116] ; (8004a94 ) + 8004a20: 681a ldr r2, [r3, #0] + 8004a22: 797b ldrb r3, [r7, #5] + 8004a24: 009b lsls r3, r3, #2 + 8004a26: 4413 add r3, r2 + 8004a28: 681b ldr r3, [r3, #0] + 8004a2a: 7b5b ldrb r3, [r3, #13] + 8004a2c: 2b00 cmp r3, #0 + 8004a2e: d007 beq.n 8004a40 + { + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_FENCE, 0); + 8004a30: 7939 ldrb r1, [r7, #4] + 8004a32: 1e4b subs r3, r1, #1 + 8004a34: 713b strb r3, [r7, #4] + 8004a36: 79b8 ldrb r0, [r7, #6] + 8004a38: 2300 movs r3, #0 + 8004a3a: 228e movs r2, #142 ; 0x8e + 8004a3c: f004 fc30 bl 80092a0 + } + + + //Alarm + if (pp_dev_aux[dev]->memory_point_flag == 0) //dont show alarm icon for memory points + 8004a40: 4b14 ldr r3, [pc, #80] ; (8004a94 ) + 8004a42: 681a ldr r2, [r3, #0] + 8004a44: 797b ldrb r3, [r7, #5] + 8004a46: 009b lsls r3, r3, #2 + 8004a48: 4413 add r3, r2 + 8004a4a: 681b ldr r3, [r3, #0] + 8004a4c: 7b9b ldrb r3, [r3, #14] + 8004a4e: 2b00 cmp r3, #0 + 8004a50: d10f bne.n 8004a72 + { + if (get_device_flags(dev, FLAGS_ALARM) == FLAG_ALARM_ON) + 8004a52: 797b ldrb r3, [r7, #5] + 8004a54: 2104 movs r1, #4 + 8004a56: 4618 mov r0, r3 + 8004a58: f7fd ff30 bl 80028bc + 8004a5c: 4603 mov r3, r0 + 8004a5e: 2b01 cmp r3, #1 + 8004a60: d107 bne.n 8004a72 + { + ssd1306_char_pos(another_dev_row, icon_col--, SYMB_ALARM, 0); + 8004a62: 7939 ldrb r1, [r7, #4] + 8004a64: 1e4b subs r3, r1, #1 + 8004a66: 713b strb r3, [r7, #4] + 8004a68: 79b8 ldrb r0, [r7, #6] + 8004a6a: 2300 movs r3, #0 + 8004a6c: 2287 movs r2, #135 ; 0x87 + 8004a6e: f004 fc17 bl 80092a0 + } + } + + + another_dev_row++; //set next row + 8004a72: 79bb ldrb r3, [r7, #6] + 8004a74: 3301 adds r3, #1 + 8004a76: 71bb strb r3, [r7, #6] + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8004a78: 797b ldrb r3, [r7, #5] + 8004a7a: 3301 adds r3, #1 + 8004a7c: 717b strb r3, [r7, #5] + 8004a7e: 797b ldrb r3, [r7, #5] + 8004a80: 2b06 cmp r3, #6 + 8004a82: f67f ad6c bls.w 800455e + } + } + } + + ssd1306_update(); + 8004a86: f004 fb03 bl 8009090 +} + 8004a8a: bf00 nop + 8004a8c: 370c adds r7, #12 + 8004a8e: 46bd mov sp, r7 + 8004a90: bd90 pop {r4, r7, pc} + 8004a92: bf00 nop + 8004a94: 2000083c .word 0x2000083c + +08004a98 : + + + +//EACH DEVICE +void draw_each_device(void) +{ + 8004a98: b590 push {r4, r7, lr} + 8004a9a: b083 sub sp, #12 + 8004a9c: af00 add r7, sp, #0 + ssd1306_clear(); + 8004a9e: f004 fb17 bl 80090d0 + + //My status row + uint8_t icon_col = LCD_LAST_COL; + 8004aa2: 2314 movs r3, #20 + 8004aa4: 71fb strb r3, [r7, #7] + + //Battery + switch (get_device_flags(device_number, FLAGS_BATTERY)) + 8004aa6: 4b3e ldr r3, [pc, #248] ; (8004ba0 ) + 8004aa8: 781b ldrb r3, [r3, #0] + 8004aaa: 2101 movs r1, #1 + 8004aac: 4618 mov r0, r3 + 8004aae: f7fd ff05 bl 80028bc + 8004ab2: 4603 mov r3, r0 + 8004ab4: 2b04 cmp r3, #4 + 8004ab6: d83a bhi.n 8004b2e + 8004ab8: a201 add r2, pc, #4 ; (adr r2, 8004ac0 ) + 8004aba: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004abe: bf00 nop + 8004ac0: 08004b1d .word 0x08004b1d + 8004ac4: 08004b0b .word 0x08004b0b + 8004ac8: 08004af9 .word 0x08004af9 + 8004acc: 08004ae7 .word 0x08004ae7 + 8004ad0: 08004ad5 .word 0x08004ad5 + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_4OF4, 0); + 8004ad4: 79f9 ldrb r1, [r7, #7] + 8004ad6: 1e4b subs r3, r1, #1 + 8004ad8: 71fb strb r3, [r7, #7] + 8004ada: 2300 movs r3, #0 + 8004adc: 228c movs r2, #140 ; 0x8c + 8004ade: 2000 movs r0, #0 + 8004ae0: f004 fbde bl 80092a0 + break; + 8004ae4: e023 b.n 8004b2e + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_3OF4, 0); + 8004ae6: 79f9 ldrb r1, [r7, #7] + 8004ae8: 1e4b subs r3, r1, #1 + 8004aea: 71fb strb r3, [r7, #7] + 8004aec: 2300 movs r3, #0 + 8004aee: 228b movs r2, #139 ; 0x8b + 8004af0: 2000 movs r0, #0 + 8004af2: f004 fbd5 bl 80092a0 + break; + 8004af6: e01a b.n 8004b2e + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_2OF4, 0); + 8004af8: 79f9 ldrb r1, [r7, #7] + 8004afa: 1e4b subs r3, r1, #1 + 8004afc: 71fb strb r3, [r7, #7] + 8004afe: 2300 movs r3, #0 + 8004b00: 228a movs r2, #138 ; 0x8a + 8004b02: 2000 movs r0, #0 + 8004b04: f004 fbcc bl 80092a0 + break; + 8004b08: e011 b.n 8004b2e + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_1OF4, 0); + 8004b0a: 79f9 ldrb r1, [r7, #7] + 8004b0c: 1e4b subs r3, r1, #1 + 8004b0e: 71fb strb r3, [r7, #7] + 8004b10: 2300 movs r3, #0 + 8004b12: 2289 movs r2, #137 ; 0x89 + 8004b14: 2000 movs r0, #0 + 8004b16: f004 fbc3 bl 80092a0 + break; + 8004b1a: e008 b.n 8004b2e + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_0OF4, 0); + 8004b1c: 79f9 ldrb r1, [r7, #7] + 8004b1e: 1e4b subs r3, r1, #1 + 8004b20: 71fb strb r3, [r7, #7] + 8004b22: 2300 movs r3, #0 + 8004b24: 2288 movs r2, #136 ; 0x88 + 8004b26: 2000 movs r0, #0 + 8004b28: f004 fbba bl 80092a0 + break; + 8004b2c: bf00 nop + } + + + + //Sattelites + if (p_gps_raw->time[0] == 0) //if no time received then no sattelites at all + 8004b2e: 4b1d ldr r3, [pc, #116] ; (8004ba4 ) + 8004b30: 681b ldr r3, [r3, #0] + 8004b32: 781b ldrb r3, [r3, #0] + 8004b34: 2b00 cmp r3, #0 + 8004b36: d108 bne.n 8004b4a + { + ssd1306_char_pos(0, icon_col--, SYMB_NO_SATT, 0); + 8004b38: 79f9 ldrb r1, [r7, #7] + 8004b3a: 1e4b subs r3, r1, #1 + 8004b3c: 71fb strb r3, [r7, #7] + 8004b3e: 2300 movs r3, #0 + 8004b40: 2282 movs r2, #130 ; 0x82 + 8004b42: 2000 movs r0, #0 + 8004b44: f004 fbac bl 80092a0 + 8004b48: e038 b.n 8004bbc + } + else + { + if (p_gps_num->mode == GPS_POSITION_3DFIX && p_gps_num->status == GPS_DATA_VALID) + 8004b4a: 4b17 ldr r3, [pc, #92] ; (8004ba8 ) + 8004b4c: 681b ldr r3, [r3, #0] + 8004b4e: f893 3037 ldrb.w r3, [r3, #55] ; 0x37 + 8004b52: 2b03 cmp r3, #3 + 8004b54: d10e bne.n 8004b74 + 8004b56: 4b14 ldr r3, [pc, #80] ; (8004ba8 ) + 8004b58: 681b ldr r3, [r3, #0] + 8004b5a: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 + 8004b5e: 2b01 cmp r3, #1 + 8004b60: d108 bne.n 8004b74 + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_3D, 0); //3D when data is valid + 8004b62: 79f9 ldrb r1, [r7, #7] + 8004b64: 1e4b subs r3, r1, #1 + 8004b66: 71fb strb r3, [r7, #7] + 8004b68: 2300 movs r3, #0 + 8004b6a: 2285 movs r2, #133 ; 0x85 + 8004b6c: 2000 movs r0, #0 + 8004b6e: f004 fb97 bl 80092a0 + 8004b72: e023 b.n 8004bbc + } + else if (p_gps_num->mode == GPS_POSITION_2DFIX && p_gps_num->status == GPS_DATA_VALID) + 8004b74: 4b0c ldr r3, [pc, #48] ; (8004ba8 ) + 8004b76: 681b ldr r3, [r3, #0] + 8004b78: f893 3037 ldrb.w r3, [r3, #55] ; 0x37 + 8004b7c: 2b02 cmp r3, #2 + 8004b7e: d115 bne.n 8004bac + 8004b80: 4b09 ldr r3, [pc, #36] ; (8004ba8 ) + 8004b82: 681b ldr r3, [r3, #0] + 8004b84: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 + 8004b88: 2b01 cmp r3, #1 + 8004b8a: d10f bne.n 8004bac + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_2D, 0); //2D when data is valid + 8004b8c: 79f9 ldrb r1, [r7, #7] + 8004b8e: 1e4b subs r3, r1, #1 + 8004b90: 71fb strb r3, [r7, #7] + 8004b92: 2300 movs r3, #0 + 8004b94: 2284 movs r2, #132 ; 0x84 + 8004b96: 2000 movs r0, #0 + 8004b98: f004 fb82 bl 80092a0 + 8004b9c: e00e b.n 8004bbc + 8004b9e: bf00 nop + 8004ba0: 20000738 .word 0x20000738 + 8004ba4: 20000808 .word 0x20000808 + 8004ba8: 20000614 .word 0x20000614 + } + else + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_1D, 0); //if not 2D or 3D then only time is avaliable + 8004bac: 79f9 ldrb r1, [r7, #7] + 8004bae: 1e4b subs r3, r1, #1 + 8004bb0: 71fb strb r3, [r7, #7] + 8004bb2: 2300 movs r3, #0 + 8004bb4: 2283 movs r2, #131 ; 0x83 + 8004bb6: 2000 movs r0, #0 + 8004bb8: f004 fb72 bl 80092a0 + } + } + + + //TRX + if (get_main_flags()->gps_sync) + 8004bbc: f7ff f922 bl 8003e04 + 8004bc0: 4603 mov r3, r0 + 8004bc2: 785b ldrb r3, [r3, #1] + 8004bc4: 2b00 cmp r3, #0 + 8004bc6: d00f beq.n 8004be8 + { + ssd1306_char_pos(0, icon_col--, SYMB_ARROW_DOWN, 0); + 8004bc8: 79f9 ldrb r1, [r7, #7] + 8004bca: 1e4b subs r3, r1, #1 + 8004bcc: 71fb strb r3, [r7, #7] + 8004bce: 2300 movs r3, #0 + 8004bd0: 2281 movs r2, #129 ; 0x81 + 8004bd2: 2000 movs r0, #0 + 8004bd4: f004 fb64 bl 80092a0 + ssd1306_char_pos(0, icon_col--, SYMB_ARROW_UP, 0); + 8004bd8: 79f9 ldrb r1, [r7, #7] + 8004bda: 1e4b subs r3, r1, #1 + 8004bdc: 71fb strb r3, [r7, #7] + 8004bde: 2300 movs r3, #0 + 8004be0: 2280 movs r2, #128 ; 0x80 + 8004be2: 2000 movs r0, #0 + 8004be4: f004 fb5c bl 80092a0 + } + + + //Timeout + if (pp_dev_aux[device_number]->timeout_flag) + 8004be8: 4bbe ldr r3, [pc, #760] ; (8004ee4 ) + 8004bea: 681a ldr r2, [r3, #0] + 8004bec: 4bbe ldr r3, [pc, #760] ; (8004ee8 ) + 8004bee: 781b ldrb r3, [r3, #0] + 8004bf0: 009b lsls r3, r3, #2 + 8004bf2: 4413 add r3, r2 + 8004bf4: 681b ldr r3, [r3, #0] + 8004bf6: 7b1b ldrb r3, [r3, #12] + 8004bf8: 2b00 cmp r3, #0 + 8004bfa: d007 beq.n 8004c0c + { + ssd1306_char_pos(0, icon_col--, SYMB_TIMEOUT, 0); + 8004bfc: 79f9 ldrb r1, [r7, #7] + 8004bfe: 1e4b subs r3, r1, #1 + 8004c00: 71fb strb r3, [r7, #7] + 8004c02: 2300 movs r3, #0 + 8004c04: 2286 movs r2, #134 ; 0x86 + 8004c06: 2000 movs r0, #0 + 8004c08: f004 fb4a bl 80092a0 + } + + + //Alarm + if (get_device_flags(device_number, FLAGS_ALARM) == FLAG_ALARM_ON) + 8004c0c: 4bb6 ldr r3, [pc, #728] ; (8004ee8 ) + 8004c0e: 781b ldrb r3, [r3, #0] + 8004c10: 2104 movs r1, #4 + 8004c12: 4618 mov r0, r3 + 8004c14: f7fd fe52 bl 80028bc + 8004c18: 4603 mov r3, r0 + 8004c1a: 2b01 cmp r3, #1 + 8004c1c: d107 bne.n 8004c2e + { + ssd1306_char_pos(0, icon_col--, SYMB_ALARM, 0); + 8004c1e: 79f9 ldrb r1, [r7, #7] + 8004c20: 1e4b subs r3, r1, #1 + 8004c22: 71fb strb r3, [r7, #7] + 8004c24: 2300 movs r3, #0 + 8004c26: 2287 movs r2, #135 ; 0x87 + 8004c28: 2000 movs r0, #0 + 8004c2a: f004 fb39 bl 80092a0 + } + + + + if (current_each_device == device_number) //if me + 8004c2e: 4baf ldr r3, [pc, #700] ; (8004eec ) + 8004c30: 781a ldrb r2, [r3, #0] + 8004c32: 4bad ldr r3, [pc, #692] ; (8004ee8 ) + 8004c34: 781b ldrb r3, [r3, #0] + 8004c36: 429a cmp r2, r3 + 8004c38: f040 8256 bne.w 80050e8 + { + ssd1306_print(0, 0, "#", 0); + 8004c3c: 2300 movs r3, #0 + 8004c3e: 4aac ldr r2, [pc, #688] ; (8004ef0 ) + 8004c40: 2100 movs r1, #0 + 8004c42: 2000 movs r0, #0 + 8004c44: f004 fb4b bl 80092de + itoa32(current_each_device, &buf[0]); + 8004c48: 4ba8 ldr r3, [pc, #672] ; (8004eec ) + 8004c4a: 781b ldrb r3, [r3, #0] + 8004c4c: 49a9 ldr r1, [pc, #676] ; (8004ef4 ) + 8004c4e: 4618 mov r0, r3 + 8004c50: f003 fde2 bl 8008818 + ssd1306_print(0, 1, &buf[0], 0); + 8004c54: 2300 movs r3, #0 + 8004c56: 4aa7 ldr r2, [pc, #668] ; (8004ef4 ) + 8004c58: 2101 movs r1, #1 + 8004c5a: 2000 movs r0, #0 + 8004c5c: f004 fb3f bl 80092de + + ssd1306_char_pos(0, 3, p_settings->device_id[0], 0); + 8004c60: 4ba5 ldr r3, [pc, #660] ; (8004ef8 ) + 8004c62: 681b ldr r3, [r3, #0] + 8004c64: 785a ldrb r2, [r3, #1] + 8004c66: 2300 movs r3, #0 + 8004c68: 2103 movs r1, #3 + 8004c6a: 2000 movs r0, #0 + 8004c6c: f004 fb18 bl 80092a0 + ssd1306_char_pos(0, 4, p_settings->device_id[1], 0); + 8004c70: 4ba1 ldr r3, [pc, #644] ; (8004ef8 ) + 8004c72: 681b ldr r3, [r3, #0] + 8004c74: 789a ldrb r2, [r3, #2] + 8004c76: 2300 movs r3, #0 + 8004c78: 2104 movs r1, #4 + 8004c7a: 2000 movs r0, #0 + 8004c7c: f004 fb10 bl 80092a0 + + ssd1306_print(0, 6, "(me)", 0); + 8004c80: 2300 movs r3, #0 + 8004c82: 4a9e ldr r2, [pc, #632] ; (8004efc ) + 8004c84: 2106 movs r1, #6 + 8004c86: 2000 movs r0, #0 + 8004c88: f004 fb29 bl 80092de + + ssd1306_char_pos(1, 0, p_gps_raw->date[0], 0); + 8004c8c: 4b9c ldr r3, [pc, #624] ; (8004f00 ) + 8004c8e: 681b ldr r3, [r3, #0] + 8004c90: 7b1a ldrb r2, [r3, #12] + 8004c92: 2300 movs r3, #0 + 8004c94: 2100 movs r1, #0 + 8004c96: 2001 movs r0, #1 + 8004c98: f004 fb02 bl 80092a0 + ssd1306_char_pos(1, 1, p_gps_raw->date[1], 0); + 8004c9c: 4b98 ldr r3, [pc, #608] ; (8004f00 ) + 8004c9e: 681b ldr r3, [r3, #0] + 8004ca0: 7b5a ldrb r2, [r3, #13] + 8004ca2: 2300 movs r3, #0 + 8004ca4: 2101 movs r1, #1 + 8004ca6: 2001 movs r0, #1 + 8004ca8: f004 fafa bl 80092a0 + ssd1306_print(1, 2, ".", 0); + 8004cac: 2300 movs r3, #0 + 8004cae: 4a95 ldr r2, [pc, #596] ; (8004f04 ) + 8004cb0: 2102 movs r1, #2 + 8004cb2: 2001 movs r0, #1 + 8004cb4: f004 fb13 bl 80092de + + ssd1306_char_pos(1, 3, p_gps_raw->date[2], 0); + 8004cb8: 4b91 ldr r3, [pc, #580] ; (8004f00 ) + 8004cba: 681b ldr r3, [r3, #0] + 8004cbc: 7b9a ldrb r2, [r3, #14] + 8004cbe: 2300 movs r3, #0 + 8004cc0: 2103 movs r1, #3 + 8004cc2: 2001 movs r0, #1 + 8004cc4: f004 faec bl 80092a0 + ssd1306_char_pos(1, 4, p_gps_raw->date[3], 0); + 8004cc8: 4b8d ldr r3, [pc, #564] ; (8004f00 ) + 8004cca: 681b ldr r3, [r3, #0] + 8004ccc: 7bda ldrb r2, [r3, #15] + 8004cce: 2300 movs r3, #0 + 8004cd0: 2104 movs r1, #4 + 8004cd2: 2001 movs r0, #1 + 8004cd4: f004 fae4 bl 80092a0 + ssd1306_print(1, 5, ".", 0); + 8004cd8: 2300 movs r3, #0 + 8004cda: 4a8a ldr r2, [pc, #552] ; (8004f04 ) + 8004cdc: 2105 movs r1, #5 + 8004cde: 2001 movs r0, #1 + 8004ce0: f004 fafd bl 80092de + + ssd1306_char_pos(1, 6, p_gps_raw->date[4], 0); + 8004ce4: 4b86 ldr r3, [pc, #536] ; (8004f00 ) + 8004ce6: 681b ldr r3, [r3, #0] + 8004ce8: 7c1a ldrb r2, [r3, #16] + 8004cea: 2300 movs r3, #0 + 8004cec: 2106 movs r1, #6 + 8004cee: 2001 movs r0, #1 + 8004cf0: f004 fad6 bl 80092a0 + ssd1306_char_pos(1, 7, p_gps_raw->date[5], 0); + 8004cf4: 4b82 ldr r3, [pc, #520] ; (8004f00 ) + 8004cf6: 681b ldr r3, [r3, #0] + 8004cf8: 7c5a ldrb r2, [r3, #17] + 8004cfa: 2300 movs r3, #0 + 8004cfc: 2107 movs r1, #7 + 8004cfe: 2001 movs r0, #1 + 8004d00: f004 face bl 80092a0 + + ssd1306_char_pos(1, 9, p_gps_raw->time[0], 0); + 8004d04: 4b7e ldr r3, [pc, #504] ; (8004f00 ) + 8004d06: 681b ldr r3, [r3, #0] + 8004d08: 781a ldrb r2, [r3, #0] + 8004d0a: 2300 movs r3, #0 + 8004d0c: 2109 movs r1, #9 + 8004d0e: 2001 movs r0, #1 + 8004d10: f004 fac6 bl 80092a0 + ssd1306_char_pos(1, 10, p_gps_raw->time[1], 0); + 8004d14: 4b7a ldr r3, [pc, #488] ; (8004f00 ) + 8004d16: 681b ldr r3, [r3, #0] + 8004d18: 785a ldrb r2, [r3, #1] + 8004d1a: 2300 movs r3, #0 + 8004d1c: 210a movs r1, #10 + 8004d1e: 2001 movs r0, #1 + 8004d20: f004 fabe bl 80092a0 + ssd1306_print(1, 11, ":", 0); + 8004d24: 2300 movs r3, #0 + 8004d26: 4a78 ldr r2, [pc, #480] ; (8004f08 ) + 8004d28: 210b movs r1, #11 + 8004d2a: 2001 movs r0, #1 + 8004d2c: f004 fad7 bl 80092de + + ssd1306_char_pos(1, 12, p_gps_raw->time[2], 0); + 8004d30: 4b73 ldr r3, [pc, #460] ; (8004f00 ) + 8004d32: 681b ldr r3, [r3, #0] + 8004d34: 789a ldrb r2, [r3, #2] + 8004d36: 2300 movs r3, #0 + 8004d38: 210c movs r1, #12 + 8004d3a: 2001 movs r0, #1 + 8004d3c: f004 fab0 bl 80092a0 + ssd1306_char_pos(1, 13, p_gps_raw->time[3], 0); + 8004d40: 4b6f ldr r3, [pc, #444] ; (8004f00 ) + 8004d42: 681b ldr r3, [r3, #0] + 8004d44: 78da ldrb r2, [r3, #3] + 8004d46: 2300 movs r3, #0 + 8004d48: 210d movs r1, #13 + 8004d4a: 2001 movs r0, #1 + 8004d4c: f004 faa8 bl 80092a0 + ssd1306_print(1, 14, ":", 0); + 8004d50: 2300 movs r3, #0 + 8004d52: 4a6d ldr r2, [pc, #436] ; (8004f08 ) + 8004d54: 210e movs r1, #14 + 8004d56: 2001 movs r0, #1 + 8004d58: f004 fac1 bl 80092de + + ssd1306_char_pos(1, 15, p_gps_raw->time[4], 0); + 8004d5c: 4b68 ldr r3, [pc, #416] ; (8004f00 ) + 8004d5e: 681b ldr r3, [r3, #0] + 8004d60: 791a ldrb r2, [r3, #4] + 8004d62: 2300 movs r3, #0 + 8004d64: 210f movs r1, #15 + 8004d66: 2001 movs r0, #1 + 8004d68: f004 fa9a bl 80092a0 + ssd1306_char_pos(1, 16, p_gps_raw->time[5], 0); + 8004d6c: 4b64 ldr r3, [pc, #400] ; (8004f00 ) + 8004d6e: 681b ldr r3, [r3, #0] + 8004d70: 795a ldrb r2, [r3, #5] + 8004d72: 2300 movs r3, #0 + 8004d74: 2110 movs r1, #16 + 8004d76: 2001 movs r0, #1 + 8004d78: f004 fa92 bl 80092a0 + + ssd1306_print(1, 18, "GMT", 0); + 8004d7c: 2300 movs r3, #0 + 8004d7e: 4a63 ldr r2, [pc, #396] ; (8004f0c ) + 8004d80: 2112 movs r1, #18 + 8004d82: 2001 movs r0, #1 + 8004d84: f004 faab bl 80092de + + ssd1306_print(2, 0, "LAT", 0); + 8004d88: 2300 movs r3, #0 + 8004d8a: 4a61 ldr r2, [pc, #388] ; (8004f10 ) + 8004d8c: 2100 movs r1, #0 + 8004d8e: 2002 movs r0, #2 + 8004d90: f004 faa5 bl 80092de + ftoa32(p_gps_num->latitude.in_deg, 6, &buf[0]); + 8004d94: 4b5f ldr r3, [pc, #380] ; (8004f14 ) + 8004d96: 681b ldr r3, [r3, #0] + 8004d98: 689b ldr r3, [r3, #8] + 8004d9a: 4a56 ldr r2, [pc, #344] ; (8004ef4 ) + 8004d9c: 2106 movs r1, #6 + 8004d9e: 4618 mov r0, r3 + 8004da0: f003 fbea bl 8008578 + ssd1306_print_viceversa(2, 14, &buf[0], 0); + 8004da4: 2300 movs r3, #0 + 8004da6: 4a53 ldr r2, [pc, #332] ; (8004ef4 ) + 8004da8: 210e movs r1, #14 + 8004daa: 2002 movs r0, #2 + 8004dac: f004 faba bl 8009324 + if (p_gps_num->latitude.in_deg >= 0) + 8004db0: 4b58 ldr r3, [pc, #352] ; (8004f14 ) + 8004db2: 681b ldr r3, [r3, #0] + 8004db4: 689b ldr r3, [r3, #8] + 8004db6: f04f 0100 mov.w r1, #0 + 8004dba: 4618 mov r0, r3 + 8004dbc: f7fc f99c bl 80010f8 <__aeabi_fcmpge> + 8004dc0: 4603 mov r3, r0 + 8004dc2: 2b00 cmp r3, #0 + 8004dc4: d00a beq.n 8004ddc + { + ssd1306_char('+', 0); + 8004dc6: 2100 movs r1, #0 + 8004dc8: 202b movs r0, #43 ; 0x2b + 8004dca: f004 fa25 bl 8009218 + ssd1306_print(2, 16, "(N)", 0); + 8004dce: 2300 movs r3, #0 + 8004dd0: 4a51 ldr r2, [pc, #324] ; (8004f18 ) + 8004dd2: 2110 movs r1, #16 + 8004dd4: 2002 movs r0, #2 + 8004dd6: f004 fa82 bl 80092de + 8004dda: e005 b.n 8004de8 + } + else + { + ssd1306_print(2, 16, "(S)", 0); + 8004ddc: 2300 movs r3, #0 + 8004dde: 4a4f ldr r2, [pc, #316] ; (8004f1c ) + 8004de0: 2110 movs r1, #16 + 8004de2: 2002 movs r0, #2 + 8004de4: f004 fa7b bl 80092de + } + + ssd1306_print(3, 0, "LON", 0); + 8004de8: 2300 movs r3, #0 + 8004dea: 4a4d ldr r2, [pc, #308] ; (8004f20 ) + 8004dec: 2100 movs r1, #0 + 8004dee: 2003 movs r0, #3 + 8004df0: f004 fa75 bl 80092de + ftoa32(p_gps_num->longitude.in_deg, 6, &buf[0]); + 8004df4: 4b47 ldr r3, [pc, #284] ; (8004f14 ) + 8004df6: 681b ldr r3, [r3, #0] + 8004df8: 699b ldr r3, [r3, #24] + 8004dfa: 4a3e ldr r2, [pc, #248] ; (8004ef4 ) + 8004dfc: 2106 movs r1, #6 + 8004dfe: 4618 mov r0, r3 + 8004e00: f003 fbba bl 8008578 + ssd1306_print_viceversa(3, 14, &buf[0], 0); + 8004e04: 2300 movs r3, #0 + 8004e06: 4a3b ldr r2, [pc, #236] ; (8004ef4 ) + 8004e08: 210e movs r1, #14 + 8004e0a: 2003 movs r0, #3 + 8004e0c: f004 fa8a bl 8009324 + if (p_gps_num->longitude.in_deg >= 0) + 8004e10: 4b40 ldr r3, [pc, #256] ; (8004f14 ) + 8004e12: 681b ldr r3, [r3, #0] + 8004e14: 699b ldr r3, [r3, #24] + 8004e16: f04f 0100 mov.w r1, #0 + 8004e1a: 4618 mov r0, r3 + 8004e1c: f7fc f96c bl 80010f8 <__aeabi_fcmpge> + 8004e20: 4603 mov r3, r0 + 8004e22: 2b00 cmp r3, #0 + 8004e24: d00a beq.n 8004e3c + { + ssd1306_char('+', 0); + 8004e26: 2100 movs r1, #0 + 8004e28: 202b movs r0, #43 ; 0x2b + 8004e2a: f004 f9f5 bl 8009218 + ssd1306_print(3, 16, "(E)", 0); + 8004e2e: 2300 movs r3, #0 + 8004e30: 4a3c ldr r2, [pc, #240] ; (8004f24 ) + 8004e32: 2110 movs r1, #16 + 8004e34: 2003 movs r0, #3 + 8004e36: f004 fa52 bl 80092de + 8004e3a: e005 b.n 8004e48 + } + else + { + ssd1306_print(3, 16, "(W)", 0); + 8004e3c: 2300 movs r3, #0 + 8004e3e: 4a3a ldr r2, [pc, #232] ; (8004f28 ) + 8004e40: 2110 movs r1, #16 + 8004e42: 2003 movs r0, #3 + 8004e44: f004 fa4b bl 80092de + } + + ssd1306_print(4, 0, "ALT", 0); + 8004e48: 2300 movs r3, #0 + 8004e4a: 4a38 ldr r2, [pc, #224] ; (8004f2c ) + 8004e4c: 2100 movs r1, #0 + 8004e4e: 2004 movs r0, #4 + 8004e50: f004 fa45 bl 80092de + itoa32(p_gps_num->altitude, &buf[0]); + 8004e54: 4b2f ldr r3, [pc, #188] ; (8004f14 ) + 8004e56: 681b ldr r3, [r3, #0] + 8004e58: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004e5a: 4618 mov r0, r3 + 8004e5c: f7fc f960 bl 8001120 <__aeabi_f2iz> + 8004e60: 4603 mov r3, r0 + 8004e62: 4924 ldr r1, [pc, #144] ; (8004ef4 ) + 8004e64: 4618 mov r0, r3 + 8004e66: f003 fcd7 bl 8008818 + ssd1306_print(4, 4, &buf[0], 0); + 8004e6a: 2300 movs r3, #0 + 8004e6c: 4a21 ldr r2, [pc, #132] ; (8004ef4 ) + 8004e6e: 2104 movs r1, #4 + 8004e70: 2004 movs r0, #4 + 8004e72: f004 fa34 bl 80092de + ssd1306_print_next("m", 0); + 8004e76: 2100 movs r1, #0 + 8004e78: 482d ldr r0, [pc, #180] ; (8004f30 ) + 8004e7a: f004 fa8f bl 800939c + + ssd1306_print(4, 11, "FIX", 0); + 8004e7e: 2300 movs r3, #0 + 8004e80: 4a2c ldr r2, [pc, #176] ; (8004f34 ) + 8004e82: 210b movs r1, #11 + 8004e84: 2004 movs r0, #4 + 8004e86: f004 fa2a bl 80092de + if (p_gps_num->status == GPS_DATA_VALID) + 8004e8a: 4b22 ldr r3, [pc, #136] ; (8004f14 ) + 8004e8c: 681b ldr r3, [r3, #0] + 8004e8e: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 + 8004e92: 2b01 cmp r3, #1 + 8004e94: d106 bne.n 8004ea4 + { + ssd1306_print(4, 15, "A/", 0); + 8004e96: 2300 movs r3, #0 + 8004e98: 4a27 ldr r2, [pc, #156] ; (8004f38 ) + 8004e9a: 210f movs r1, #15 + 8004e9c: 2004 movs r0, #4 + 8004e9e: f004 fa1e bl 80092de + 8004ea2: e005 b.n 8004eb0 + } + else + { + ssd1306_print(4, 15, "V/", 0); + 8004ea4: 2300 movs r3, #0 + 8004ea6: 4a25 ldr r2, [pc, #148] ; (8004f3c ) + 8004ea8: 210f movs r1, #15 + 8004eaa: 2004 movs r0, #4 + 8004eac: f004 fa17 bl 80092de + } + + if (p_gps_num->mode == GPS_POSITION_2DFIX) + 8004eb0: 4b18 ldr r3, [pc, #96] ; (8004f14 ) + 8004eb2: 681b ldr r3, [r3, #0] + 8004eb4: f893 3037 ldrb.w r3, [r3, #55] ; 0x37 + 8004eb8: 2b02 cmp r3, #2 + 8004eba: d106 bne.n 8004eca + { + ssd1306_print(4, 17, "2D", 0); + 8004ebc: 2300 movs r3, #0 + 8004ebe: 4a20 ldr r2, [pc, #128] ; (8004f40 ) + 8004ec0: 2111 movs r1, #17 + 8004ec2: 2004 movs r0, #4 + 8004ec4: f004 fa0b bl 80092de + 8004ec8: e044 b.n 8004f54 + } + else if (p_gps_num->mode == GPS_POSITION_3DFIX) + 8004eca: 4b12 ldr r3, [pc, #72] ; (8004f14 ) + 8004ecc: 681b ldr r3, [r3, #0] + 8004ece: f893 3037 ldrb.w r3, [r3, #55] ; 0x37 + 8004ed2: 2b03 cmp r3, #3 + 8004ed4: d138 bne.n 8004f48 + { + ssd1306_print(4, 17, "3D", 0); + 8004ed6: 2300 movs r3, #0 + 8004ed8: 4a1a ldr r2, [pc, #104] ; (8004f44 ) + 8004eda: 2111 movs r1, #17 + 8004edc: 2004 movs r0, #4 + 8004ede: f004 f9fe bl 80092de + 8004ee2: e037 b.n 8004f54 + 8004ee4: 2000083c .word 0x2000083c + 8004ee8: 20000738 .word 0x20000738 + 8004eec: 20000032 .word 0x20000032 + 8004ef0: 0800ca1c .word 0x0800ca1c + 8004ef4: 20000810 .word 0x20000810 + 8004ef8: 2000061c .word 0x2000061c + 8004efc: 0800ca20 .word 0x0800ca20 + 8004f00: 20000808 .word 0x20000808 + 8004f04: 0800ca28 .word 0x0800ca28 + 8004f08: 0800ca2c .word 0x0800ca2c + 8004f0c: 0800ca30 .word 0x0800ca30 + 8004f10: 0800ca34 .word 0x0800ca34 + 8004f14: 20000614 .word 0x20000614 + 8004f18: 0800ca38 .word 0x0800ca38 + 8004f1c: 0800ca3c .word 0x0800ca3c + 8004f20: 0800ca40 .word 0x0800ca40 + 8004f24: 0800ca44 .word 0x0800ca44 + 8004f28: 0800ca48 .word 0x0800ca48 + 8004f2c: 0800ca4c .word 0x0800ca4c + 8004f30: 0800ca50 .word 0x0800ca50 + 8004f34: 0800ca54 .word 0x0800ca54 + 8004f38: 0800ca58 .word 0x0800ca58 + 8004f3c: 0800ca5c .word 0x0800ca5c + 8004f40: 0800ca60 .word 0x0800ca60 + 8004f44: 0800ca64 .word 0x0800ca64 + } + else + { + ssd1306_print(4, 17, "NO", 0); + 8004f48: 2300 movs r3, #0 + 8004f4a: 4aa3 ldr r2, [pc, #652] ; (80051d8 ) + 8004f4c: 2111 movs r1, #17 + 8004f4e: 2004 movs r0, #4 + 8004f50: f004 f9c5 bl 80092de + } + + ssd1306_print(5, 0, "COG", 0); + 8004f54: 2300 movs r3, #0 + 8004f56: 4aa1 ldr r2, [pc, #644] ; (80051dc ) + 8004f58: 2100 movs r1, #0 + 8004f5a: 2005 movs r0, #5 + 8004f5c: f004 f9bf bl 80092de + itoa32(p_gps_num->course, &buf[0]); + 8004f60: 4b9f ldr r3, [pc, #636] ; (80051e0 ) + 8004f62: 681b ldr r3, [r3, #0] + 8004f64: 6adb ldr r3, [r3, #44] ; 0x2c + 8004f66: 4618 mov r0, r3 + 8004f68: f7fc f8da bl 8001120 <__aeabi_f2iz> + 8004f6c: 4603 mov r3, r0 + 8004f6e: 499d ldr r1, [pc, #628] ; (80051e4 ) + 8004f70: 4618 mov r0, r3 + 8004f72: f003 fc51 bl 8008818 + ssd1306_print(5, 4, &buf[0], 0); + 8004f76: 2300 movs r3, #0 + 8004f78: 4a9a ldr r2, [pc, #616] ; (80051e4 ) + 8004f7a: 2104 movs r1, #4 + 8004f7c: 2005 movs r0, #5 + 8004f7e: f004 f9ae bl 80092de + ssd1306_char(SYMB_DEGREE, 0); + 8004f82: 2100 movs r1, #0 + 8004f84: 208d movs r0, #141 ; 0x8d + 8004f86: f004 f947 bl 8009218 + + ssd1306_print(5, 11, "DOP", 0); + 8004f8a: 2300 movs r3, #0 + 8004f8c: 4a96 ldr r2, [pc, #600] ; (80051e8 ) + 8004f8e: 210b movs r1, #11 + 8004f90: 2005 movs r0, #5 + 8004f92: f004 f9a4 bl 80092de + ftoa32(p_gps_num->pdop, 2, &buf[0]); + 8004f96: 4b92 ldr r3, [pc, #584] ; (80051e0 ) + 8004f98: 681b ldr r3, [r3, #0] + 8004f9a: 6b9b ldr r3, [r3, #56] ; 0x38 + 8004f9c: 4a91 ldr r2, [pc, #580] ; (80051e4 ) + 8004f9e: 2102 movs r1, #2 + 8004fa0: 4618 mov r0, r3 + 8004fa2: f003 fae9 bl 8008578 + ssd1306_print(5, 15, &buf[0], 0); + 8004fa6: 2300 movs r3, #0 + 8004fa8: 4a8e ldr r2, [pc, #568] ; (80051e4 ) + 8004faa: 210f movs r1, #15 + 8004fac: 2005 movs r0, #5 + 8004fae: f004 f996 bl 80092de + + ssd1306_print(6, 0, "SOG", 0); + 8004fb2: 2300 movs r3, #0 + 8004fb4: 4a8d ldr r2, [pc, #564] ; (80051ec ) + 8004fb6: 2100 movs r1, #0 + 8004fb8: 2006 movs r0, #6 + 8004fba: f004 f990 bl 80092de + if (p_gps_num->speed < 10.0) //if speed is small show x.x format + 8004fbe: 4b88 ldr r3, [pc, #544] ; (80051e0 ) + 8004fc0: 681b ldr r3, [r3, #0] + 8004fc2: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004fc4: 498a ldr r1, [pc, #552] ; (80051f0 ) + 8004fc6: 4618 mov r0, r3 + 8004fc8: f7fc f882 bl 80010d0 <__aeabi_fcmplt> + 8004fcc: 4603 mov r3, r0 + 8004fce: 2b00 cmp r3, #0 + 8004fd0: d00e beq.n 8004ff0 + { + ftoa32(p_gps_num->speed, 1, &buf[0]); + 8004fd2: 4b83 ldr r3, [pc, #524] ; (80051e0 ) + 8004fd4: 681b ldr r3, [r3, #0] + 8004fd6: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004fd8: 4a82 ldr r2, [pc, #520] ; (80051e4 ) + 8004fda: 2101 movs r1, #1 + 8004fdc: 4618 mov r0, r3 + 8004fde: f003 facb bl 8008578 + ssd1306_print(6, 4, &buf[0], 0); + 8004fe2: 2300 movs r3, #0 + 8004fe4: 4a7f ldr r2, [pc, #508] ; (80051e4 ) + 8004fe6: 2104 movs r1, #4 + 8004fe8: 2006 movs r0, #6 + 8004fea: f004 f978 bl 80092de + 8004fee: e011 b.n 8005014 + } + else //else show int format + { + itoa32((int16_t)p_gps_num->speed, &buf[0]); + 8004ff0: 4b7b ldr r3, [pc, #492] ; (80051e0 ) + 8004ff2: 681b ldr r3, [r3, #0] + 8004ff4: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004ff6: 4618 mov r0, r3 + 8004ff8: f7fc f892 bl 8001120 <__aeabi_f2iz> + 8004ffc: 4603 mov r3, r0 + 8004ffe: b21b sxth r3, r3 + 8005000: 4978 ldr r1, [pc, #480] ; (80051e4 ) + 8005002: 4618 mov r0, r3 + 8005004: f003 fc08 bl 8008818 + ssd1306_print(6, 4, &buf[0], 0); + 8005008: 2300 movs r3, #0 + 800500a: 4a76 ldr r2, [pc, #472] ; (80051e4 ) + 800500c: 2104 movs r1, #4 + 800500e: 2006 movs r0, #6 + 8005010: f004 f965 bl 80092de + } + ssd1306_print_next("kph", 0); + 8005014: 2100 movs r1, #0 + 8005016: 4877 ldr r0, [pc, #476] ; (80051f4 ) + 8005018: f004 f9c0 bl 800939c + + ssd1306_print(6, 11, "SAT", 0); + 800501c: 2300 movs r3, #0 + 800501e: 4a76 ldr r2, [pc, #472] ; (80051f8 ) + 8005020: 210b movs r1, #11 + 8005022: 2006 movs r0, #6 + 8005024: f004 f95b bl 80092de + itoa32(p_gps_num->sat_used, &buf[0]); + 8005028: 4b6d ldr r3, [pc, #436] ; (80051e0 ) + 800502a: 681b ldr r3, [r3, #0] + 800502c: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 + 8005030: 496c ldr r1, [pc, #432] ; (80051e4 ) + 8005032: 4618 mov r0, r3 + 8005034: f003 fbf0 bl 8008818 + ssd1306_print(6, 15, &buf[0], 0); + 8005038: 2300 movs r3, #0 + 800503a: 4a6a ldr r2, [pc, #424] ; (80051e4 ) + 800503c: 210f movs r1, #15 + 800503e: 2006 movs r0, #6 + 8005040: f004 f94d bl 80092de + ssd1306_print_next("/", 0); + 8005044: 2100 movs r1, #0 + 8005046: 486d ldr r0, [pc, #436] ; (80051fc ) + 8005048: f004 f9a8 bl 800939c + itoa32(p_gps_num->sat_view, &buf[0]); + 800504c: 4b64 ldr r3, [pc, #400] ; (80051e0 ) + 800504e: 681b ldr r3, [r3, #0] + 8005050: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 + 8005054: 4963 ldr r1, [pc, #396] ; (80051e4 ) + 8005056: 4618 mov r0, r3 + 8005058: f003 fbde bl 8008818 + ssd1306_print_next(&buf[0], 0); + 800505c: 2100 movs r1, #0 + 800505e: 4861 ldr r0, [pc, #388] ; (80051e4 ) + 8005060: f004 f99c bl 800939c + + if (pp_dev_aux[device_number]->timeout_flag == 1) + 8005064: 4b66 ldr r3, [pc, #408] ; (8005200 ) + 8005066: 681a ldr r2, [r3, #0] + 8005068: 4b66 ldr r3, [pc, #408] ; (8005204 ) + 800506a: 781b ldrb r3, [r3, #0] + 800506c: 009b lsls r3, r3, #2 + 800506e: 4413 add r3, r2 + 8005070: 681b ldr r3, [r3, #0] + 8005072: 7b1b ldrb r3, [r3, #12] + 8005074: 2b01 cmp r3, #1 + 8005076: d106 bne.n 8005086 + { + ssd1306_print(7, 0, "TOC", 1); + 8005078: 2301 movs r3, #1 + 800507a: 4a63 ldr r2, [pc, #396] ; (8005208 ) + 800507c: 2100 movs r1, #0 + 800507e: 2007 movs r0, #7 + 8005080: f004 f92d bl 80092de + 8005084: e005 b.n 8005092 + } + else + { + ssd1306_print(7, 0, "TOC", 0); + 8005086: 2300 movs r3, #0 + 8005088: 4a5f ldr r2, [pc, #380] ; (8005208 ) + 800508a: 2100 movs r1, #0 + 800508c: 2007 movs r0, #7 + 800508e: f004 f926 bl 80092de + } + convert_timeout(pp_dev_aux[device_number]->timeout, &buf[0]); + 8005092: 4b5b ldr r3, [pc, #364] ; (8005200 ) + 8005094: 681a ldr r2, [r3, #0] + 8005096: 4b5b ldr r3, [pc, #364] ; (8005204 ) + 8005098: 781b ldrb r3, [r3, #0] + 800509a: 009b lsls r3, r3, #2 + 800509c: 4413 add r3, r2 + 800509e: 681b ldr r3, [r3, #0] + 80050a0: 689b ldr r3, [r3, #8] + 80050a2: 4950 ldr r1, [pc, #320] ; (80051e4 ) + 80050a4: 4618 mov r0, r3 + 80050a6: f003 f893 bl 80081d0 + ssd1306_print(7, 4, &buf[0], 0); + 80050aa: 2300 movs r3, #0 + 80050ac: 4a4d ldr r2, [pc, #308] ; (80051e4 ) + 80050ae: 2104 movs r1, #4 + 80050b0: 2007 movs r0, #7 + 80050b2: f004 f914 bl 80092de + + ssd1306_print(7, 11, "BAT", 0); + 80050b6: 2300 movs r3, #0 + 80050b8: 4a54 ldr r2, [pc, #336] ; (800520c ) + 80050ba: 210b movs r1, #11 + 80050bc: 2007 movs r0, #7 + 80050be: f004 f90e bl 80092de + ftoa32(get_bat_voltage(), 2, &buf[0]); + 80050c2: f7fc fa21 bl 8001508 + 80050c6: 4603 mov r3, r0 + 80050c8: 4a46 ldr r2, [pc, #280] ; (80051e4 ) + 80050ca: 2102 movs r1, #2 + 80050cc: 4618 mov r0, r3 + 80050ce: f003 fa53 bl 8008578 + ssd1306_print(7, 15, &buf[0], 0); + 80050d2: 2300 movs r3, #0 + 80050d4: 4a43 ldr r2, [pc, #268] ; (80051e4 ) + 80050d6: 210f movs r1, #15 + 80050d8: 2007 movs r0, #7 + 80050da: f004 f900 bl 80092de + ssd1306_char('V', 0); + 80050de: 2100 movs r1, #0 + 80050e0: 2056 movs r0, #86 ; 0x56 + 80050e2: f004 f899 bl 8009218 + 80050e6: e37a b.n 80057de + } + else //if not me + { + ssd1306_print(0, 1, "#", 0); + 80050e8: 2300 movs r3, #0 + 80050ea: 4a49 ldr r2, [pc, #292] ; (8005210 ) + 80050ec: 2101 movs r1, #1 + 80050ee: 2000 movs r0, #0 + 80050f0: f004 f8f5 bl 80092de + itoa32(current_each_device, &buf[0]); + 80050f4: 4b47 ldr r3, [pc, #284] ; (8005214 ) + 80050f6: 781b ldrb r3, [r3, #0] + 80050f8: 493a ldr r1, [pc, #232] ; (80051e4 ) + 80050fa: 4618 mov r0, r3 + 80050fc: f003 fb8c bl 8008818 + ssd1306_print(0, 2, &buf[0], 0); + 8005100: 2300 movs r3, #0 + 8005102: 4a38 ldr r2, [pc, #224] ; (80051e4 ) + 8005104: 2102 movs r1, #2 + 8005106: 2000 movs r0, #0 + 8005108: f004 f8e9 bl 80092de + + ssd1306_char_pos(0, 4, pp_gps_air[current_each_device]->device_id[0], 0); + 800510c: 4b42 ldr r3, [pc, #264] ; (8005218 ) + 800510e: 681a ldr r2, [r3, #0] + 8005110: 4b40 ldr r3, [pc, #256] ; (8005214 ) + 8005112: 781b ldrb r3, [r3, #0] + 8005114: 009b lsls r3, r3, #2 + 8005116: 4413 add r3, r2 + 8005118: 681b ldr r3, [r3, #0] + 800511a: 781a ldrb r2, [r3, #0] + 800511c: 2300 movs r3, #0 + 800511e: 2104 movs r1, #4 + 8005120: 2000 movs r0, #0 + 8005122: f004 f8bd bl 80092a0 + ssd1306_char_pos(0, 5, pp_gps_air[current_each_device]->device_id[1], 0); + 8005126: 4b3c ldr r3, [pc, #240] ; (8005218 ) + 8005128: 681a ldr r2, [r3, #0] + 800512a: 4b3a ldr r3, [pc, #232] ; (8005214 ) + 800512c: 781b ldrb r3, [r3, #0] + 800512e: 009b lsls r3, r3, #2 + 8005130: 4413 add r3, r2 + 8005132: 681b ldr r3, [r3, #0] + 8005134: 785a ldrb r2, [r3, #1] + 8005136: 2300 movs r3, #0 + 8005138: 2105 movs r1, #5 + 800513a: 2000 movs r0, #0 + 800513c: f004 f8b0 bl 80092a0 + + if (pp_dev_aux[current_each_device]->memory_point_flag == 1) //print memory point name + 8005140: 4b2f ldr r3, [pc, #188] ; (8005200 ) + 8005142: 681a ldr r2, [r3, #0] + 8005144: 4b33 ldr r3, [pc, #204] ; (8005214 ) + 8005146: 781b ldrb r3, [r3, #0] + 8005148: 009b lsls r3, r3, #2 + 800514a: 4413 add r3, r2 + 800514c: 681b ldr r3, [r3, #0] + 800514e: 7b9b ldrb r3, [r3, #14] + 8005150: 2b01 cmp r3, #1 + 8005152: d10d bne.n 8005170 + { + ssd1306_print(0, 7, pp_dev_aux[current_each_device]->point_name, 0); + 8005154: 4b2a ldr r3, [pc, #168] ; (8005200 ) + 8005156: 681a ldr r2, [r3, #0] + 8005158: 4b2e ldr r3, [pc, #184] ; (8005214 ) + 800515a: 781b ldrb r3, [r3, #0] + 800515c: 009b lsls r3, r3, #2 + 800515e: 4413 add r3, r2 + 8005160: 681b ldr r3, [r3, #0] + 8005162: f103 020f add.w r2, r3, #15 + 8005166: 2300 movs r3, #0 + 8005168: 2107 movs r1, #7 + 800516a: 2000 movs r0, #0 + 800516c: f004 f8b7 bl 80092de + } + + ssd1306_print(1, 0, "LAT", 0); + 8005170: 2300 movs r3, #0 + 8005172: 4a2a ldr r2, [pc, #168] ; (800521c ) + 8005174: 2100 movs r1, #0 + 8005176: 2001 movs r0, #1 + 8005178: f004 f8b1 bl 80092de + ftoa32(pp_gps_air[current_each_device]->latitude.as_float, 6, &buf[0]); + 800517c: 4b26 ldr r3, [pc, #152] ; (8005218 ) + 800517e: 681a ldr r2, [r3, #0] + 8005180: 4b24 ldr r3, [pc, #144] ; (8005214 ) + 8005182: 781b ldrb r3, [r3, #0] + 8005184: 009b lsls r3, r3, #2 + 8005186: 4413 add r3, r2 + 8005188: 681b ldr r3, [r3, #0] + 800518a: 685b ldr r3, [r3, #4] + 800518c: 4a15 ldr r2, [pc, #84] ; (80051e4 ) + 800518e: 2106 movs r1, #6 + 8005190: 4618 mov r0, r3 + 8005192: f003 f9f1 bl 8008578 + ssd1306_print_viceversa(1, 14, &buf[0], 0); + 8005196: 2300 movs r3, #0 + 8005198: 4a12 ldr r2, [pc, #72] ; (80051e4 ) + 800519a: 210e movs r1, #14 + 800519c: 2001 movs r0, #1 + 800519e: f004 f8c1 bl 8009324 + if (pp_gps_air[current_each_device]->latitude.as_float >= 0) + 80051a2: 4b1d ldr r3, [pc, #116] ; (8005218 ) + 80051a4: 681a ldr r2, [r3, #0] + 80051a6: 4b1b ldr r3, [pc, #108] ; (8005214 ) + 80051a8: 781b ldrb r3, [r3, #0] + 80051aa: 009b lsls r3, r3, #2 + 80051ac: 4413 add r3, r2 + 80051ae: 681b ldr r3, [r3, #0] + 80051b0: 685b ldr r3, [r3, #4] + 80051b2: f04f 0100 mov.w r1, #0 + 80051b6: 4618 mov r0, r3 + 80051b8: f7fb ff9e bl 80010f8 <__aeabi_fcmpge> + 80051bc: 4603 mov r3, r0 + 80051be: 2b00 cmp r3, #0 + 80051c0: d030 beq.n 8005224 + { + ssd1306_char('+', 0); + 80051c2: 2100 movs r1, #0 + 80051c4: 202b movs r0, #43 ; 0x2b + 80051c6: f004 f827 bl 8009218 + ssd1306_print(1, 16, "(N)", 0); + 80051ca: 2300 movs r3, #0 + 80051cc: 4a14 ldr r2, [pc, #80] ; (8005220 ) + 80051ce: 2110 movs r1, #16 + 80051d0: 2001 movs r0, #1 + 80051d2: f004 f884 bl 80092de + 80051d6: e02b b.n 8005230 + 80051d8: 0800ca68 .word 0x0800ca68 + 80051dc: 0800ca6c .word 0x0800ca6c + 80051e0: 20000614 .word 0x20000614 + 80051e4: 20000810 .word 0x20000810 + 80051e8: 0800ca70 .word 0x0800ca70 + 80051ec: 0800ca74 .word 0x0800ca74 + 80051f0: 41200000 .word 0x41200000 + 80051f4: 0800ca78 .word 0x0800ca78 + 80051f8: 0800ca7c .word 0x0800ca7c + 80051fc: 0800ca80 .word 0x0800ca80 + 8005200: 2000083c .word 0x2000083c + 8005204: 20000738 .word 0x20000738 + 8005208: 0800ca84 .word 0x0800ca84 + 800520c: 0800ca88 .word 0x0800ca88 + 8005210: 0800ca1c .word 0x0800ca1c + 8005214: 20000032 .word 0x20000032 + 8005218: 20000804 .word 0x20000804 + 800521c: 0800ca34 .word 0x0800ca34 + 8005220: 0800ca38 .word 0x0800ca38 + } + else + { + ssd1306_print(1, 16, "(S)", 0); + 8005224: 2300 movs r3, #0 + 8005226: 4ab5 ldr r2, [pc, #724] ; (80054fc ) + 8005228: 2110 movs r1, #16 + 800522a: 2001 movs r0, #1 + 800522c: f004 f857 bl 80092de + } + + ssd1306_print(2, 0, "LON", 0); + 8005230: 2300 movs r3, #0 + 8005232: 4ab3 ldr r2, [pc, #716] ; (8005500 ) + 8005234: 2100 movs r1, #0 + 8005236: 2002 movs r0, #2 + 8005238: f004 f851 bl 80092de + ftoa32(pp_gps_air[current_each_device]->longitude.as_float, 6, &buf[0]); + 800523c: 4bb1 ldr r3, [pc, #708] ; (8005504 ) + 800523e: 681a ldr r2, [r3, #0] + 8005240: 4bb1 ldr r3, [pc, #708] ; (8005508 ) + 8005242: 781b ldrb r3, [r3, #0] + 8005244: 009b lsls r3, r3, #2 + 8005246: 4413 add r3, r2 + 8005248: 681b ldr r3, [r3, #0] + 800524a: 689b ldr r3, [r3, #8] + 800524c: 4aaf ldr r2, [pc, #700] ; (800550c ) + 800524e: 2106 movs r1, #6 + 8005250: 4618 mov r0, r3 + 8005252: f003 f991 bl 8008578 + ssd1306_print_viceversa(2, 14, &buf[0], 0); + 8005256: 2300 movs r3, #0 + 8005258: 4aac ldr r2, [pc, #688] ; (800550c ) + 800525a: 210e movs r1, #14 + 800525c: 2002 movs r0, #2 + 800525e: f004 f861 bl 8009324 + if (pp_gps_air[current_each_device]->longitude.as_float >= 0) + 8005262: 4ba8 ldr r3, [pc, #672] ; (8005504 ) + 8005264: 681a ldr r2, [r3, #0] + 8005266: 4ba8 ldr r3, [pc, #672] ; (8005508 ) + 8005268: 781b ldrb r3, [r3, #0] + 800526a: 009b lsls r3, r3, #2 + 800526c: 4413 add r3, r2 + 800526e: 681b ldr r3, [r3, #0] + 8005270: 689b ldr r3, [r3, #8] + 8005272: f04f 0100 mov.w r1, #0 + 8005276: 4618 mov r0, r3 + 8005278: f7fb ff3e bl 80010f8 <__aeabi_fcmpge> + 800527c: 4603 mov r3, r0 + 800527e: 2b00 cmp r3, #0 + 8005280: d00a beq.n 8005298 + { + ssd1306_char('+', 0); + 8005282: 2100 movs r1, #0 + 8005284: 202b movs r0, #43 ; 0x2b + 8005286: f003 ffc7 bl 8009218 + ssd1306_print(2, 16, "(E)", 0); + 800528a: 2300 movs r3, #0 + 800528c: 4aa0 ldr r2, [pc, #640] ; (8005510 ) + 800528e: 2110 movs r1, #16 + 8005290: 2002 movs r0, #2 + 8005292: f004 f824 bl 80092de + 8005296: e005 b.n 80052a4 + } + else + { + ssd1306_print(2, 16, "(W)", 0); + 8005298: 2300 movs r3, #0 + 800529a: 4a9e ldr r2, [pc, #632] ; (8005514 ) + 800529c: 2110 movs r1, #16 + 800529e: 2002 movs r0, #2 + 80052a0: f004 f81d bl 80092de + } + + ssd1306_print(3, 0, "ALT", 0); + 80052a4: 2300 movs r3, #0 + 80052a6: 4a9c ldr r2, [pc, #624] ; (8005518 ) + 80052a8: 2100 movs r1, #0 + 80052aa: 2003 movs r0, #3 + 80052ac: f004 f817 bl 80092de + itoa32(pp_gps_air[current_each_device]->altitude.as_integer, &buf[0]); + 80052b0: 4b94 ldr r3, [pc, #592] ; (8005504 ) + 80052b2: 681a ldr r2, [r3, #0] + 80052b4: 4b94 ldr r3, [pc, #592] ; (8005508 ) + 80052b6: 781b ldrb r3, [r3, #0] + 80052b8: 009b lsls r3, r3, #2 + 80052ba: 4413 add r3, r2 + 80052bc: 681b ldr r3, [r3, #0] + 80052be: f9b3 300c ldrsh.w r3, [r3, #12] + 80052c2: 4992 ldr r1, [pc, #584] ; (800550c ) + 80052c4: 4618 mov r0, r3 + 80052c6: f003 faa7 bl 8008818 + ssd1306_print(3, 4, &buf[0], 0); + 80052ca: 2300 movs r3, #0 + 80052cc: 4a8f ldr r2, [pc, #572] ; (800550c ) + 80052ce: 2104 movs r1, #4 + 80052d0: 2003 movs r0, #3 + 80052d2: f004 f804 bl 80092de + ssd1306_print_next("m", 0); + 80052d6: 2100 movs r1, #0 + 80052d8: 4890 ldr r0, [pc, #576] ; (800551c ) + 80052da: f004 f85f bl 800939c + + + ssd1306_print(3, 11, "DLT", 0); + 80052de: 2300 movs r3, #0 + 80052e0: 4a8f ldr r2, [pc, #572] ; (8005520 ) + 80052e2: 210b movs r1, #11 + 80052e4: 2003 movs r0, #3 + 80052e6: f003 fffa bl 80092de + tmpi16 = pp_gps_rel[current_each_device]->altitude_diff; + 80052ea: 4b8e ldr r3, [pc, #568] ; (8005524 ) + 80052ec: 681a ldr r2, [r3, #0] + 80052ee: 4b86 ldr r3, [pc, #536] ; (8005508 ) + 80052f0: 781b ldrb r3, [r3, #0] + 80052f2: 009b lsls r3, r3, #2 + 80052f4: 4413 add r3, r2 + 80052f6: 681b ldr r3, [r3, #0] + 80052f8: f9b3 2006 ldrsh.w r2, [r3, #6] + 80052fc: 4b8a ldr r3, [pc, #552] ; (8005528 ) + 80052fe: 801a strh r2, [r3, #0] + + if (tmpi16 < 0) + 8005300: 4b89 ldr r3, [pc, #548] ; (8005528 ) + 8005302: f9b3 3000 ldrsh.w r3, [r3] + 8005306: 2b00 cmp r3, #0 + 8005308: da0f bge.n 800532a + { + tmpi16 *= -1; + 800530a: 4b87 ldr r3, [pc, #540] ; (8005528 ) + 800530c: f9b3 3000 ldrsh.w r3, [r3] + 8005310: b29b uxth r3, r3 + 8005312: 425b negs r3, r3 + 8005314: b29b uxth r3, r3 + 8005316: b21a sxth r2, r3 + 8005318: 4b83 ldr r3, [pc, #524] ; (8005528 ) + 800531a: 801a strh r2, [r3, #0] + ssd1306_char_pos(3, 14, ' ', 0); + 800531c: 2300 movs r3, #0 + 800531e: 2220 movs r2, #32 + 8005320: 210e movs r1, #14 + 8005322: 2003 movs r0, #3 + 8005324: f003 ffbc bl 80092a0 + 8005328: e011 b.n 800534e + } + else if (tmpi16 > 0) + 800532a: 4b7f ldr r3, [pc, #508] ; (8005528 ) + 800532c: f9b3 3000 ldrsh.w r3, [r3] + 8005330: 2b00 cmp r3, #0 + 8005332: dd06 ble.n 8005342 + { + ssd1306_char_pos(3, 15, '+', 0); + 8005334: 2300 movs r3, #0 + 8005336: 222b movs r2, #43 ; 0x2b + 8005338: 210f movs r1, #15 + 800533a: 2003 movs r0, #3 + 800533c: f003 ffb0 bl 80092a0 + 8005340: e005 b.n 800534e + } + else + { + ssd1306_char_pos(3, 14, ' ', 0); + 8005342: 2300 movs r3, #0 + 8005344: 2220 movs r2, #32 + 8005346: 210e movs r1, #14 + 8005348: 2003 movs r0, #3 + 800534a: f003 ffa9 bl 80092a0 + } + + if (tmpi16 < 10000) //0-9999 m + 800534e: 4b76 ldr r3, [pc, #472] ; (8005528 ) + 8005350: f9b3 3000 ldrsh.w r3, [r3] + 8005354: f242 720f movw r2, #9999 ; 0x270f + 8005358: 4293 cmp r3, r2 + 800535a: dc15 bgt.n 8005388 + { + itoa32(pp_gps_rel[current_each_device]->altitude_diff, &buf[0]); + 800535c: 4b71 ldr r3, [pc, #452] ; (8005524 ) + 800535e: 681a ldr r2, [r3, #0] + 8005360: 4b69 ldr r3, [pc, #420] ; (8005508 ) + 8005362: 781b ldrb r3, [r3, #0] + 8005364: 009b lsls r3, r3, #2 + 8005366: 4413 add r3, r2 + 8005368: 681b ldr r3, [r3, #0] + 800536a: f9b3 3006 ldrsh.w r3, [r3, #6] + 800536e: 4967 ldr r1, [pc, #412] ; (800550c ) + 8005370: 4618 mov r0, r3 + 8005372: f003 fa51 bl 8008818 + ssd1306_print_next(&buf[0], 0); + 8005376: 2100 movs r1, #0 + 8005378: 4864 ldr r0, [pc, #400] ; (800550c ) + 800537a: f004 f80f bl 800939c + ssd1306_print_next("m", 0); + 800537e: 2100 movs r1, #0 + 8005380: 4866 ldr r0, [pc, #408] ; (800551c ) + 8005382: f004 f80b bl 800939c + 8005386: e028 b.n 80053da + } + else // >=10000 km + { + tmpf = pp_gps_rel[current_each_device]->altitude_diff / 1000.0; + 8005388: 4b66 ldr r3, [pc, #408] ; (8005524 ) + 800538a: 681a ldr r2, [r3, #0] + 800538c: 4b5e ldr r3, [pc, #376] ; (8005508 ) + 800538e: 781b ldrb r3, [r3, #0] + 8005390: 009b lsls r3, r3, #2 + 8005392: 4413 add r3, r2 + 8005394: 681b ldr r3, [r3, #0] + 8005396: f9b3 3006 ldrsh.w r3, [r3, #6] + 800539a: 4618 mov r0, r3 + 800539c: f7fb f83a bl 8000414 <__aeabi_i2d> + 80053a0: f04f 0200 mov.w r2, #0 + 80053a4: 4b61 ldr r3, [pc, #388] ; (800552c ) + 80053a6: f7fb f9c9 bl 800073c <__aeabi_ddiv> + 80053aa: 4603 mov r3, r0 + 80053ac: 460c mov r4, r1 + 80053ae: 4618 mov r0, r3 + 80053b0: 4621 mov r1, r4 + 80053b2: f7fb fb91 bl 8000ad8 <__aeabi_d2f> + 80053b6: 4602 mov r2, r0 + 80053b8: 4b5d ldr r3, [pc, #372] ; (8005530 ) + 80053ba: 601a str r2, [r3, #0] + ftoa32(tmpf, 1, &buf[0]); + 80053bc: 4b5c ldr r3, [pc, #368] ; (8005530 ) + 80053be: 681b ldr r3, [r3, #0] + 80053c0: 4a52 ldr r2, [pc, #328] ; (800550c ) + 80053c2: 2101 movs r1, #1 + 80053c4: 4618 mov r0, r3 + 80053c6: f003 f8d7 bl 8008578 + ssd1306_print_next(&buf[0], 0); + 80053ca: 2100 movs r1, #0 + 80053cc: 484f ldr r0, [pc, #316] ; (800550c ) + 80053ce: f003 ffe5 bl 800939c + ssd1306_print_next("k", 0); + 80053d2: 2100 movs r1, #0 + 80053d4: 4857 ldr r0, [pc, #348] ; (8005534 ) + 80053d6: f003 ffe1 bl 800939c + } + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + 80053da: 4b57 ldr r3, [pc, #348] ; (8005538 ) + 80053dc: 681a ldr r2, [r3, #0] + 80053de: 4b4a ldr r3, [pc, #296] ; (8005508 ) + 80053e0: 781b ldrb r3, [r3, #0] + 80053e2: 009b lsls r3, r3, #2 + 80053e4: 4413 add r3, r2 + 80053e6: 681b ldr r3, [r3, #0] + 80053e8: 7b9b ldrb r3, [r3, #14] + 80053ea: 2b00 cmp r3, #0 + 80053ec: d11b bne.n 8005426 + { + ssd1306_print(4, 0, "COG", 0); + 80053ee: 2300 movs r3, #0 + 80053f0: 4a52 ldr r2, [pc, #328] ; (800553c ) + 80053f2: 2100 movs r1, #0 + 80053f4: 2004 movs r0, #4 + 80053f6: f003 ff72 bl 80092de + itoa32(pp_gps_air[current_each_device]->course.as_integer, &buf[0]); + 80053fa: 4b42 ldr r3, [pc, #264] ; (8005504 ) + 80053fc: 681a ldr r2, [r3, #0] + 80053fe: 4b42 ldr r3, [pc, #264] ; (8005508 ) + 8005400: 781b ldrb r3, [r3, #0] + 8005402: 009b lsls r3, r3, #2 + 8005404: 4413 add r3, r2 + 8005406: 681b ldr r3, [r3, #0] + 8005408: 8a1b ldrh r3, [r3, #16] + 800540a: 4940 ldr r1, [pc, #256] ; (800550c ) + 800540c: 4618 mov r0, r3 + 800540e: f003 fa03 bl 8008818 + ssd1306_print(4, 4, &buf[0], 0); + 8005412: 2300 movs r3, #0 + 8005414: 4a3d ldr r2, [pc, #244] ; (800550c ) + 8005416: 2104 movs r1, #4 + 8005418: 2004 movs r0, #4 + 800541a: f003 ff60 bl 80092de + ssd1306_char(SYMB_DEGREE, 0); + 800541e: 2100 movs r1, #0 + 8005420: 208d movs r0, #141 ; 0x8d + 8005422: f003 fef9 bl 8009218 + } + + ssd1306_print(4, 11, "BRG", 0); + 8005426: 2300 movs r3, #0 + 8005428: 4a45 ldr r2, [pc, #276] ; (8005540 ) + 800542a: 210b movs r1, #11 + 800542c: 2004 movs r0, #4 + 800542e: f003 ff56 bl 80092de + itoa32(pp_gps_rel[current_each_device]->heading, &buf[0]); + 8005432: 4b3c ldr r3, [pc, #240] ; (8005524 ) + 8005434: 681a ldr r2, [r3, #0] + 8005436: 4b34 ldr r3, [pc, #208] ; (8005508 ) + 8005438: 781b ldrb r3, [r3, #0] + 800543a: 009b lsls r3, r3, #2 + 800543c: 4413 add r3, r2 + 800543e: 681b ldr r3, [r3, #0] + 8005440: 889b ldrh r3, [r3, #4] + 8005442: 4932 ldr r1, [pc, #200] ; (800550c ) + 8005444: 4618 mov r0, r3 + 8005446: f003 f9e7 bl 8008818 + ssd1306_print(4, 15, &buf[0], 0); + 800544a: 2300 movs r3, #0 + 800544c: 4a2f ldr r2, [pc, #188] ; (800550c ) + 800544e: 210f movs r1, #15 + 8005450: 2004 movs r0, #4 + 8005452: f003 ff44 bl 80092de + ssd1306_char(SYMB_DEGREE, 0); + 8005456: 2100 movs r1, #0 + 8005458: 208d movs r0, #141 ; 0x8d + 800545a: f003 fedd bl 8009218 + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + 800545e: 4b36 ldr r3, [pc, #216] ; (8005538 ) + 8005460: 681a ldr r2, [r3, #0] + 8005462: 4b29 ldr r3, [pc, #164] ; (8005508 ) + 8005464: 781b ldrb r3, [r3, #0] + 8005466: 009b lsls r3, r3, #2 + 8005468: 4413 add r3, r2 + 800546a: 681b ldr r3, [r3, #0] + 800546c: 7b9b ldrb r3, [r3, #14] + 800546e: 2b00 cmp r3, #0 + 8005470: d11b bne.n 80054aa + { + ssd1306_print(5, 0, "SOG", 0); + 8005472: 2300 movs r3, #0 + 8005474: 4a33 ldr r2, [pc, #204] ; (8005544 ) + 8005476: 2100 movs r1, #0 + 8005478: 2005 movs r0, #5 + 800547a: f003 ff30 bl 80092de + itoa32(pp_gps_air[current_each_device]->speed, &buf[0]); + 800547e: 4b21 ldr r3, [pc, #132] ; (8005504 ) + 8005480: 681a ldr r2, [r3, #0] + 8005482: 4b21 ldr r3, [pc, #132] ; (8005508 ) + 8005484: 781b ldrb r3, [r3, #0] + 8005486: 009b lsls r3, r3, #2 + 8005488: 4413 add r3, r2 + 800548a: 681b ldr r3, [r3, #0] + 800548c: 7b9b ldrb r3, [r3, #14] + 800548e: 491f ldr r1, [pc, #124] ; (800550c ) + 8005490: 4618 mov r0, r3 + 8005492: f003 f9c1 bl 8008818 + ssd1306_print(5, 4, &buf[0], 0); + 8005496: 2300 movs r3, #0 + 8005498: 4a1c ldr r2, [pc, #112] ; (800550c ) + 800549a: 2104 movs r1, #4 + 800549c: 2005 movs r0, #5 + 800549e: f003 ff1e bl 80092de + ssd1306_print_next("kph", 0); + 80054a2: 2100 movs r1, #0 + 80054a4: 4828 ldr r0, [pc, #160] ; (8005548 ) + 80054a6: f003 ff79 bl 800939c + } + + + ssd1306_print(5, 11, "DST", 0); + 80054aa: 2300 movs r3, #0 + 80054ac: 4a27 ldr r2, [pc, #156] ; (800554c ) + 80054ae: 210b movs r1, #11 + 80054b0: 2005 movs r0, #5 + 80054b2: f003 ff14 bl 80092de + + if (pp_gps_rel[current_each_device]->distance < 100000) // 0-99999 m + 80054b6: 4b1b ldr r3, [pc, #108] ; (8005524 ) + 80054b8: 681a ldr r2, [r3, #0] + 80054ba: 4b13 ldr r3, [pc, #76] ; (8005508 ) + 80054bc: 781b ldrb r3, [r3, #0] + 80054be: 009b lsls r3, r3, #2 + 80054c0: 4413 add r3, r2 + 80054c2: 681b ldr r3, [r3, #0] + 80054c4: 681b ldr r3, [r3, #0] + 80054c6: 4a22 ldr r2, [pc, #136] ; (8005550 ) + 80054c8: 4293 cmp r3, r2 + 80054ca: d843 bhi.n 8005554 + { + itoa32(pp_gps_rel[current_each_device]->distance, &buf[0]); + 80054cc: 4b15 ldr r3, [pc, #84] ; (8005524 ) + 80054ce: 681a ldr r2, [r3, #0] + 80054d0: 4b0d ldr r3, [pc, #52] ; (8005508 ) + 80054d2: 781b ldrb r3, [r3, #0] + 80054d4: 009b lsls r3, r3, #2 + 80054d6: 4413 add r3, r2 + 80054d8: 681b ldr r3, [r3, #0] + 80054da: 681b ldr r3, [r3, #0] + 80054dc: 490b ldr r1, [pc, #44] ; (800550c ) + 80054de: 4618 mov r0, r3 + 80054e0: f003 f99a bl 8008818 + ssd1306_print(5, 15, &buf[0], 0); + 80054e4: 2300 movs r3, #0 + 80054e6: 4a09 ldr r2, [pc, #36] ; (800550c ) + 80054e8: 210f movs r1, #15 + 80054ea: 2005 movs r0, #5 + 80054ec: f003 fef7 bl 80092de + ssd1306_print_next("m", 0); + 80054f0: 2100 movs r1, #0 + 80054f2: 480a ldr r0, [pc, #40] ; (800551c ) + 80054f4: f003 ff52 bl 800939c + 80054f8: e08c b.n 8005614 + 80054fa: bf00 nop + 80054fc: 0800ca3c .word 0x0800ca3c + 8005500: 0800ca40 .word 0x0800ca40 + 8005504: 20000804 .word 0x20000804 + 8005508: 20000032 .word 0x20000032 + 800550c: 20000810 .word 0x20000810 + 8005510: 0800ca44 .word 0x0800ca44 + 8005514: 0800ca48 .word 0x0800ca48 + 8005518: 0800ca4c .word 0x0800ca4c + 800551c: 0800ca50 .word 0x0800ca50 + 8005520: 0800ca8c .word 0x0800ca8c + 8005524: 200007d0 .word 0x200007d0 + 8005528: 200007f8 .word 0x200007f8 + 800552c: 408f4000 .word 0x408f4000 + 8005530: 200007f4 .word 0x200007f4 + 8005534: 0800ca90 .word 0x0800ca90 + 8005538: 2000083c .word 0x2000083c + 800553c: 0800ca6c .word 0x0800ca6c + 8005540: 0800ca94 .word 0x0800ca94 + 8005544: 0800ca74 .word 0x0800ca74 + 8005548: 0800ca78 .word 0x0800ca78 + 800554c: 0800ca98 .word 0x0800ca98 + 8005550: 0001869f .word 0x0001869f + } + else if (pp_gps_rel[current_each_device]->distance < 1000000) // 100-999.9 km + 8005554: 4ba8 ldr r3, [pc, #672] ; (80057f8 ) + 8005556: 681a ldr r2, [r3, #0] + 8005558: 4ba8 ldr r3, [pc, #672] ; (80057fc ) + 800555a: 781b ldrb r3, [r3, #0] + 800555c: 009b lsls r3, r3, #2 + 800555e: 4413 add r3, r2 + 8005560: 681b ldr r3, [r3, #0] + 8005562: 681b ldr r3, [r3, #0] + 8005564: 4aa6 ldr r2, [pc, #664] ; (8005800 ) + 8005566: 4293 cmp r3, r2 + 8005568: d82a bhi.n 80055c0 + { + tmpf = pp_gps_rel[current_each_device]->distance / 1000.0; + 800556a: 4ba3 ldr r3, [pc, #652] ; (80057f8 ) + 800556c: 681a ldr r2, [r3, #0] + 800556e: 4ba3 ldr r3, [pc, #652] ; (80057fc ) + 8005570: 781b ldrb r3, [r3, #0] + 8005572: 009b lsls r3, r3, #2 + 8005574: 4413 add r3, r2 + 8005576: 681b ldr r3, [r3, #0] + 8005578: 681b ldr r3, [r3, #0] + 800557a: 4618 mov r0, r3 + 800557c: f7fa ff3a bl 80003f4 <__aeabi_ui2d> + 8005580: f04f 0200 mov.w r2, #0 + 8005584: 4b9f ldr r3, [pc, #636] ; (8005804 ) + 8005586: f7fb f8d9 bl 800073c <__aeabi_ddiv> + 800558a: 4603 mov r3, r0 + 800558c: 460c mov r4, r1 + 800558e: 4618 mov r0, r3 + 8005590: 4621 mov r1, r4 + 8005592: f7fb faa1 bl 8000ad8 <__aeabi_d2f> + 8005596: 4602 mov r2, r0 + 8005598: 4b9b ldr r3, [pc, #620] ; (8005808 ) + 800559a: 601a str r2, [r3, #0] + ftoa32(tmpf, 1, &buf[0]); + 800559c: 4b9a ldr r3, [pc, #616] ; (8005808 ) + 800559e: 681b ldr r3, [r3, #0] + 80055a0: 4a9a ldr r2, [pc, #616] ; (800580c ) + 80055a2: 2101 movs r1, #1 + 80055a4: 4618 mov r0, r3 + 80055a6: f002 ffe7 bl 8008578 + ssd1306_print(5, 15, &buf[0], 0); + 80055aa: 2300 movs r3, #0 + 80055ac: 4a97 ldr r2, [pc, #604] ; (800580c ) + 80055ae: 210f movs r1, #15 + 80055b0: 2005 movs r0, #5 + 80055b2: f003 fe94 bl 80092de + ssd1306_print_next("k", 0); + 80055b6: 2100 movs r1, #0 + 80055b8: 4895 ldr r0, [pc, #596] ; (8005810 ) + 80055ba: f003 feef bl 800939c + 80055be: e029 b.n 8005614 + } + else // 1000-... km + { + tmpf = pp_gps_rel[current_each_device]->distance / 1000000.0; + 80055c0: 4b8d ldr r3, [pc, #564] ; (80057f8 ) + 80055c2: 681a ldr r2, [r3, #0] + 80055c4: 4b8d ldr r3, [pc, #564] ; (80057fc ) + 80055c6: 781b ldrb r3, [r3, #0] + 80055c8: 009b lsls r3, r3, #2 + 80055ca: 4413 add r3, r2 + 80055cc: 681b ldr r3, [r3, #0] + 80055ce: 681b ldr r3, [r3, #0] + 80055d0: 4618 mov r0, r3 + 80055d2: f7fa ff0f bl 80003f4 <__aeabi_ui2d> + 80055d6: a386 add r3, pc, #536 ; (adr r3, 80057f0 ) + 80055d8: e9d3 2300 ldrd r2, r3, [r3] + 80055dc: f7fb f8ae bl 800073c <__aeabi_ddiv> + 80055e0: 4603 mov r3, r0 + 80055e2: 460c mov r4, r1 + 80055e4: 4618 mov r0, r3 + 80055e6: 4621 mov r1, r4 + 80055e8: f7fb fa76 bl 8000ad8 <__aeabi_d2f> + 80055ec: 4602 mov r2, r0 + 80055ee: 4b86 ldr r3, [pc, #536] ; (8005808 ) + 80055f0: 601a str r2, [r3, #0] + ftoa32(tmpf, 1, &buf[0]); + 80055f2: 4b85 ldr r3, [pc, #532] ; (8005808 ) + 80055f4: 681b ldr r3, [r3, #0] + 80055f6: 4a85 ldr r2, [pc, #532] ; (800580c ) + 80055f8: 2101 movs r1, #1 + 80055fa: 4618 mov r0, r3 + 80055fc: f002 ffbc bl 8008578 + ssd1306_print(5, 15, &buf[0], 0); + 8005600: 2300 movs r3, #0 + 8005602: 4a82 ldr r2, [pc, #520] ; (800580c ) + 8005604: 210f movs r1, #15 + 8005606: 2005 movs r0, #5 + 8005608: f003 fe69 bl 80092de + ssd1306_print_next("M", 0); + 800560c: 2100 movs r1, #0 + 800560e: 4881 ldr r0, [pc, #516] ; (8005814 ) + 8005610: f003 fec4 bl 800939c + } + + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + 8005614: 4b80 ldr r3, [pc, #512] ; (8005818 ) + 8005616: 681a ldr r2, [r3, #0] + 8005618: 4b78 ldr r3, [pc, #480] ; (80057fc ) + 800561a: 781b ldrb r3, [r3, #0] + 800561c: 009b lsls r3, r3, #2 + 800561e: 4413 add r3, r2 + 8005620: 681b ldr r3, [r3, #0] + 8005622: 7b9b ldrb r3, [r3, #14] + 8005624: 2b00 cmp r3, #0 + 8005626: d131 bne.n 800568c + { + ssd1306_print(6, 0, "FIX", 0); + 8005628: 2300 movs r3, #0 + 800562a: 4a7c ldr r2, [pc, #496] ; (800581c ) + 800562c: 2100 movs r1, #0 + 800562e: 2006 movs r0, #6 + 8005630: f003 fe55 bl 80092de + if (get_device_flags(current_each_device, FLAGS_GPS_FIX) == FLAG_GPS_FIX_3D) + 8005634: 4b71 ldr r3, [pc, #452] ; (80057fc ) + 8005636: 781b ldrb r3, [r3, #0] + 8005638: 2102 movs r1, #2 + 800563a: 4618 mov r0, r3 + 800563c: f7fd f93e bl 80028bc + 8005640: 4603 mov r3, r0 + 8005642: 2b01 cmp r3, #1 + 8005644: d106 bne.n 8005654 + { + ssd1306_print(6, 4, "3D/", 0); + 8005646: 2300 movs r3, #0 + 8005648: 4a75 ldr r2, [pc, #468] ; (8005820 ) + 800564a: 2104 movs r1, #4 + 800564c: 2006 movs r0, #6 + 800564e: f003 fe46 bl 80092de + 8005652: e005 b.n 8005660 + } + else + { + ssd1306_print(6, 4, "2D/", 0); + 8005654: 2300 movs r3, #0 + 8005656: 4a73 ldr r2, [pc, #460] ; (8005824 ) + 8005658: 2104 movs r1, #4 + 800565a: 2006 movs r0, #6 + 800565c: f003 fe3f bl 80092de + } + + if (get_device_flags(current_each_device, FLAGS_PDOP) == FLAG_PDOP_GOOD) + 8005660: 4b66 ldr r3, [pc, #408] ; (80057fc ) + 8005662: 781b ldrb r3, [r3, #0] + 8005664: 2103 movs r1, #3 + 8005666: 4618 mov r0, r3 + 8005668: f7fd f928 bl 80028bc + 800566c: 4603 mov r3, r0 + 800566e: 2b01 cmp r3, #1 + 8005670: d106 bne.n 8005680 + { + ssd1306_print(6, 7, "HI", 0); + 8005672: 2300 movs r3, #0 + 8005674: 4a6c ldr r2, [pc, #432] ; (8005828 ) + 8005676: 2107 movs r1, #7 + 8005678: 2006 movs r0, #6 + 800567a: f003 fe30 bl 80092de + 800567e: e005 b.n 800568c + } + else + { + ssd1306_print(6, 7, "LO", 0); + 8005680: 2300 movs r3, #0 + 8005682: 4a6a ldr r2, [pc, #424] ; (800582c ) + 8005684: 2107 movs r1, #7 + 8005686: 2006 movs r0, #6 + 8005688: f003 fe29 bl 80092de + } + } + + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + 800568c: 4b62 ldr r3, [pc, #392] ; (8005818 ) + 800568e: 681a ldr r2, [r3, #0] + 8005690: 4b5a ldr r3, [pc, #360] ; (80057fc ) + 8005692: 781b ldrb r3, [r3, #0] + 8005694: 009b lsls r3, r3, #2 + 8005696: 4413 add r3, r2 + 8005698: 681b ldr r3, [r3, #0] + 800569a: 7b9b ldrb r3, [r3, #14] + 800569c: 2b00 cmp r3, #0 + 800569e: d13e bne.n 800571e + { + ssd1306_print(6, 11, "BAT", 0); + 80056a0: 2300 movs r3, #0 + 80056a2: 4a63 ldr r2, [pc, #396] ; (8005830 ) + 80056a4: 210b movs r1, #11 + 80056a6: 2006 movs r0, #6 + 80056a8: f003 fe19 bl 80092de + switch (get_device_flags(current_each_device, FLAGS_BATTERY)) + 80056ac: 4b53 ldr r3, [pc, #332] ; (80057fc ) + 80056ae: 781b ldrb r3, [r3, #0] + 80056b0: 2101 movs r1, #1 + 80056b2: 4618 mov r0, r3 + 80056b4: f7fd f902 bl 80028bc + 80056b8: 4603 mov r3, r0 + 80056ba: 2b04 cmp r3, #4 + 80056bc: d82f bhi.n 800571e + 80056be: a201 add r2, pc, #4 ; (adr r2, 80056c4 ) + 80056c0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80056c4: 08005711 .word 0x08005711 + 80056c8: 08005703 .word 0x08005703 + 80056cc: 080056f5 .word 0x080056f5 + 80056d0: 080056e7 .word 0x080056e7 + 80056d4: 080056d9 .word 0x080056d9 + { + case FLAG_BATTERY_75_TO_100: + ssd1306_print(6, 15, "4/4", 0); + 80056d8: 2300 movs r3, #0 + 80056da: 4a56 ldr r2, [pc, #344] ; (8005834 ) + 80056dc: 210f movs r1, #15 + 80056de: 2006 movs r0, #6 + 80056e0: f003 fdfd bl 80092de + break; + 80056e4: e01b b.n 800571e + + case FLAG_BATTERY_50_TO_75: + ssd1306_print(6, 15, "3/4", 0); + 80056e6: 2300 movs r3, #0 + 80056e8: 4a53 ldr r2, [pc, #332] ; (8005838 ) + 80056ea: 210f movs r1, #15 + 80056ec: 2006 movs r0, #6 + 80056ee: f003 fdf6 bl 80092de + break; + 80056f2: e014 b.n 800571e + + case FLAG_BATTERY_25_TO_50: + ssd1306_print(6, 15, "2/4", 0); + 80056f4: 2300 movs r3, #0 + 80056f6: 4a51 ldr r2, [pc, #324] ; (800583c ) + 80056f8: 210f movs r1, #15 + 80056fa: 2006 movs r0, #6 + 80056fc: f003 fdef bl 80092de + break; + 8005700: e00d b.n 800571e + + case FLAG_BATTERY_10_TO_25: + ssd1306_print(6, 15, "1/4", 0); + 8005702: 2300 movs r3, #0 + 8005704: 4a4e ldr r2, [pc, #312] ; (8005840 ) + 8005706: 210f movs r1, #15 + 8005708: 2006 movs r0, #6 + 800570a: f003 fde8 bl 80092de + break; + 800570e: e006 b.n 800571e + + case FLAG_BATTERY_0_TO_10: + ssd1306_print(6, 15, "0/4", 0); + 8005710: 2300 movs r3, #0 + 8005712: 4a4c ldr r2, [pc, #304] ; (8005844 ) + 8005714: 210f movs r1, #15 + 8005716: 2006 movs r0, #6 + 8005718: f003 fde1 bl 80092de + break; + 800571c: bf00 nop + } + } + + if (pp_dev_aux[current_each_device]->timeout_flag == 1) + 800571e: 4b3e ldr r3, [pc, #248] ; (8005818 ) + 8005720: 681a ldr r2, [r3, #0] + 8005722: 4b36 ldr r3, [pc, #216] ; (80057fc ) + 8005724: 781b ldrb r3, [r3, #0] + 8005726: 009b lsls r3, r3, #2 + 8005728: 4413 add r3, r2 + 800572a: 681b ldr r3, [r3, #0] + 800572c: 7b1b ldrb r3, [r3, #12] + 800572e: 2b01 cmp r3, #1 + 8005730: d106 bne.n 8005740 + { + ssd1306_print(7, 0, "TOC", 1); + 8005732: 2301 movs r3, #1 + 8005734: 4a44 ldr r2, [pc, #272] ; (8005848 ) + 8005736: 2100 movs r1, #0 + 8005738: 2007 movs r0, #7 + 800573a: f003 fdd0 bl 80092de + 800573e: e005 b.n 800574c + } + else + { + ssd1306_print(7, 0, "TOC", 0); + 8005740: 2300 movs r3, #0 + 8005742: 4a41 ldr r2, [pc, #260] ; (8005848 ) + 8005744: 2100 movs r1, #0 + 8005746: 2007 movs r0, #7 + 8005748: f003 fdc9 bl 80092de + } + convert_timeout(pp_dev_aux[current_each_device]->timeout, &buf[0]); + 800574c: 4b32 ldr r3, [pc, #200] ; (8005818 ) + 800574e: 681a ldr r2, [r3, #0] + 8005750: 4b2a ldr r3, [pc, #168] ; (80057fc ) + 8005752: 781b ldrb r3, [r3, #0] + 8005754: 009b lsls r3, r3, #2 + 8005756: 4413 add r3, r2 + 8005758: 681b ldr r3, [r3, #0] + 800575a: 689b ldr r3, [r3, #8] + 800575c: 492b ldr r1, [pc, #172] ; (800580c ) + 800575e: 4618 mov r0, r3 + 8005760: f002 fd36 bl 80081d0 + ssd1306_print(7, 4, &buf[0], 0); + 8005764: 2300 movs r3, #0 + 8005766: 4a29 ldr r2, [pc, #164] ; (800580c ) + 8005768: 2104 movs r1, #4 + 800576a: 2007 movs r0, #7 + 800576c: f003 fdb7 bl 80092de + + + + if (pp_dev_aux[current_each_device]->fence_flag) + 8005770: 4b29 ldr r3, [pc, #164] ; (8005818 ) + 8005772: 681a ldr r2, [r3, #0] + 8005774: 4b21 ldr r3, [pc, #132] ; (80057fc ) + 8005776: 781b ldrb r3, [r3, #0] + 8005778: 009b lsls r3, r3, #2 + 800577a: 4413 add r3, r2 + 800577c: 681b ldr r3, [r3, #0] + 800577e: 7b5b ldrb r3, [r3, #13] + 8005780: 2b00 cmp r3, #0 + 8005782: d006 beq.n 8005792 + { + ssd1306_print(7, 11, "FNC", 1); //print inverted + 8005784: 2301 movs r3, #1 + 8005786: 4a31 ldr r2, [pc, #196] ; (800584c ) + 8005788: 210b movs r1, #11 + 800578a: 2007 movs r0, #7 + 800578c: f003 fda7 bl 80092de + 8005790: e005 b.n 800579e + } + else + { + ssd1306_print(7, 11, "FNC", 0); + 8005792: 2300 movs r3, #0 + 8005794: 4a2d ldr r2, [pc, #180] ; (800584c ) + 8005796: 210b movs r1, #11 + 8005798: 2007 movs r0, #7 + 800579a: f003 fda0 bl 80092de + } + + + if (pp_dev_aux[current_each_device]->memory_point_flag == 0) + 800579e: 4b1e ldr r3, [pc, #120] ; (8005818 ) + 80057a0: 681a ldr r2, [r3, #0] + 80057a2: 4b16 ldr r3, [pc, #88] ; (80057fc ) + 80057a4: 781b ldrb r3, [r3, #0] + 80057a6: 009b lsls r3, r3, #2 + 80057a8: 4413 add r3, r2 + 80057aa: 681b ldr r3, [r3, #0] + 80057ac: 7b9b ldrb r3, [r3, #14] + 80057ae: 2b00 cmp r3, #0 + 80057b0: d115 bne.n 80057de + { + if (get_device_flags(current_each_device, FLAGS_ALARM) == FLAG_ALARM_ON) + 80057b2: 4b12 ldr r3, [pc, #72] ; (80057fc ) + 80057b4: 781b ldrb r3, [r3, #0] + 80057b6: 2104 movs r1, #4 + 80057b8: 4618 mov r0, r3 + 80057ba: f7fd f87f bl 80028bc + 80057be: 4603 mov r3, r0 + 80057c0: 2b01 cmp r3, #1 + 80057c2: d106 bne.n 80057d2 + { + ssd1306_print(7, 15, "ALR", 1); //print inverted + 80057c4: 2301 movs r3, #1 + 80057c6: 4a22 ldr r2, [pc, #136] ; (8005850 ) + 80057c8: 210f movs r1, #15 + 80057ca: 2007 movs r0, #7 + 80057cc: f003 fd87 bl 80092de + 80057d0: e005 b.n 80057de + } + else + { + ssd1306_print(7, 15, "ALR", 0); + 80057d2: 2300 movs r3, #0 + 80057d4: 4a1e ldr r2, [pc, #120] ; (8005850 ) + 80057d6: 210f movs r1, #15 + 80057d8: 2007 movs r0, #7 + 80057da: f003 fd80 bl 80092de + } + + + + } + ssd1306_update(); + 80057de: f003 fc57 bl 8009090 +} + 80057e2: bf00 nop + 80057e4: 370c adds r7, #12 + 80057e6: 46bd mov sp, r7 + 80057e8: bd90 pop {r4, r7, pc} + 80057ea: bf00 nop + 80057ec: f3af 8000 nop.w + 80057f0: 00000000 .word 0x00000000 + 80057f4: 412e8480 .word 0x412e8480 + 80057f8: 200007d0 .word 0x200007d0 + 80057fc: 20000032 .word 0x20000032 + 8005800: 000f423f .word 0x000f423f + 8005804: 408f4000 .word 0x408f4000 + 8005808: 200007f4 .word 0x200007f4 + 800580c: 20000810 .word 0x20000810 + 8005810: 0800ca90 .word 0x0800ca90 + 8005814: 0800ca9c .word 0x0800ca9c + 8005818: 2000083c .word 0x2000083c + 800581c: 0800ca54 .word 0x0800ca54 + 8005820: 0800caa0 .word 0x0800caa0 + 8005824: 0800caa4 .word 0x0800caa4 + 8005828: 0800caa8 .word 0x0800caa8 + 800582c: 0800caac .word 0x0800caac + 8005830: 0800ca88 .word 0x0800ca88 + 8005834: 0800cab0 .word 0x0800cab0 + 8005838: 0800cab4 .word 0x0800cab4 + 800583c: 0800cab8 .word 0x0800cab8 + 8005840: 0800cabc .word 0x0800cabc + 8005844: 0800cac0 .word 0x0800cac0 + 8005848: 0800ca84 .word 0x0800ca84 + 800584c: 0800cac4 .word 0x0800cac4 + 8005850: 0800cac8 .word 0x0800cac8 + +08005854 : + + + +void draw_each_device_submenu(void) +{ + 8005854: b580 push {r7, lr} + 8005856: af00 add r7, sp, #0 + #define EACH_DEV_SM_ROW (2) + #define EACH_DEV_SM_COL (1) + + ssd1306_clear(); + 8005858: f003 fc3a bl 80090d0 + + ssd1306_print(0, EACH_DEV_SM_COL, "DEVICE", 0); + 800585c: 2300 movs r3, #0 + 800585e: 4a25 ldr r2, [pc, #148] ; (80058f4 ) + 8005860: 2101 movs r1, #1 + 8005862: 2000 movs r0, #0 + 8005864: f003 fd3b bl 80092de + + ssd1306_print(0, EACH_DEV_SM_COL + 7, "#", 0); + 8005868: 2300 movs r3, #0 + 800586a: 4a23 ldr r2, [pc, #140] ; (80058f8 ) + 800586c: 2108 movs r1, #8 + 800586e: 2000 movs r0, #0 + 8005870: f003 fd35 bl 80092de + itoa32(current_each_device, &buf[0]); + 8005874: 4b21 ldr r3, [pc, #132] ; (80058fc ) + 8005876: 781b ldrb r3, [r3, #0] + 8005878: 4921 ldr r1, [pc, #132] ; (8005900 ) + 800587a: 4618 mov r0, r3 + 800587c: f002 ffcc bl 8008818 + ssd1306_print(0, EACH_DEV_SM_COL + 8, &buf[0], 0); + 8005880: 2300 movs r3, #0 + 8005882: 4a1f ldr r2, [pc, #124] ; (8005900 ) + 8005884: 2109 movs r1, #9 + 8005886: 2000 movs r0, #0 + 8005888: f003 fd29 bl 80092de + + ssd1306_char_pos(0, EACH_DEV_SM_COL + 10, pp_gps_air[current_each_device]->device_id[0], 0); + 800588c: 4b1d ldr r3, [pc, #116] ; (8005904 ) + 800588e: 681a ldr r2, [r3, #0] + 8005890: 4b1a ldr r3, [pc, #104] ; (80058fc ) + 8005892: 781b ldrb r3, [r3, #0] + 8005894: 009b lsls r3, r3, #2 + 8005896: 4413 add r3, r2 + 8005898: 681b ldr r3, [r3, #0] + 800589a: 781a ldrb r2, [r3, #0] + 800589c: 2300 movs r3, #0 + 800589e: 210b movs r1, #11 + 80058a0: 2000 movs r0, #0 + 80058a2: f003 fcfd bl 80092a0 + ssd1306_char_pos(0, EACH_DEV_SM_COL + 11, pp_gps_air[current_each_device]->device_id[1], 0); + 80058a6: 4b17 ldr r3, [pc, #92] ; (8005904 ) + 80058a8: 681a ldr r2, [r3, #0] + 80058aa: 4b14 ldr r3, [pc, #80] ; (80058fc ) + 80058ac: 781b ldrb r3, [r3, #0] + 80058ae: 009b lsls r3, r3, #2 + 80058b0: 4413 add r3, r2 + 80058b2: 681b ldr r3, [r3, #0] + 80058b4: 785a ldrb r2, [r3, #1] + 80058b6: 2300 movs r3, #0 + 80058b8: 210c movs r1, #12 + 80058ba: 2000 movs r0, #0 + 80058bc: f003 fcf0 bl 80092a0 + + ssd1306_print(EACH_DEV_SM_ROW, EACH_DEV_SM_COL, "Save", 0); + 80058c0: 2300 movs r3, #0 + 80058c2: 4a11 ldr r2, [pc, #68] ; (8005908 ) + 80058c4: 2101 movs r1, #1 + 80058c6: 2002 movs r0, #2 + 80058c8: f003 fd09 bl 80092de + ssd1306_print(EACH_DEV_SM_ROW + 1, EACH_DEV_SM_COL, "Delete", 0); + 80058cc: 2300 movs r3, #0 + 80058ce: 4a0f ldr r2, [pc, #60] ; (800590c ) + 80058d0: 2101 movs r1, #1 + 80058d2: 2003 movs r0, #3 + 80058d4: f003 fd03 bl 80092de + ssd1306_print(EACH_DEV_SM_ROW + get_current_item(), EACH_DEV_SM_COL - 1, ">", 0); + 80058d8: f7fe fc44 bl 8004164 + 80058dc: 4603 mov r3, r0 + 80058de: 3302 adds r3, #2 + 80058e0: b2d8 uxtb r0, r3 + 80058e2: 2300 movs r3, #0 + 80058e4: 4a0a ldr r2, [pc, #40] ; (8005910 ) + 80058e6: 2100 movs r1, #0 + 80058e8: f003 fcf9 bl 80092de + + ssd1306_update(); + 80058ec: f003 fbd0 bl 8009090 +} + 80058f0: bf00 nop + 80058f2: bd80 pop {r7, pc} + 80058f4: 0800cacc .word 0x0800cacc + 80058f8: 0800ca1c .word 0x0800ca1c + 80058fc: 20000032 .word 0x20000032 + 8005900: 20000810 .word 0x20000810 + 8005904: 20000804 .word 0x20000804 + 8005908: 0800cad4 .word 0x0800cad4 + 800590c: 0800cadc .word 0x0800cadc + 8005910: 0800ca14 .word 0x0800ca14 + +08005914 : + + + +void draw_delete_device(void) +{ + 8005914: b580 push {r7, lr} + 8005916: af00 add r7, sp, #0 + ssd1306_clear(); + 8005918: f003 fbda bl 80090d0 + ssd1306_print(0, 1, "Delete device", 0); + 800591c: 2300 movs r3, #0 + 800591e: 4a29 ldr r2, [pc, #164] ; (80059c4 ) + 8005920: 2101 movs r1, #1 + 8005922: 2000 movs r0, #0 + 8005924: f003 fcdb bl 80092de + + ssd1306_print(0, 15, "#", 0); + 8005928: 2300 movs r3, #0 + 800592a: 4a27 ldr r2, [pc, #156] ; (80059c8 ) + 800592c: 210f movs r1, #15 + 800592e: 2000 movs r0, #0 + 8005930: f003 fcd5 bl 80092de + itoa32(current_each_device, &buf[0]); + 8005934: 4b25 ldr r3, [pc, #148] ; (80059cc ) + 8005936: 781b ldrb r3, [r3, #0] + 8005938: 4925 ldr r1, [pc, #148] ; (80059d0 ) + 800593a: 4618 mov r0, r3 + 800593c: f002 ff6c bl 8008818 + ssd1306_print(0, 16, &buf[0], 0); + 8005940: 2300 movs r3, #0 + 8005942: 4a23 ldr r2, [pc, #140] ; (80059d0 ) + 8005944: 2110 movs r1, #16 + 8005946: 2000 movs r0, #0 + 8005948: f003 fcc9 bl 80092de + + ssd1306_char_pos(0, 18, pp_gps_air[current_each_device]->device_id[0], 0); + 800594c: 4b21 ldr r3, [pc, #132] ; (80059d4 ) + 800594e: 681a ldr r2, [r3, #0] + 8005950: 4b1e ldr r3, [pc, #120] ; (80059cc ) + 8005952: 781b ldrb r3, [r3, #0] + 8005954: 009b lsls r3, r3, #2 + 8005956: 4413 add r3, r2 + 8005958: 681b ldr r3, [r3, #0] + 800595a: 781a ldrb r2, [r3, #0] + 800595c: 2300 movs r3, #0 + 800595e: 2112 movs r1, #18 + 8005960: 2000 movs r0, #0 + 8005962: f003 fc9d bl 80092a0 + ssd1306_char_pos(0, 19, pp_gps_air[current_each_device]->device_id[1], 0); + 8005966: 4b1b ldr r3, [pc, #108] ; (80059d4 ) + 8005968: 681a ldr r2, [r3, #0] + 800596a: 4b18 ldr r3, [pc, #96] ; (80059cc ) + 800596c: 781b ldrb r3, [r3, #0] + 800596e: 009b lsls r3, r3, #2 + 8005970: 4413 add r3, r2 + 8005972: 681b ldr r3, [r3, #0] + 8005974: 785a ldrb r2, [r3, #1] + 8005976: 2300 movs r3, #0 + 8005978: 2113 movs r1, #19 + 800597a: 2000 movs r0, #0 + 800597c: f003 fc90 bl 80092a0 + + ssd1306_print_next("?", 0); + 8005980: 2100 movs r1, #0 + 8005982: 4815 ldr r0, [pc, #84] ; (80059d8 ) + 8005984: f003 fd0a bl 800939c + + + if (current_each_device == device_number) + 8005988: 4b10 ldr r3, [pc, #64] ; (80059cc ) + 800598a: 781a ldrb r2, [r3, #0] + 800598c: 4b13 ldr r3, [pc, #76] ; (80059dc ) + 800598e: 781b ldrb r3, [r3, #0] + 8005990: 429a cmp r2, r3 + 8005992: d106 bne.n 80059a2 + { + ssd1306_print(3, 1, "Can't del yourself", 0); + 8005994: 2300 movs r3, #0 + 8005996: 4a12 ldr r2, [pc, #72] ; (80059e0 ) + 8005998: 2101 movs r1, #1 + 800599a: 2003 movs r0, #3 + 800599c: f003 fc9f bl 80092de + 80059a0: e005 b.n 80059ae + } + else + { + ssd1306_print(3, 1, "OK - delete", 0); + 80059a2: 2300 movs r3, #0 + 80059a4: 4a0f ldr r2, [pc, #60] ; (80059e4 ) + 80059a6: 2101 movs r1, #1 + 80059a8: 2003 movs r0, #3 + 80059aa: f003 fc98 bl 80092de + } + + ssd1306_print(4, 1, "ESC - cancel", 0); + 80059ae: 2300 movs r3, #0 + 80059b0: 4a0d ldr r2, [pc, #52] ; (80059e8 ) + 80059b2: 2101 movs r1, #1 + 80059b4: 2004 movs r0, #4 + 80059b6: f003 fc92 bl 80092de + + ssd1306_update(); + 80059ba: f003 fb69 bl 8009090 +} + 80059be: bf00 nop + 80059c0: bd80 pop {r7, pc} + 80059c2: bf00 nop + 80059c4: 0800cae4 .word 0x0800cae4 + 80059c8: 0800ca1c .word 0x0800ca1c + 80059cc: 20000032 .word 0x20000032 + 80059d0: 20000810 .word 0x20000810 + 80059d4: 20000804 .word 0x20000804 + 80059d8: 0800caf4 .word 0x0800caf4 + 80059dc: 20000738 .word 0x20000738 + 80059e0: 0800caf8 .word 0x0800caf8 + 80059e4: 0800cb0c .word 0x0800cb0c + 80059e8: 0800cb18 .word 0x0800cb18 + +080059ec : + + + +void delete_device_ok(void) +{ + 80059ec: b580 push {r7, lr} + 80059ee: af00 add r7, sp, #0 + if (current_each_device != device_number) + 80059f0: 4b12 ldr r3, [pc, #72] ; (8005a3c ) + 80059f2: 781a ldrb r2, [r3, #0] + 80059f4: 4b12 ldr r3, [pc, #72] ; (8005a40 ) + 80059f6: 781b ldrb r3, [r3, #0] + 80059f8: 429a cmp r2, r3 + 80059fa: d01d beq.n 8005a38 + { + pp_dev_aux[current_each_device]->exist_flag = 0; //delete device just by resetting exist flag + 80059fc: 4b11 ldr r3, [pc, #68] ; (8005a44 ) + 80059fe: 681a ldr r2, [r3, #0] + 8005a00: 4b0e ldr r3, [pc, #56] ; (8005a3c ) + 8005a02: 781b ldrb r3, [r3, #0] + 8005a04: 009b lsls r3, r3, #2 + 8005a06: 4413 add r3, r2 + 8005a08: 681b ldr r3, [r3, #0] + 8005a0a: 2200 movs r2, #0 + 8005a0c: 701a strb r2, [r3, #0] + current_each_device = device_number; //also reset the current device + 8005a0e: 4b0c ldr r3, [pc, #48] ; (8005a40 ) + 8005a10: 781a ldrb r2, [r3, #0] + 8005a12: 4b0a ldr r3, [pc, #40] ; (8005a3c ) + 8005a14: 701a strb r2, [r3, #0] + current_radar_device = 0; //reset current dev in radar menu + 8005a16: 4b0c ldr r3, [pc, #48] ; (8005a48 ) + 8005a18: 2200 movs r2, #0 + 8005a1a: 701a strb r2, [r3, #0] + radar_list_hide[current_each_device] = 0;//reset hide flag + 8005a1c: 4b07 ldr r3, [pc, #28] ; (8005a3c ) + 8005a1e: 781b ldrb r3, [r3, #0] + 8005a20: 461a mov r2, r3 + 8005a22: 4b0a ldr r3, [pc, #40] ; (8005a4c ) + 8005a24: 2100 movs r1, #0 + 8005a26: 5499 strb r1, [r3, r2] + + reset_current_item_in_menu(M_EACH_DEVICE_SUBMENU); + 8005a28: 2004 movs r0, #4 + 8005a2a: f7fe fc2d bl 8004288 + current_menu = M_DEVICES; + 8005a2e: 4b08 ldr r3, [pc, #32] ; (8005a50 ) + 8005a30: 2202 movs r2, #2 + 8005a32: 701a strb r2, [r3, #0] + draw_current_menu(); + 8005a34: f7fe fc58 bl 80042e8 + } +} + 8005a38: bf00 nop + 8005a3a: bd80 pop {r7, pc} + 8005a3c: 20000032 .word 0x20000032 + 8005a40: 20000738 .word 0x20000738 + 8005a44: 2000083c .word 0x2000083c + 8005a48: 20000121 .word 0x20000121 + 8005a4c: 20000830 .word 0x20000830 + 8005a50: 200007fa .word 0x200007fa + +08005a54 : + + + +void draw_save_device(void) +{ + 8005a54: b580 push {r7, lr} + 8005a56: b082 sub sp, #8 + 8005a58: af00 add r7, sp, #0 + #define SAVE_DEVICE_ROW (2) + #define SAVE_DEVICE_COL (1) + + memcpy(point_to_save_name, point_to_save_default_name, sizeof(point_to_save_default_name)); //init default name here + 8005a5a: 4b48 ldr r3, [pc, #288] ; (8005b7c ) + 8005a5c: 4a48 ldr r2, [pc, #288] ; (8005b80 ) + 8005a5e: 6810 ldr r0, [r2, #0] + 8005a60: 6018 str r0, [r3, #0] + 8005a62: 8892 ldrh r2, [r2, #4] + 8005a64: 809a strh r2, [r3, #4] + + ssd1306_clear(); + 8005a66: f003 fb33 bl 80090d0 + + ssd1306_print(0, SAVE_DEVICE_COL, "Where to save", 0); + 8005a6a: 2300 movs r3, #0 + 8005a6c: 4a45 ldr r2, [pc, #276] ; (8005b84 ) + 8005a6e: 2101 movs r1, #1 + 8005a70: 2000 movs r0, #0 + 8005a72: f003 fc34 bl 80092de + + ssd1306_print(0, SAVE_DEVICE_COL + 14, "#", 0); + 8005a76: 2300 movs r3, #0 + 8005a78: 4a43 ldr r2, [pc, #268] ; (8005b88 ) + 8005a7a: 210f movs r1, #15 + 8005a7c: 2000 movs r0, #0 + 8005a7e: f003 fc2e bl 80092de + itoa32(current_each_device, &buf[0]); + 8005a82: 4b42 ldr r3, [pc, #264] ; (8005b8c ) + 8005a84: 781b ldrb r3, [r3, #0] + 8005a86: 4942 ldr r1, [pc, #264] ; (8005b90 ) + 8005a88: 4618 mov r0, r3 + 8005a8a: f002 fec5 bl 8008818 + ssd1306_print(0, SAVE_DEVICE_COL + 15, &buf[0], 0); + 8005a8e: 2300 movs r3, #0 + 8005a90: 4a3f ldr r2, [pc, #252] ; (8005b90 ) + 8005a92: 2110 movs r1, #16 + 8005a94: 2000 movs r0, #0 + 8005a96: f003 fc22 bl 80092de + + ssd1306_char_pos(0, SAVE_DEVICE_COL + 17, pp_gps_air[current_each_device]->device_id[0], 0); + 8005a9a: 4b3e ldr r3, [pc, #248] ; (8005b94 ) + 8005a9c: 681a ldr r2, [r3, #0] + 8005a9e: 4b3b ldr r3, [pc, #236] ; (8005b8c ) + 8005aa0: 781b ldrb r3, [r3, #0] + 8005aa2: 009b lsls r3, r3, #2 + 8005aa4: 4413 add r3, r2 + 8005aa6: 681b ldr r3, [r3, #0] + 8005aa8: 781a ldrb r2, [r3, #0] + 8005aaa: 2300 movs r3, #0 + 8005aac: 2112 movs r1, #18 + 8005aae: 2000 movs r0, #0 + 8005ab0: f003 fbf6 bl 80092a0 + ssd1306_char_pos(0, SAVE_DEVICE_COL + 18, pp_gps_air[current_each_device]->device_id[1], 0); + 8005ab4: 4b37 ldr r3, [pc, #220] ; (8005b94 ) + 8005ab6: 681a ldr r2, [r3, #0] + 8005ab8: 4b34 ldr r3, [pc, #208] ; (8005b8c ) + 8005aba: 781b ldrb r3, [r3, #0] + 8005abc: 009b lsls r3, r3, #2 + 8005abe: 4413 add r3, r2 + 8005ac0: 681b ldr r3, [r3, #0] + 8005ac2: 785a ldrb r2, [r3, #1] + 8005ac4: 2300 movs r3, #0 + 8005ac6: 2113 movs r1, #19 + 8005ac8: 2000 movs r0, #0 + 8005aca: f003 fbe9 bl 80092a0 + + ssd1306_print_next("?", 0); + 8005ace: 2100 movs r1, #0 + 8005ad0: 4831 ldr r0, [pc, #196] ; (8005b98 ) + 8005ad2: f003 fc63 bl 800939c + + read_memory_slots(); + 8005ad6: f002 f911 bl 8007cfc + + uint8_t another_point_to_save_row = SAVE_DEVICE_ROW; + 8005ada: 2302 movs r3, #2 + 8005adc: 71fb strb r3, [r7, #7] + uint8_t points_enlisted_cntr = 0; + 8005ade: 2300 movs r3, #0 + 8005ae0: 71bb strb r3, [r7, #6] + + for (uint8_t s = 1; s <= MEMORY_SLOTS_TOTAL; s++) + 8005ae2: 2301 movs r3, #1 + 8005ae4: 717b strb r3, [r7, #5] + 8005ae6: e027 b.n 8005b38 + { + if (pp_memory_slot[s]->exist_flag == 0) + 8005ae8: 4b2c ldr r3, [pc, #176] ; (8005b9c ) + 8005aea: 681a ldr r2, [r3, #0] + 8005aec: 797b ldrb r3, [r7, #5] + 8005aee: 009b lsls r3, r3, #2 + 8005af0: 4413 add r3, r2 + 8005af2: 681b ldr r3, [r3, #0] + 8005af4: 781b ldrb r3, [r3, #0] + 8005af6: 2b00 cmp r3, #0 + 8005af8: d11b bne.n 8005b32 + { + point_to_save_list[s] = points_enlisted_cntr++; //first nonexisting point will get index 0 + 8005afa: 79bb ldrb r3, [r7, #6] + 8005afc: 1c5a adds r2, r3, #1 + 8005afe: 71ba strb r2, [r7, #6] + 8005b00: 797a ldrb r2, [r7, #5] + 8005b02: 4927 ldr r1, [pc, #156] ; (8005ba0 ) + 8005b04: 548b strb r3, [r1, r2] + + if (current_slot_to_save == 0) //if for the first time + 8005b06: 4b27 ldr r3, [pc, #156] ; (8005ba4 ) + 8005b08: 781b ldrb r3, [r3, #0] + 8005b0a: 2b00 cmp r3, #0 + 8005b0c: d102 bne.n 8005b14 + { + current_slot_to_save = s; + 8005b0e: 4a25 ldr r2, [pc, #148] ; (8005ba4 ) + 8005b10: 797b ldrb r3, [r7, #5] + 8005b12: 7013 strb r3, [r2, #0] + } + + //Slot name + ssd1306_print(another_point_to_save_row, SAVE_DEVICE_COL, pp_memory_slot[s]->slot_name, 0); + 8005b14: 4b21 ldr r3, [pc, #132] ; (8005b9c ) + 8005b16: 681a ldr r2, [r3, #0] + 8005b18: 797b ldrb r3, [r7, #5] + 8005b1a: 009b lsls r3, r3, #2 + 8005b1c: 4413 add r3, r2 + 8005b1e: 681b ldr r3, [r3, #0] + 8005b20: 1c5a adds r2, r3, #1 + 8005b22: 79f8 ldrb r0, [r7, #7] + 8005b24: 2300 movs r3, #0 + 8005b26: 2101 movs r1, #1 + 8005b28: f003 fbd9 bl 80092de + + another_point_to_save_row++; + 8005b2c: 79fb ldrb r3, [r7, #7] + 8005b2e: 3301 adds r3, #1 + 8005b30: 71fb strb r3, [r7, #7] + for (uint8_t s = 1; s <= MEMORY_SLOTS_TOTAL; s++) + 8005b32: 797b ldrb r3, [r7, #5] + 8005b34: 3301 adds r3, #1 + 8005b36: 717b strb r3, [r7, #5] + 8005b38: 797b ldrb r3, [r7, #5] + 8005b3a: 2b05 cmp r3, #5 + 8005b3c: d9d4 bls.n 8005ae8 + } + } + + if (points_enlisted_cntr > 0) + 8005b3e: 79bb ldrb r3, [r7, #6] + 8005b40: 2b00 cmp r3, #0 + 8005b42: d00c beq.n 8005b5e + { + ssd1306_print(SAVE_DEVICE_ROW + point_to_save_list[current_slot_to_save], SAVE_DEVICE_COL - 1, ">", 0); + 8005b44: 4b17 ldr r3, [pc, #92] ; (8005ba4 ) + 8005b46: 781b ldrb r3, [r3, #0] + 8005b48: 461a mov r2, r3 + 8005b4a: 4b15 ldr r3, [pc, #84] ; (8005ba0 ) + 8005b4c: 5c9b ldrb r3, [r3, r2] + 8005b4e: 3302 adds r3, #2 + 8005b50: b2d8 uxtb r0, r3 + 8005b52: 2300 movs r3, #0 + 8005b54: 4a14 ldr r2, [pc, #80] ; (8005ba8 ) + 8005b56: 2100 movs r1, #0 + 8005b58: f003 fbc1 bl 80092de + 8005b5c: e008 b.n 8005b70 + } + else + { + ssd1306_print(SAVE_DEVICE_ROW, SAVE_DEVICE_COL, "no empty slots", 0); + 8005b5e: 2300 movs r3, #0 + 8005b60: 4a12 ldr r2, [pc, #72] ; (8005bac ) + 8005b62: 2101 movs r1, #1 + 8005b64: 2002 movs r0, #2 + 8005b66: f003 fbba bl 80092de + current_slot_to_save = 0; + 8005b6a: 4b0e ldr r3, [pc, #56] ; (8005ba4 ) + 8005b6c: 2200 movs r2, #0 + 8005b6e: 701a strb r2, [r3, #0] + } + + ssd1306_update(); + 8005b70: f003 fa8e bl 8009090 +} + 8005b74: bf00 nop + 8005b76: 3708 adds r7, #8 + 8005b78: 46bd mov sp, r7 + 8005b7a: bd80 pop {r7, pc} + 8005b7c: 20000828 .word 0x20000828 + 8005b80: 0800d260 .word 0x0800d260 + 8005b84: 0800cb28 .word 0x0800cb28 + 8005b88: 0800ca1c .word 0x0800ca1c + 8005b8c: 20000032 .word 0x20000032 + 8005b90: 20000810 .word 0x20000810 + 8005b94: 20000804 .word 0x20000804 + 8005b98: 0800caf4 .word 0x0800caf4 + 8005b9c: 200007d4 .word 0x200007d4 + 8005ba0: 200007fc .word 0x200007fc + 8005ba4: 20000123 .word 0x20000123 + 8005ba8: 0800ca14 .word 0x0800ca14 + 8005bac: 0800cb38 .word 0x0800cb38 + +08005bb0 : + + + +void draw_save_device_as(void) +{ + 8005bb0: b580 push {r7, lr} + 8005bb2: af00 add r7, sp, #0 + #define SAVE_DEV_AS_ROW (2) + #define SAVE_DEV_AS_COL (1) + #define SAVE_DEV_AS_PARAM_COL (11) + + ssd1306_clear(); + 8005bb4: f003 fa8c bl 80090d0 + ssd1306_print(0, SAVE_DEV_AS_COL, "Set point name", 0); + 8005bb8: 2300 movs r3, #0 + 8005bba: 4a12 ldr r2, [pc, #72] ; (8005c04 ) + 8005bbc: 2101 movs r1, #1 + 8005bbe: 2000 movs r0, #0 + 8005bc0: f003 fb8d bl 80092de + + ssd1306_print(SAVE_DEV_AS_ROW, SAVE_DEV_AS_COL, "Name", 0); + 8005bc4: 2300 movs r3, #0 + 8005bc6: 4a10 ldr r2, [pc, #64] ; (8005c08 ) + 8005bc8: 2101 movs r1, #1 + 8005bca: 2002 movs r0, #2 + 8005bcc: f003 fb87 bl 80092de + ssd1306_print(SAVE_DEV_AS_ROW, SAVE_DEV_AS_PARAM_COL, point_to_save_name, 0); + 8005bd0: 2300 movs r3, #0 + 8005bd2: 4a0e ldr r2, [pc, #56] ; (8005c0c ) + 8005bd4: 210b movs r1, #11 + 8005bd6: 2002 movs r0, #2 + 8005bd8: f003 fb81 bl 80092de + ssd1306_print(SAVE_DEV_AS_ROW + 1, SAVE_DEV_AS_PARAM_COL + point_name_current_symbol, "^", 0); + 8005bdc: 4b0c ldr r3, [pc, #48] ; (8005c10 ) + 8005bde: 781b ldrb r3, [r3, #0] + 8005be0: 330b adds r3, #11 + 8005be2: b2d9 uxtb r1, r3 + 8005be4: 2300 movs r3, #0 + 8005be6: 4a0b ldr r2, [pc, #44] ; (8005c14 ) + 8005be8: 2003 movs r0, #3 + 8005bea: f003 fb78 bl 80092de + ssd1306_print(SAVE_DEV_AS_ROW + 3, SAVE_DEV_AS_COL, "Long OK - save", 0); + 8005bee: 2300 movs r3, #0 + 8005bf0: 4a09 ldr r2, [pc, #36] ; (8005c18 ) + 8005bf2: 2101 movs r1, #1 + 8005bf4: 2005 movs r0, #5 + 8005bf6: f003 fb72 bl 80092de + ssd1306_update(); + 8005bfa: f003 fa49 bl 8009090 +} + 8005bfe: bf00 nop + 8005c00: bd80 pop {r7, pc} + 8005c02: bf00 nop + 8005c04: 0800cb48 .word 0x0800cb48 + 8005c08: 0800cb58 .word 0x0800cb58 + 8005c0c: 20000828 .word 0x20000828 + 8005c10: 20000120 .word 0x20000120 + 8005c14: 0800cb60 .word 0x0800cb60 + 8005c18: 0800cb64 .word 0x0800cb64 + +08005c1c : + + + +void draw_saved_popup(void) +{ + 8005c1c: b580 push {r7, lr} + 8005c1e: af00 add r7, sp, #0 + ssd1306_clear(); + 8005c20: f003 fa56 bl 80090d0 + ssd1306_print(0, 1, "Saved!", 0); + 8005c24: 2300 movs r3, #0 + 8005c26: 4a04 ldr r2, [pc, #16] ; (8005c38 ) + 8005c28: 2101 movs r1, #1 + 8005c2a: 2000 movs r0, #0 + 8005c2c: f003 fb57 bl 80092de + ssd1306_update(); + 8005c30: f003 fa2e bl 8009090 +} + 8005c34: bf00 nop + 8005c36: bd80 pop {r7, pc} + 8005c38: 0800cb74 .word 0x0800cb74 + 8005c3c: 00000000 .word 0x00000000 + +08005c40 : + + + +//RADAR +void draw_radar(void) +{ + 8005c40: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8005c44: b08d sub sp, #52 ; 0x34 + 8005c46: af00 add r7, sp, #0 + ssd1306_clear(); + 8005c48: f003 fa42 bl 80090d0 + ssd1306_bitmap(&radar_blank[0]); + 8005c4c: 48b9 ldr r0, [pc, #740] ; (8005f34 ) + 8005c4e: f003 fbbd bl 80093cc + + //My status row + uint8_t icon_col = LCD_LAST_COL; + 8005c52: 2314 movs r3, #20 + 8005c54: f887 302f strb.w r3, [r7, #47] ; 0x2f + + + //Battery + switch (get_device_flags(device_number, FLAGS_BATTERY)) + 8005c58: 4bb7 ldr r3, [pc, #732] ; (8005f38 ) + 8005c5a: 781b ldrb r3, [r3, #0] + 8005c5c: 2101 movs r1, #1 + 8005c5e: 4618 mov r0, r3 + 8005c60: f7fc fe2c bl 80028bc + 8005c64: 4603 mov r3, r0 + 8005c66: 2b04 cmp r3, #4 + 8005c68: d843 bhi.n 8005cf2 + 8005c6a: a201 add r2, pc, #4 ; (adr r2, 8005c70 ) + 8005c6c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005c70: 08005cdd .word 0x08005cdd + 8005c74: 08005cc7 .word 0x08005cc7 + 8005c78: 08005cb1 .word 0x08005cb1 + 8005c7c: 08005c9b .word 0x08005c9b + 8005c80: 08005c85 .word 0x08005c85 + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_4OF4, 0); + 8005c84: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005c88: 1e4b subs r3, r1, #1 + 8005c8a: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005c8e: 2300 movs r3, #0 + 8005c90: 228c movs r2, #140 ; 0x8c + 8005c92: 2000 movs r0, #0 + 8005c94: f003 fb04 bl 80092a0 + break; + 8005c98: e02b b.n 8005cf2 + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_3OF4, 0); + 8005c9a: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005c9e: 1e4b subs r3, r1, #1 + 8005ca0: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005ca4: 2300 movs r3, #0 + 8005ca6: 228b movs r2, #139 ; 0x8b + 8005ca8: 2000 movs r0, #0 + 8005caa: f003 faf9 bl 80092a0 + break; + 8005cae: e020 b.n 8005cf2 + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_2OF4, 0); + 8005cb0: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005cb4: 1e4b subs r3, r1, #1 + 8005cb6: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005cba: 2300 movs r3, #0 + 8005cbc: 228a movs r2, #138 ; 0x8a + 8005cbe: 2000 movs r0, #0 + 8005cc0: f003 faee bl 80092a0 + break; + 8005cc4: e015 b.n 8005cf2 + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_1OF4, 0); + 8005cc6: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005cca: 1e4b subs r3, r1, #1 + 8005ccc: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005cd0: 2300 movs r3, #0 + 8005cd2: 2289 movs r2, #137 ; 0x89 + 8005cd4: 2000 movs r0, #0 + 8005cd6: f003 fae3 bl 80092a0 + break; + 8005cda: e00a b.n 8005cf2 + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(0, icon_col--, SYMB_BAT_0OF4, 0); + 8005cdc: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005ce0: 1e4b subs r3, r1, #1 + 8005ce2: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005ce6: 2300 movs r3, #0 + 8005ce8: 2288 movs r2, #136 ; 0x88 + 8005cea: 2000 movs r0, #0 + 8005cec: f003 fad8 bl 80092a0 + break; + 8005cf0: bf00 nop + } + + + //Sattelites + if (p_gps_raw->time[0] == 0) //if no time received then no sattelites at all + 8005cf2: 4b92 ldr r3, [pc, #584] ; (8005f3c ) + 8005cf4: 681b ldr r3, [r3, #0] + 8005cf6: 781b ldrb r3, [r3, #0] + 8005cf8: 2b00 cmp r3, #0 + 8005cfa: d10a bne.n 8005d12 + { + ssd1306_char_pos(0, icon_col--, SYMB_NO_SATT, 0); + 8005cfc: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005d00: 1e4b subs r3, r1, #1 + 8005d02: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005d06: 2300 movs r3, #0 + 8005d08: 2282 movs r2, #130 ; 0x82 + 8005d0a: 2000 movs r0, #0 + 8005d0c: f003 fac8 bl 80092a0 + 8005d10: e037 b.n 8005d82 + } + else + { + if (p_gps_num->mode == GPS_POSITION_3DFIX && p_gps_num->status == GPS_DATA_VALID) + 8005d12: 4b8b ldr r3, [pc, #556] ; (8005f40 ) + 8005d14: 681b ldr r3, [r3, #0] + 8005d16: f893 3037 ldrb.w r3, [r3, #55] ; 0x37 + 8005d1a: 2b03 cmp r3, #3 + 8005d1c: d110 bne.n 8005d40 + 8005d1e: 4b88 ldr r3, [pc, #544] ; (8005f40 ) + 8005d20: 681b ldr r3, [r3, #0] + 8005d22: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 + 8005d26: 2b01 cmp r3, #1 + 8005d28: d10a bne.n 8005d40 + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_3D, 0); //3D when data is valid + 8005d2a: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005d2e: 1e4b subs r3, r1, #1 + 8005d30: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005d34: 2300 movs r3, #0 + 8005d36: 2285 movs r2, #133 ; 0x85 + 8005d38: 2000 movs r0, #0 + 8005d3a: f003 fab1 bl 80092a0 + 8005d3e: e020 b.n 8005d82 + } + else if (p_gps_num->mode == GPS_POSITION_2DFIX && p_gps_num->status == GPS_DATA_VALID) + 8005d40: 4b7f ldr r3, [pc, #508] ; (8005f40 ) + 8005d42: 681b ldr r3, [r3, #0] + 8005d44: f893 3037 ldrb.w r3, [r3, #55] ; 0x37 + 8005d48: 2b02 cmp r3, #2 + 8005d4a: d110 bne.n 8005d6e + 8005d4c: 4b7c ldr r3, [pc, #496] ; (8005f40 ) + 8005d4e: 681b ldr r3, [r3, #0] + 8005d50: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 + 8005d54: 2b01 cmp r3, #1 + 8005d56: d10a bne.n 8005d6e + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_2D, 0); //2D when data is valid + 8005d58: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005d5c: 1e4b subs r3, r1, #1 + 8005d5e: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005d62: 2300 movs r3, #0 + 8005d64: 2284 movs r2, #132 ; 0x84 + 8005d66: 2000 movs r0, #0 + 8005d68: f003 fa9a bl 80092a0 + 8005d6c: e009 b.n 8005d82 + } + else + { + ssd1306_char_pos(0, icon_col--, SYMB_SATT_1D, 0); //if not 2D or 3D then only time is avaliable + 8005d6e: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005d72: 1e4b subs r3, r1, #1 + 8005d74: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005d78: 2300 movs r3, #0 + 8005d7a: 2283 movs r2, #131 ; 0x83 + 8005d7c: 2000 movs r0, #0 + 8005d7e: f003 fa8f bl 80092a0 + } + } + + //TRX + if (get_main_flags()->gps_sync) + 8005d82: f7fe f83f bl 8003e04 + 8005d86: 4603 mov r3, r0 + 8005d88: 785b ldrb r3, [r3, #1] + 8005d8a: 2b00 cmp r3, #0 + 8005d8c: d013 beq.n 8005db6 + { + ssd1306_char_pos(0, icon_col--, SYMB_ARROW_DOWN, 0); + 8005d8e: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005d92: 1e4b subs r3, r1, #1 + 8005d94: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005d98: 2300 movs r3, #0 + 8005d9a: 2281 movs r2, #129 ; 0x81 + 8005d9c: 2000 movs r0, #0 + 8005d9e: f003 fa7f bl 80092a0 + ssd1306_char_pos(0, icon_col--, SYMB_ARROW_UP, 0); + 8005da2: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005da6: 1e4b subs r3, r1, #1 + 8005da8: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005dac: 2300 movs r3, #0 + 8005dae: 2280 movs r2, #128 ; 0x80 + 8005db0: 2000 movs r0, #0 + 8005db2: f003 fa75 bl 80092a0 + } + + + + //Timeout + if (pp_dev_aux[device_number]->timeout_flag) + 8005db6: 4b63 ldr r3, [pc, #396] ; (8005f44 ) + 8005db8: 681a ldr r2, [r3, #0] + 8005dba: 4b5f ldr r3, [pc, #380] ; (8005f38 ) + 8005dbc: 781b ldrb r3, [r3, #0] + 8005dbe: 009b lsls r3, r3, #2 + 8005dc0: 4413 add r3, r2 + 8005dc2: 681b ldr r3, [r3, #0] + 8005dc4: 7b1b ldrb r3, [r3, #12] + 8005dc6: 2b00 cmp r3, #0 + 8005dc8: d009 beq.n 8005dde + { + ssd1306_char_pos(0, icon_col--, SYMB_TIMEOUT, 0); + 8005dca: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005dce: 1e4b subs r3, r1, #1 + 8005dd0: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005dd4: 2300 movs r3, #0 + 8005dd6: 2286 movs r2, #134 ; 0x86 + 8005dd8: 2000 movs r0, #0 + 8005dda: f003 fa61 bl 80092a0 + } + + //Alarm + if (get_device_flags(device_number, FLAGS_ALARM) == FLAG_ALARM_ON) + 8005dde: 4b56 ldr r3, [pc, #344] ; (8005f38 ) + 8005de0: 781b ldrb r3, [r3, #0] + 8005de2: 2104 movs r1, #4 + 8005de4: 4618 mov r0, r3 + 8005de6: f7fc fd69 bl 80028bc + 8005dea: 4603 mov r3, r0 + 8005dec: 2b01 cmp r3, #1 + 8005dee: d109 bne.n 8005e04 + { + ssd1306_char_pos(0, icon_col--, SYMB_ALARM, 0); + 8005df0: f897 102f ldrb.w r1, [r7, #47] ; 0x2f + 8005df4: 1e4b subs r3, r1, #1 + 8005df6: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8005dfa: 2300 movs r3, #0 + 8005dfc: 2287 movs r2, #135 ; 0x87 + 8005dfe: 2000 movs r0, #0 + 8005e00: f003 fa4e bl 80092a0 + } + + + + //COG + itoa32(pp_gps_air[device_number]->course.as_integer, &buf[0]); + 8005e04: 4b50 ldr r3, [pc, #320] ; (8005f48 ) + 8005e06: 681a ldr r2, [r3, #0] + 8005e08: 4b4b ldr r3, [pc, #300] ; (8005f38 ) + 8005e0a: 781b ldrb r3, [r3, #0] + 8005e0c: 009b lsls r3, r3, #2 + 8005e0e: 4413 add r3, r2 + 8005e10: 681b ldr r3, [r3, #0] + 8005e12: 8a1b ldrh r3, [r3, #16] + 8005e14: 494d ldr r1, [pc, #308] ; (8005f4c ) + 8005e16: 4618 mov r0, r3 + 8005e18: f002 fcfe bl 8008818 + ssd1306_print_viceversa(0, 7, &buf[0], 0); + 8005e1c: 2300 movs r3, #0 + 8005e1e: 4a4b ldr r2, [pc, #300] ; (8005f4c ) + 8005e20: 2107 movs r1, #7 + 8005e22: 2000 movs r0, #0 + 8005e24: f003 fa7e bl 8009324 + + + + uint8_t another_radar_dev_row = ANOTHER_RADAR_DEVICE_START_ROW; + 8005e28: 2302 movs r3, #2 + 8005e2a: f887 302e strb.w r3, [r7, #46] ; 0x2e + uint32_t max_distance = 0; + 8005e2e: 2300 movs r3, #0 + 8005e30: 62bb str r3, [r7, #40] ; 0x28 + uint8_t devices_enlisted_cntr = 0; + 8005e32: 2300 movs r3, #0 + 8005e34: f887 3027 strb.w r3, [r7, #39] ; 0x27 + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8005e38: 2301 movs r3, #1 + 8005e3a: f887 3026 strb.w r3, [r7, #38] ; 0x26 + 8005e3e: e168 b.n 8006112 + { + if (dev != device_number) + 8005e40: 4b3d ldr r3, [pc, #244] ; (8005f38 ) + 8005e42: 781b ldrb r3, [r3, #0] + 8005e44: f897 2026 ldrb.w r2, [r7, #38] ; 0x26 + 8005e48: 429a cmp r2, r3 + 8005e4a: f000 815d beq.w 8006108 + { + if (pp_dev_aux[dev]->exist_flag == 1) + 8005e4e: 4b3d ldr r3, [pc, #244] ; (8005f44 ) + 8005e50: 681a ldr r2, [r3, #0] + 8005e52: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005e56: 009b lsls r3, r3, #2 + 8005e58: 4413 add r3, r2 + 8005e5a: 681b ldr r3, [r3, #0] + 8005e5c: 781b ldrb r3, [r3, #0] + 8005e5e: 2b01 cmp r3, #1 + 8005e60: f040 814d bne.w 80060fe + { + radar_list[dev] = devices_enlisted_cntr++; //first existing device will get index 0 + 8005e64: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8005e68: 1c5a adds r2, r3, #1 + 8005e6a: f887 2027 strb.w r2, [r7, #39] ; 0x27 + 8005e6e: f897 2026 ldrb.w r2, [r7, #38] ; 0x26 + 8005e72: 4937 ldr r1, [pc, #220] ; (8005f50 ) + 8005e74: 548b strb r3, [r1, r2] + + if (current_radar_device == 0) //if for the first time + 8005e76: 4b37 ldr r3, [pc, #220] ; (8005f54 ) + 8005e78: 781b ldrb r3, [r3, #0] + 8005e7a: 2b00 cmp r3, #0 + 8005e7c: d103 bne.n 8005e86 + { + current_radar_device = dev; + 8005e7e: 4a35 ldr r2, [pc, #212] ; (8005f54 ) + 8005e80: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005e84: 7013 strb r3, [r2, #0] + } + + //Number + itoa32(dev, &buf[0]); + 8005e86: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005e8a: 4930 ldr r1, [pc, #192] ; (8005f4c ) + 8005e8c: 4618 mov r0, r3 + 8005e8e: f002 fcc3 bl 8008818 + if (radar_list_hide[dev] == 1) + 8005e92: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005e96: 4a30 ldr r2, [pc, #192] ; (8005f58 ) + 8005e98: 5cd3 ldrb r3, [r2, r3] + 8005e9a: 2b01 cmp r3, #1 + 8005e9c: d107 bne.n 8005eae + { + ssd1306_print(another_radar_dev_row, 9, &buf[0], 1); + 8005e9e: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 8005ea2: 2301 movs r3, #1 + 8005ea4: 4a29 ldr r2, [pc, #164] ; (8005f4c ) + 8005ea6: 2109 movs r1, #9 + 8005ea8: f003 fa19 bl 80092de + 8005eac: e006 b.n 8005ebc + } + else + { + ssd1306_print(another_radar_dev_row, 9, &buf[0], 0); + 8005eae: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 8005eb2: 2300 movs r3, #0 + 8005eb4: 4a25 ldr r2, [pc, #148] ; (8005f4c ) + 8005eb6: 2109 movs r1, #9 + 8005eb8: f003 fa11 bl 80092de + } + + //ID + ssd1306_char_pos(another_radar_dev_row, 11, pp_gps_air[dev]->device_id[0], 0); + 8005ebc: 4b22 ldr r3, [pc, #136] ; (8005f48 ) + 8005ebe: 681a ldr r2, [r3, #0] + 8005ec0: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005ec4: 009b lsls r3, r3, #2 + 8005ec6: 4413 add r3, r2 + 8005ec8: 681b ldr r3, [r3, #0] + 8005eca: 781a ldrb r2, [r3, #0] + 8005ecc: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 8005ed0: 2300 movs r3, #0 + 8005ed2: 210b movs r1, #11 + 8005ed4: f003 f9e4 bl 80092a0 + ssd1306_char_pos(another_radar_dev_row, 12, pp_gps_air[dev]->device_id[1], 0); + 8005ed8: 4b1b ldr r3, [pc, #108] ; (8005f48 ) + 8005eda: 681a ldr r2, [r3, #0] + 8005edc: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005ee0: 009b lsls r3, r3, #2 + 8005ee2: 4413 add r3, r2 + 8005ee4: 681b ldr r3, [r3, #0] + 8005ee6: 785a ldrb r2, [r3, #1] + 8005ee8: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 8005eec: 2300 movs r3, #0 + 8005eee: 210c movs r1, #12 + 8005ef0: f003 f9d6 bl 80092a0 + + //Distance + if (pp_gps_rel[dev]->distance < 1000) //1-999 m + 8005ef4: 4b19 ldr r3, [pc, #100] ; (8005f5c ) + 8005ef6: 681a ldr r2, [r3, #0] + 8005ef8: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005efc: 009b lsls r3, r3, #2 + 8005efe: 4413 add r3, r2 + 8005f00: 681b ldr r3, [r3, #0] + 8005f02: 681b ldr r3, [r3, #0] + 8005f04: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8005f08: d22a bcs.n 8005f60 + { + itoa32(pp_gps_rel[dev]->distance, &buf[0]); + 8005f0a: 4b14 ldr r3, [pc, #80] ; (8005f5c ) + 8005f0c: 681a ldr r2, [r3, #0] + 8005f0e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005f12: 009b lsls r3, r3, #2 + 8005f14: 4413 add r3, r2 + 8005f16: 681b ldr r3, [r3, #0] + 8005f18: 681b ldr r3, [r3, #0] + 8005f1a: 490c ldr r1, [pc, #48] ; (8005f4c ) + 8005f1c: 4618 mov r0, r3 + 8005f1e: f002 fc7b bl 8008818 + ssd1306_print_viceversa(another_radar_dev_row, 16, &buf[0], 0); + 8005f22: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 8005f26: 2300 movs r3, #0 + 8005f28: 4a08 ldr r2, [pc, #32] ; (8005f4c ) + 8005f2a: 2110 movs r1, #16 + 8005f2c: f003 f9fa bl 8009324 + 8005f30: e08e b.n 8006050 + 8005f32: bf00 nop + 8005f34: 0800dd44 .word 0x0800dd44 + 8005f38: 20000738 .word 0x20000738 + 8005f3c: 20000808 .word 0x20000808 + 8005f40: 20000614 .word 0x20000614 + 8005f44: 2000083c .word 0x2000083c + 8005f48: 20000804 .word 0x20000804 + 8005f4c: 20000810 .word 0x20000810 + 8005f50: 200007d8 .word 0x200007d8 + 8005f54: 20000121 .word 0x20000121 + 8005f58: 20000830 .word 0x20000830 + 8005f5c: 200007d0 .word 0x200007d0 + } + else if (pp_gps_rel[dev]->distance < 10000) //1.0-9.9 km + 8005f60: 4b9e ldr r3, [pc, #632] ; (80061dc ) + 8005f62: 681a ldr r2, [r3, #0] + 8005f64: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005f68: 009b lsls r3, r3, #2 + 8005f6a: 4413 add r3, r2 + 8005f6c: 681b ldr r3, [r3, #0] + 8005f6e: 681b ldr r3, [r3, #0] + 8005f70: f242 720f movw r2, #9999 ; 0x270f + 8005f74: 4293 cmp r3, r2 + 8005f76: d827 bhi.n 8005fc8 + { + tmpf = pp_gps_rel[dev]->distance / 1000.0; + 8005f78: 4b98 ldr r3, [pc, #608] ; (80061dc ) + 8005f7a: 681a ldr r2, [r3, #0] + 8005f7c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005f80: 009b lsls r3, r3, #2 + 8005f82: 4413 add r3, r2 + 8005f84: 681b ldr r3, [r3, #0] + 8005f86: 681b ldr r3, [r3, #0] + 8005f88: 4618 mov r0, r3 + 8005f8a: f7fa fa33 bl 80003f4 <__aeabi_ui2d> + 8005f8e: f04f 0200 mov.w r2, #0 + 8005f92: 4b93 ldr r3, [pc, #588] ; (80061e0 ) + 8005f94: f7fa fbd2 bl 800073c <__aeabi_ddiv> + 8005f98: 4603 mov r3, r0 + 8005f9a: 460c mov r4, r1 + 8005f9c: 4618 mov r0, r3 + 8005f9e: 4621 mov r1, r4 + 8005fa0: f7fa fd9a bl 8000ad8 <__aeabi_d2f> + 8005fa4: 4602 mov r2, r0 + 8005fa6: 4b8f ldr r3, [pc, #572] ; (80061e4 ) + 8005fa8: 601a str r2, [r3, #0] + ftoa32(tmpf, 1, &buf[0]); + 8005faa: 4b8e ldr r3, [pc, #568] ; (80061e4 ) + 8005fac: 681b ldr r3, [r3, #0] + 8005fae: 4a8e ldr r2, [pc, #568] ; (80061e8 ) + 8005fb0: 2101 movs r1, #1 + 8005fb2: 4618 mov r0, r3 + 8005fb4: f002 fae0 bl 8008578 + ssd1306_print_viceversa(another_radar_dev_row, 16, &buf[0], 0); + 8005fb8: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 8005fbc: 2300 movs r3, #0 + 8005fbe: 4a8a ldr r2, [pc, #552] ; (80061e8 ) + 8005fc0: 2110 movs r1, #16 + 8005fc2: f003 f9af bl 8009324 + 8005fc6: e043 b.n 8006050 + } + else if (pp_gps_rel[dev]->distance < 100000) //10.-99. km + 8005fc8: 4b84 ldr r3, [pc, #528] ; (80061dc ) + 8005fca: 681a ldr r2, [r3, #0] + 8005fcc: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005fd0: 009b lsls r3, r3, #2 + 8005fd2: 4413 add r3, r2 + 8005fd4: 681b ldr r3, [r3, #0] + 8005fd6: 681b ldr r3, [r3, #0] + 8005fd8: 4a84 ldr r2, [pc, #528] ; (80061ec ) + 8005fda: 4293 cmp r3, r2 + 8005fdc: d831 bhi.n 8006042 + { + tmpf = pp_gps_rel[dev]->distance / 1000.0; + 8005fde: 4b7f ldr r3, [pc, #508] ; (80061dc ) + 8005fe0: 681a ldr r2, [r3, #0] + 8005fe2: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8005fe6: 009b lsls r3, r3, #2 + 8005fe8: 4413 add r3, r2 + 8005fea: 681b ldr r3, [r3, #0] + 8005fec: 681b ldr r3, [r3, #0] + 8005fee: 4618 mov r0, r3 + 8005ff0: f7fa fa00 bl 80003f4 <__aeabi_ui2d> + 8005ff4: f04f 0200 mov.w r2, #0 + 8005ff8: 4b79 ldr r3, [pc, #484] ; (80061e0 ) + 8005ffa: f7fa fb9f bl 800073c <__aeabi_ddiv> + 8005ffe: 4603 mov r3, r0 + 8006000: 460c mov r4, r1 + 8006002: 4618 mov r0, r3 + 8006004: 4621 mov r1, r4 + 8006006: f7fa fd67 bl 8000ad8 <__aeabi_d2f> + 800600a: 4602 mov r2, r0 + 800600c: 4b75 ldr r3, [pc, #468] ; (80061e4 ) + 800600e: 601a str r2, [r3, #0] + itoa32((uint32_t)tmpf, &buf[0]); + 8006010: 4b74 ldr r3, [pc, #464] ; (80061e4 ) + 8006012: 681b ldr r3, [r3, #0] + 8006014: 4618 mov r0, r3 + 8006016: f7fb f8a9 bl 800116c <__aeabi_f2uiz> + 800601a: 4603 mov r3, r0 + 800601c: 4972 ldr r1, [pc, #456] ; (80061e8 ) + 800601e: 4618 mov r0, r3 + 8006020: f002 fbfa bl 8008818 + ssd1306_print_viceversa(another_radar_dev_row, 16, &buf[0], 0); + 8006024: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 8006028: 2300 movs r3, #0 + 800602a: 4a6f ldr r2, [pc, #444] ; (80061e8 ) + 800602c: 2110 movs r1, #16 + 800602e: f003 f979 bl 8009324 + ssd1306_char_pos(another_radar_dev_row, 17, '.', 0); + 8006032: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 8006036: 2300 movs r3, #0 + 8006038: 222e movs r2, #46 ; 0x2e + 800603a: 2111 movs r1, #17 + 800603c: f003 f930 bl 80092a0 + 8006040: e006 b.n 8006050 + } + else // >100 km + { + ssd1306_print(another_radar_dev_row, 14, "...", 0); + 8006042: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 8006046: 2300 movs r3, #0 + 8006048: 4a69 ldr r2, [pc, #420] ; (80061f0 ) + 800604a: 210e movs r1, #14 + 800604c: f003 f947 bl 80092de + } + + //Search max distance + if (pp_gps_rel[dev]->distance > max_distance) + 8006050: 4b62 ldr r3, [pc, #392] ; (80061dc ) + 8006052: 681a ldr r2, [r3, #0] + 8006054: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8006058: 009b lsls r3, r3, #2 + 800605a: 4413 add r3, r2 + 800605c: 681b ldr r3, [r3, #0] + 800605e: 681b ldr r3, [r3, #0] + 8006060: 6aba ldr r2, [r7, #40] ; 0x28 + 8006062: 429a cmp r2, r3 + 8006064: d20e bcs.n 8006084 + { + if (radar_list_hide[dev] == 0) + 8006066: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800606a: 4a62 ldr r2, [pc, #392] ; (80061f4 ) + 800606c: 5cd3 ldrb r3, [r2, r3] + 800606e: 2b00 cmp r3, #0 + 8006070: d108 bne.n 8006084 + { + max_distance = pp_gps_rel[dev]->distance; //fix max distance only if device is not hided + 8006072: 4b5a ldr r3, [pc, #360] ; (80061dc ) + 8006074: 681a ldr r2, [r3, #0] + 8006076: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800607a: 009b lsls r3, r3, #2 + 800607c: 4413 add r3, r2 + 800607e: 681b ldr r3, [r3, #0] + 8006080: 681b ldr r3, [r3, #0] + 8006082: 62bb str r3, [r7, #40] ; 0x28 + } + } + + //Heading + itoa32(pp_gps_rel[dev]->heading, &buf[0]); + 8006084: 4b55 ldr r3, [pc, #340] ; (80061dc ) + 8006086: 681a ldr r2, [r3, #0] + 8006088: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800608c: 009b lsls r3, r3, #2 + 800608e: 4413 add r3, r2 + 8006090: 681b ldr r3, [r3, #0] + 8006092: 889b ldrh r3, [r3, #4] + 8006094: 4954 ldr r1, [pc, #336] ; (80061e8 ) + 8006096: 4618 mov r0, r3 + 8006098: f002 fbbe bl 8008818 + ssd1306_print_viceversa(another_radar_dev_row, 20, &buf[0], 0); + 800609c: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 80060a0: 2300 movs r3, #0 + 80060a2: 4a51 ldr r2, [pc, #324] ; (80061e8 ) + 80060a4: 2114 movs r1, #20 + 80060a6: f003 f93d bl 8009324 + + + //Warning sign in case of timeout, alarm or fence + if (get_device_flags(dev, FLAGS_ALARM) || pp_dev_aux[dev]->timeout_flag || pp_dev_aux[dev]->fence_flag) + 80060aa: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 80060ae: 2104 movs r1, #4 + 80060b0: 4618 mov r0, r3 + 80060b2: f7fc fc03 bl 80028bc + 80060b6: 4603 mov r3, r0 + 80060b8: 2b00 cmp r3, #0 + 80060ba: d113 bne.n 80060e4 + 80060bc: 4b4e ldr r3, [pc, #312] ; (80061f8 ) + 80060be: 681a ldr r2, [r3, #0] + 80060c0: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 80060c4: 009b lsls r3, r3, #2 + 80060c6: 4413 add r3, r2 + 80060c8: 681b ldr r3, [r3, #0] + 80060ca: 7b1b ldrb r3, [r3, #12] + 80060cc: 2b00 cmp r3, #0 + 80060ce: d109 bne.n 80060e4 + 80060d0: 4b49 ldr r3, [pc, #292] ; (80061f8 ) + 80060d2: 681a ldr r2, [r3, #0] + 80060d4: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 80060d8: 009b lsls r3, r3, #2 + 80060da: 4413 add r3, r2 + 80060dc: 681b ldr r3, [r3, #0] + 80060de: 7b5b ldrb r3, [r3, #13] + 80060e0: 2b00 cmp r3, #0 + 80060e2: d006 beq.n 80060f2 + { + ssd1306_print_byte(another_radar_dev_row, 21, custom_exclam_mark, 2); + 80060e4: f897 002e ldrb.w r0, [r7, #46] ; 0x2e + 80060e8: 2302 movs r3, #2 + 80060ea: 4a44 ldr r2, [pc, #272] ; (80061fc ) + 80060ec: 2115 movs r1, #21 + 80060ee: f003 f989 bl 8009404 + } + + another_radar_dev_row++; + 80060f2: f897 302e ldrb.w r3, [r7, #46] ; 0x2e + 80060f6: 3301 adds r3, #1 + 80060f8: f887 302e strb.w r3, [r7, #46] ; 0x2e + 80060fc: e004 b.n 8006108 + } + else //if device is not exist + { + radar_list_hide[dev] = 0; //clear hide flag, so when device disappear, and appear again it will be not hided + 80060fe: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8006102: 4a3c ldr r2, [pc, #240] ; (80061f4 ) + 8006104: 2100 movs r1, #0 + 8006106: 54d1 strb r1, [r2, r3] + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8006108: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800610c: 3301 adds r3, #1 + 800610e: f887 3026 strb.w r3, [r7, #38] ; 0x26 + 8006112: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8006116: 2b06 cmp r3, #6 + 8006118: f67f ae92 bls.w 8005e40 + } + } + + + //Pointer and bottom row information bar + if (devices_enlisted_cntr > 0) + 800611c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8006120: 2b00 cmp r3, #0 + 8006122: f000 80e6 beq.w 80062f2 + { + ssd1306_print(2 + radar_list[current_radar_device], 8, ">", 0); + 8006126: 4b36 ldr r3, [pc, #216] ; (8006200 ) + 8006128: 781b ldrb r3, [r3, #0] + 800612a: 461a mov r2, r3 + 800612c: 4b35 ldr r3, [pc, #212] ; (8006204 ) + 800612e: 5c9b ldrb r3, [r3, r2] + 8006130: 3302 adds r3, #2 + 8006132: b2d8 uxtb r0, r3 + 8006134: 2300 movs r3, #0 + 8006136: 4a34 ldr r2, [pc, #208] ; (8006208 ) + 8006138: 2108 movs r1, #8 + 800613a: f003 f8d0 bl 80092de + + uint8_t icon_col = LCD_LAST_COL; + 800613e: 2314 movs r3, #20 + 8006140: f887 3025 strb.w r3, [r7, #37] ; 0x25 + + if (pp_dev_aux[current_radar_device]->memory_point_flag == 0) //dont show battery icon for memory points + 8006144: 4b2c ldr r3, [pc, #176] ; (80061f8 ) + 8006146: 681a ldr r2, [r3, #0] + 8006148: 4b2d ldr r3, [pc, #180] ; (8006200 ) + 800614a: 781b ldrb r3, [r3, #0] + 800614c: 009b lsls r3, r3, #2 + 800614e: 4413 add r3, r2 + 8006150: 681b ldr r3, [r3, #0] + 8006152: 7b9b ldrb r3, [r3, #14] + 8006154: 2b00 cmp r3, #0 + 8006156: d164 bne.n 8006222 + { + //Battery + switch (get_device_flags(current_radar_device, FLAGS_BATTERY)) + 8006158: 4b29 ldr r3, [pc, #164] ; (8006200 ) + 800615a: 781b ldrb r3, [r3, #0] + 800615c: 2101 movs r1, #1 + 800615e: 4618 mov r0, r3 + 8006160: f7fc fbac bl 80028bc + 8006164: 4603 mov r3, r0 + 8006166: 2b04 cmp r3, #4 + 8006168: d85b bhi.n 8006222 + 800616a: a201 add r2, pc, #4 ; (adr r2, 8006170 ) + 800616c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8006170: 0800620d .word 0x0800620d + 8006174: 080061c7 .word 0x080061c7 + 8006178: 080061b1 .word 0x080061b1 + 800617c: 0800619b .word 0x0800619b + 8006180: 08006185 .word 0x08006185 + { + case FLAG_BATTERY_75_TO_100: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_4OF4, 0); + 8006184: f897 1025 ldrb.w r1, [r7, #37] ; 0x25 + 8006188: 1e4b subs r3, r1, #1 + 800618a: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 800618e: 2300 movs r3, #0 + 8006190: 228c movs r2, #140 ; 0x8c + 8006192: 2007 movs r0, #7 + 8006194: f003 f884 bl 80092a0 + break; + 8006198: e043 b.n 8006222 + + case FLAG_BATTERY_50_TO_75: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_3OF4, 0); + 800619a: f897 1025 ldrb.w r1, [r7, #37] ; 0x25 + 800619e: 1e4b subs r3, r1, #1 + 80061a0: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 80061a4: 2300 movs r3, #0 + 80061a6: 228b movs r2, #139 ; 0x8b + 80061a8: 2007 movs r0, #7 + 80061aa: f003 f879 bl 80092a0 + break; + 80061ae: e038 b.n 8006222 + + case FLAG_BATTERY_25_TO_50: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_2OF4, 0); + 80061b0: f897 1025 ldrb.w r1, [r7, #37] ; 0x25 + 80061b4: 1e4b subs r3, r1, #1 + 80061b6: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 80061ba: 2300 movs r3, #0 + 80061bc: 228a movs r2, #138 ; 0x8a + 80061be: 2007 movs r0, #7 + 80061c0: f003 f86e bl 80092a0 + break; + 80061c4: e02d b.n 8006222 + + case FLAG_BATTERY_10_TO_25: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_1OF4, 0); + 80061c6: f897 1025 ldrb.w r1, [r7, #37] ; 0x25 + 80061ca: 1e4b subs r3, r1, #1 + 80061cc: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 80061d0: 2300 movs r3, #0 + 80061d2: 2289 movs r2, #137 ; 0x89 + 80061d4: 2007 movs r0, #7 + 80061d6: f003 f863 bl 80092a0 + break; + 80061da: e022 b.n 8006222 + 80061dc: 200007d0 .word 0x200007d0 + 80061e0: 408f4000 .word 0x408f4000 + 80061e4: 200007f4 .word 0x200007f4 + 80061e8: 20000810 .word 0x20000810 + 80061ec: 0001869f .word 0x0001869f + 80061f0: 0800ca18 .word 0x0800ca18 + 80061f4: 20000830 .word 0x20000830 + 80061f8: 2000083c .word 0x2000083c + 80061fc: 20000034 .word 0x20000034 + 8006200: 20000121 .word 0x20000121 + 8006204: 200007d8 .word 0x200007d8 + 8006208: 0800ca14 .word 0x0800ca14 + + case FLAG_BATTERY_0_TO_10: + ssd1306_char_pos(7, icon_col--, SYMB_BAT_0OF4, 0); + 800620c: f897 1025 ldrb.w r1, [r7, #37] ; 0x25 + 8006210: 1e4b subs r3, r1, #1 + 8006212: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 8006216: 2300 movs r3, #0 + 8006218: 2288 movs r2, #136 ; 0x88 + 800621a: 2007 movs r0, #7 + 800621c: f003 f840 bl 80092a0 + break; + 8006220: bf00 nop + } + } + + + if (pp_dev_aux[current_radar_device]->memory_point_flag == 0) + 8006222: 4b71 ldr r3, [pc, #452] ; (80063e8 ) + 8006224: 681a ldr r2, [r3, #0] + 8006226: 4b71 ldr r3, [pc, #452] ; (80063ec ) + 8006228: 781b ldrb r3, [r3, #0] + 800622a: 009b lsls r3, r3, #2 + 800622c: 4413 add r3, r2 + 800622e: 681b ldr r3, [r3, #0] + 8006230: 7b9b ldrb r3, [r3, #14] + 8006232: 2b00 cmp r3, #0 + 8006234: d113 bne.n 800625e + { + //Timeout + if (pp_dev_aux[current_radar_device]->timeout_flag) + 8006236: 4b6c ldr r3, [pc, #432] ; (80063e8 ) + 8006238: 681a ldr r2, [r3, #0] + 800623a: 4b6c ldr r3, [pc, #432] ; (80063ec ) + 800623c: 781b ldrb r3, [r3, #0] + 800623e: 009b lsls r3, r3, #2 + 8006240: 4413 add r3, r2 + 8006242: 681b ldr r3, [r3, #0] + 8006244: 7b1b ldrb r3, [r3, #12] + 8006246: 2b00 cmp r3, #0 + 8006248: d009 beq.n 800625e + { + ssd1306_char_pos(7, icon_col--, SYMB_TIMEOUT, 0); + 800624a: f897 1025 ldrb.w r1, [r7, #37] ; 0x25 + 800624e: 1e4b subs r3, r1, #1 + 8006250: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 8006254: 2300 movs r3, #0 + 8006256: 2286 movs r2, #134 ; 0x86 + 8006258: 2007 movs r0, #7 + 800625a: f003 f821 bl 80092a0 + } + } + + + //Fence + if (pp_dev_aux[current_radar_device]->fence_flag) + 800625e: 4b62 ldr r3, [pc, #392] ; (80063e8 ) + 8006260: 681a ldr r2, [r3, #0] + 8006262: 4b62 ldr r3, [pc, #392] ; (80063ec ) + 8006264: 781b ldrb r3, [r3, #0] + 8006266: 009b lsls r3, r3, #2 + 8006268: 4413 add r3, r2 + 800626a: 681b ldr r3, [r3, #0] + 800626c: 7b5b ldrb r3, [r3, #13] + 800626e: 2b00 cmp r3, #0 + 8006270: d009 beq.n 8006286 + { + ssd1306_char_pos(7, icon_col--, SYMB_FENCE, 0); + 8006272: f897 1025 ldrb.w r1, [r7, #37] ; 0x25 + 8006276: 1e4b subs r3, r1, #1 + 8006278: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 800627c: 2300 movs r3, #0 + 800627e: 228e movs r2, #142 ; 0x8e + 8006280: 2007 movs r0, #7 + 8006282: f003 f80d bl 80092a0 + } + + + if (pp_dev_aux[current_radar_device]->memory_point_flag == 0) + 8006286: 4b58 ldr r3, [pc, #352] ; (80063e8 ) + 8006288: 681a ldr r2, [r3, #0] + 800628a: 4b58 ldr r3, [pc, #352] ; (80063ec ) + 800628c: 781b ldrb r3, [r3, #0] + 800628e: 009b lsls r3, r3, #2 + 8006290: 4413 add r3, r2 + 8006292: 681b ldr r3, [r3, #0] + 8006294: 7b9b ldrb r3, [r3, #14] + 8006296: 2b00 cmp r3, #0 + 8006298: d112 bne.n 80062c0 + { + //Alarm + if (get_device_flags(current_radar_device, FLAGS_ALARM) == FLAG_ALARM_ON) + 800629a: 4b54 ldr r3, [pc, #336] ; (80063ec ) + 800629c: 781b ldrb r3, [r3, #0] + 800629e: 2104 movs r1, #4 + 80062a0: 4618 mov r0, r3 + 80062a2: f7fc fb0b bl 80028bc + 80062a6: 4603 mov r3, r0 + 80062a8: 2b01 cmp r3, #1 + 80062aa: d109 bne.n 80062c0 + { + ssd1306_char_pos(7, icon_col--, SYMB_ALARM, 0); + 80062ac: f897 1025 ldrb.w r1, [r7, #37] ; 0x25 + 80062b0: 1e4b subs r3, r1, #1 + 80062b2: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 80062b6: 2300 movs r3, #0 + 80062b8: 2287 movs r2, #135 ; 0x87 + 80062ba: 2007 movs r0, #7 + 80062bc: f002 fff0 bl 80092a0 + } + } + + + //if mem point then print it name + if (pp_dev_aux[current_radar_device]->memory_point_flag == 1) + 80062c0: 4b49 ldr r3, [pc, #292] ; (80063e8 ) + 80062c2: 681a ldr r2, [r3, #0] + 80062c4: 4b49 ldr r3, [pc, #292] ; (80063ec ) + 80062c6: 781b ldrb r3, [r3, #0] + 80062c8: 009b lsls r3, r3, #2 + 80062ca: 4413 add r3, r2 + 80062cc: 681b ldr r3, [r3, #0] + 80062ce: 7b9b ldrb r3, [r3, #14] + 80062d0: 2b01 cmp r3, #1 + 80062d2: d111 bne.n 80062f8 + { + ssd1306_print(7, 9, pp_dev_aux[current_radar_device]->point_name, 0); + 80062d4: 4b44 ldr r3, [pc, #272] ; (80063e8 ) + 80062d6: 681a ldr r2, [r3, #0] + 80062d8: 4b44 ldr r3, [pc, #272] ; (80063ec ) + 80062da: 781b ldrb r3, [r3, #0] + 80062dc: 009b lsls r3, r3, #2 + 80062de: 4413 add r3, r2 + 80062e0: 681b ldr r3, [r3, #0] + 80062e2: f103 020f add.w r2, r3, #15 + 80062e6: 2300 movs r3, #0 + 80062e8: 2109 movs r1, #9 + 80062ea: 2007 movs r0, #7 + 80062ec: f002 fff7 bl 80092de + 80062f0: e002 b.n 80062f8 + + + } + else + { + current_radar_device = 0; + 80062f2: 4b3e ldr r3, [pc, #248] ; (80063ec ) + 80062f4: 2200 movs r2, #0 + 80062f6: 701a strb r2, [r3, #0] + } + + + //Radar implementation is here + float mpd_ratio_f = 0.0; //meters per dot ratio + 80062f8: f04f 0300 mov.w r3, #0 + 80062fc: 61bb str r3, [r7, #24] + uint32_t mpd_ratio_i = 0; + 80062fe: 2300 movs r3, #0 + 8006300: 623b str r3, [r7, #32] + + if (max_distance < r_circ_dots) + 8006302: 2314 movs r3, #20 + 8006304: 461a mov r2, r3 + 8006306: 6abb ldr r3, [r7, #40] ; 0x28 + 8006308: 4293 cmp r3, r2 + 800630a: d201 bcs.n 8006310 + { + max_distance = r_circ_dots; + 800630c: 2314 movs r3, #20 + 800630e: 62bb str r3, [r7, #40] ; 0x28 + } + + mpd_ratio_f = (float)max_distance / (float)r_circ_dots; //calc ratio + 8006310: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8006312: f7fa fce7 bl 8000ce4 <__aeabi_ui2f> + 8006316: 4604 mov r4, r0 + 8006318: 2314 movs r3, #20 + 800631a: 4618 mov r0, r3 + 800631c: f7fa fce2 bl 8000ce4 <__aeabi_ui2f> + 8006320: 4603 mov r3, r0 + 8006322: 4619 mov r1, r3 + 8006324: 4620 mov r0, r4 + 8006326: f7fa fde9 bl 8000efc <__aeabi_fdiv> + 800632a: 4603 mov r3, r0 + 800632c: 61bb str r3, [r7, #24] + mpd_ratio_i = (uint32_t)mpd_ratio_f; //extract int part + 800632e: 69b8 ldr r0, [r7, #24] + 8006330: f7fa ff1c bl 800116c <__aeabi_f2uiz> + 8006334: 4603 mov r3, r0 + 8006336: 623b str r3, [r7, #32] + + mpd_ratio_f -= mpd_ratio_i; //extract frac part + 8006338: 6a38 ldr r0, [r7, #32] + 800633a: f7fa fcd3 bl 8000ce4 <__aeabi_ui2f> + 800633e: 4603 mov r3, r0 + 8006340: 4619 mov r1, r3 + 8006342: 69b8 ldr r0, [r7, #24] + 8006344: f7fa fc1c bl 8000b80 <__aeabi_fsub> + 8006348: 4603 mov r3, r0 + 800634a: 61bb str r3, [r7, #24] + + if (mpd_ratio_f > 0.001) //if frac part is non-zero, then inc ratio + 800634c: 69b8 ldr r0, [r7, #24] + 800634e: f7fa f873 bl 8000438 <__aeabi_f2d> + 8006352: a323 add r3, pc, #140 ; (adr r3, 80063e0 ) + 8006354: e9d3 2300 ldrd r2, r3, [r3] + 8006358: f7fa fb56 bl 8000a08 <__aeabi_dcmpgt> + 800635c: 4603 mov r3, r0 + 800635e: 2b00 cmp r3, #0 + 8006360: d002 beq.n 8006368 + { + mpd_ratio_i++; + 8006362: 6a3b ldr r3, [r7, #32] + 8006364: 3301 adds r3, #1 + 8006366: 623b str r3, [r7, #32] + } + + //print radar range + uint32_t radar_range = mpd_ratio_i * r_circ_dots; //i.e. radar screen radius + 8006368: 2314 movs r3, #20 + 800636a: 461a mov r2, r3 + 800636c: 6a3b ldr r3, [r7, #32] + 800636e: fb02 f303 mul.w r3, r2, r3 + 8006372: 617b str r3, [r7, #20] + + if (radar_range < 10000) // 0...9999 meters, screen fits 4 characters max + 8006374: 697b ldr r3, [r7, #20] + 8006376: f242 720f movw r2, #9999 ; 0x270f + 800637a: 4293 cmp r3, r2 + 800637c: d80b bhi.n 8006396 + { + itoa32(radar_range, &buf[0]); + 800637e: 697b ldr r3, [r7, #20] + 8006380: 491b ldr r1, [pc, #108] ; (80063f0 ) + 8006382: 4618 mov r0, r3 + 8006384: f002 fa48 bl 8008818 + ssd1306_print_viceversa(7, 7, &buf[0], 0); + 8006388: 2300 movs r3, #0 + 800638a: 4a19 ldr r2, [pc, #100] ; (80063f0 ) + 800638c: 2107 movs r1, #7 + 800638e: 2007 movs r0, #7 + 8006390: f002 ffc8 bl 8009324 + 8006394: e01f b.n 80063d6 + } + else if (radar_range < 1000000) // 10000...999999 meters + 8006396: 697b ldr r3, [r7, #20] + 8006398: 4a16 ldr r2, [pc, #88] ; (80063f4 ) + 800639a: 4293 cmp r3, r2 + 800639c: d815 bhi.n 80063ca + { + itoa32((radar_range / 1000), &buf[0]); + 800639e: 697b ldr r3, [r7, #20] + 80063a0: 4a15 ldr r2, [pc, #84] ; (80063f8 ) + 80063a2: fba2 2303 umull r2, r3, r2, r3 + 80063a6: 099b lsrs r3, r3, #6 + 80063a8: 4911 ldr r1, [pc, #68] ; (80063f0 ) + 80063aa: 4618 mov r0, r3 + 80063ac: f002 fa34 bl 8008818 + ssd1306_char_pos(7, 7, 'k', 0); + 80063b0: 2300 movs r3, #0 + 80063b2: 226b movs r2, #107 ; 0x6b + 80063b4: 2107 movs r1, #7 + 80063b6: 2007 movs r0, #7 + 80063b8: f002 ff72 bl 80092a0 + ssd1306_print_viceversa(7, 6, &buf[0], 0); + 80063bc: 2300 movs r3, #0 + 80063be: 4a0c ldr r2, [pc, #48] ; (80063f0 ) + 80063c0: 2106 movs r1, #6 + 80063c2: 2007 movs r0, #7 + 80063c4: f002 ffae bl 8009324 + 80063c8: e005 b.n 80063d6 + } + else + { + ssd1306_print_viceversa(7, 7, "...", 0); + 80063ca: 2300 movs r3, #0 + 80063cc: 4a0b ldr r2, [pc, #44] ; (80063fc ) + 80063ce: 2107 movs r1, #7 + 80063d0: 2007 movs r0, #7 + 80063d2: f002 ffa7 bl 8009324 + } + + + + //plot on radar + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 80063d6: 2301 movs r3, #1 + 80063d8: 77fb strb r3, [r7, #31] + 80063da: e0f6 b.n 80065ca + 80063dc: f3af 8000 nop.w + 80063e0: d2f1a9fc .word 0xd2f1a9fc + 80063e4: 3f50624d .word 0x3f50624d + 80063e8: 2000083c .word 0x2000083c + 80063ec: 20000121 .word 0x20000121 + 80063f0: 20000810 .word 0x20000810 + 80063f4: 000f423f .word 0x000f423f + 80063f8: 10624dd3 .word 0x10624dd3 + 80063fc: 0800ca18 .word 0x0800ca18 + { + if (dev != device_number) + 8006400: 4b77 ldr r3, [pc, #476] ; (80065e0 ) + 8006402: 781b ldrb r3, [r3, #0] + 8006404: 7ffa ldrb r2, [r7, #31] + 8006406: 429a cmp r2, r3 + 8006408: f000 80dc beq.w 80065c4 + { + if (pp_dev_aux[dev]->exist_flag == 1) + 800640c: 4b75 ldr r3, [pc, #468] ; (80065e4 ) + 800640e: 681a ldr r2, [r3, #0] + 8006410: 7ffb ldrb r3, [r7, #31] + 8006412: 009b lsls r3, r3, #2 + 8006414: 4413 add r3, r2 + 8006416: 681b ldr r3, [r3, #0] + 8006418: 781b ldrb r3, [r3, #0] + 800641a: 2b01 cmp r3, #1 + 800641c: f040 80d2 bne.w 80065c4 + { + if (radar_list_hide[dev] == 0) //if not hided + 8006420: 7ffb ldrb r3, [r7, #31] + 8006422: 4a71 ldr r2, [pc, #452] ; (80065e8 ) + 8006424: 5cd3 ldrb r3, [r2, r3] + 8006426: 2b00 cmp r3, #0 + 8006428: f040 80cc bne.w 80065c4 + { + uint8_t sx1 = 0; //device coordinates on the screen + 800642c: 2300 movs r3, #0 + 800642e: 74fb strb r3, [r7, #19] + uint8_t sy1 = 0; + 8006430: 2300 movs r3, #0 + 8006432: 74bb strb r3, [r7, #18] + + double x1 = 0.0; //device coordinates relative from my position (0, 0) + 8006434: f04f 0300 mov.w r3, #0 + 8006438: f04f 0400 mov.w r4, #0 + 800643c: e9c7 3402 strd r3, r4, [r7, #8] + double y1 = 0.0; + 8006440: f04f 0300 mov.w r3, #0 + 8006444: f04f 0400 mov.w r4, #0 + 8006448: e9c7 3400 strd r3, r4, [r7] + + x1 = -((pp_gps_rel[dev]->distance)/(double)mpd_ratio_i) * cos((pp_gps_rel[dev]->heading + 90) * deg_to_rad); + 800644c: 4b67 ldr r3, [pc, #412] ; (80065ec ) + 800644e: 681a ldr r2, [r3, #0] + 8006450: 7ffb ldrb r3, [r7, #31] + 8006452: 009b lsls r3, r3, #2 + 8006454: 4413 add r3, r2 + 8006456: 681b ldr r3, [r3, #0] + 8006458: 681b ldr r3, [r3, #0] + 800645a: 4618 mov r0, r3 + 800645c: f7f9 ffca bl 80003f4 <__aeabi_ui2d> + 8006460: 4680 mov r8, r0 + 8006462: 4689 mov r9, r1 + 8006464: 6a38 ldr r0, [r7, #32] + 8006466: f7f9 ffc5 bl 80003f4 <__aeabi_ui2d> + 800646a: 4603 mov r3, r0 + 800646c: 460c mov r4, r1 + 800646e: 461a mov r2, r3 + 8006470: 4623 mov r3, r4 + 8006472: 4640 mov r0, r8 + 8006474: 4649 mov r1, r9 + 8006476: f7fa f961 bl 800073c <__aeabi_ddiv> + 800647a: 4603 mov r3, r0 + 800647c: 460c mov r4, r1 + 800647e: 461d mov r5, r3 + 8006480: f084 4600 eor.w r6, r4, #2147483648 ; 0x80000000 + 8006484: 4b59 ldr r3, [pc, #356] ; (80065ec ) + 8006486: 681a ldr r2, [r3, #0] + 8006488: 7ffb ldrb r3, [r7, #31] + 800648a: 009b lsls r3, r3, #2 + 800648c: 4413 add r3, r2 + 800648e: 681b ldr r3, [r3, #0] + 8006490: 889b ldrh r3, [r3, #4] + 8006492: 335a adds r3, #90 ; 0x5a + 8006494: 4618 mov r0, r3 + 8006496: f7f9 ffbd bl 8000414 <__aeabi_i2d> + 800649a: 4b55 ldr r3, [pc, #340] ; (80065f0 ) + 800649c: cb18 ldmia r3, {r3, r4} + 800649e: 461a mov r2, r3 + 80064a0: 4623 mov r3, r4 + 80064a2: f7fa f821 bl 80004e8 <__aeabi_dmul> + 80064a6: 4603 mov r3, r0 + 80064a8: 460c mov r4, r1 + 80064aa: 4618 mov r0, r3 + 80064ac: 4621 mov r1, r4 + 80064ae: f003 fbf1 bl 8009c94 + 80064b2: 4603 mov r3, r0 + 80064b4: 460c mov r4, r1 + 80064b6: 461a mov r2, r3 + 80064b8: 4623 mov r3, r4 + 80064ba: 4628 mov r0, r5 + 80064bc: 4631 mov r1, r6 + 80064be: f7fa f813 bl 80004e8 <__aeabi_dmul> + 80064c2: 4603 mov r3, r0 + 80064c4: 460c mov r4, r1 + 80064c6: e9c7 3402 strd r3, r4, [r7, #8] + y1 = ((pp_gps_rel[dev]->distance)/(double)mpd_ratio_i) * sin((pp_gps_rel[dev]->heading + 90) * deg_to_rad); + 80064ca: 4b48 ldr r3, [pc, #288] ; (80065ec ) + 80064cc: 681a ldr r2, [r3, #0] + 80064ce: 7ffb ldrb r3, [r7, #31] + 80064d0: 009b lsls r3, r3, #2 + 80064d2: 4413 add r3, r2 + 80064d4: 681b ldr r3, [r3, #0] + 80064d6: 681b ldr r3, [r3, #0] + 80064d8: 4618 mov r0, r3 + 80064da: f7f9 ff8b bl 80003f4 <__aeabi_ui2d> + 80064de: 4680 mov r8, r0 + 80064e0: 4689 mov r9, r1 + 80064e2: 6a38 ldr r0, [r7, #32] + 80064e4: f7f9 ff86 bl 80003f4 <__aeabi_ui2d> + 80064e8: 4603 mov r3, r0 + 80064ea: 460c mov r4, r1 + 80064ec: 461a mov r2, r3 + 80064ee: 4623 mov r3, r4 + 80064f0: 4640 mov r0, r8 + 80064f2: 4649 mov r1, r9 + 80064f4: f7fa f922 bl 800073c <__aeabi_ddiv> + 80064f8: 4603 mov r3, r0 + 80064fa: 460c mov r4, r1 + 80064fc: 4698 mov r8, r3 + 80064fe: 46a1 mov r9, r4 + 8006500: 4b3a ldr r3, [pc, #232] ; (80065ec ) + 8006502: 681a ldr r2, [r3, #0] + 8006504: 7ffb ldrb r3, [r7, #31] + 8006506: 009b lsls r3, r3, #2 + 8006508: 4413 add r3, r2 + 800650a: 681b ldr r3, [r3, #0] + 800650c: 889b ldrh r3, [r3, #4] + 800650e: 335a adds r3, #90 ; 0x5a + 8006510: 4618 mov r0, r3 + 8006512: f7f9 ff7f bl 8000414 <__aeabi_i2d> + 8006516: 4b36 ldr r3, [pc, #216] ; (80065f0 ) + 8006518: cb18 ldmia r3, {r3, r4} + 800651a: 461a mov r2, r3 + 800651c: 4623 mov r3, r4 + 800651e: f7f9 ffe3 bl 80004e8 <__aeabi_dmul> + 8006522: 4603 mov r3, r0 + 8006524: 460c mov r4, r1 + 8006526: 4618 mov r0, r3 + 8006528: 4621 mov r1, r4 + 800652a: f003 fbed bl 8009d08 + 800652e: 4603 mov r3, r0 + 8006530: 460c mov r4, r1 + 8006532: 461a mov r2, r3 + 8006534: 4623 mov r3, r4 + 8006536: 4640 mov r0, r8 + 8006538: 4649 mov r1, r9 + 800653a: f7f9 ffd5 bl 80004e8 <__aeabi_dmul> + 800653e: 4603 mov r3, r0 + 8006540: 460c mov r4, r1 + 8006542: e9c7 3400 strd r3, r4, [r7] + + sx1 = sx0 + (int8_t)x1; + 8006546: e9d7 0102 ldrd r0, r1, [r7, #8] + 800654a: f7fa fa7d bl 8000a48 <__aeabi_d2iz> + 800654e: 4603 mov r3, r0 + 8006550: b25b sxtb r3, r3 + 8006552: b2db uxtb r3, r3 + 8006554: 2218 movs r2, #24 + 8006556: 4413 add r3, r2 + 8006558: 74fb strb r3, [r7, #19] + sy1 = sy0 - (int8_t)y1; //note: Y axis is inverted (counts from top to the bottom) + 800655a: 241f movs r4, #31 + 800655c: e9d7 0100 ldrd r0, r1, [r7] + 8006560: f7fa fa72 bl 8000a48 <__aeabi_d2iz> + 8006564: 4603 mov r3, r0 + 8006566: b25b sxtb r3, r3 + 8006568: b2db uxtb r3, r3 + 800656a: 1ae3 subs r3, r4, r3 + 800656c: 74bb strb r3, [r7, #18] + + + ssd1306_pixel(sx1, sy1+1, 1); //pixel cross + 800656e: 7cbb ldrb r3, [r7, #18] + 8006570: 3301 adds r3, #1 + 8006572: b2d9 uxtb r1, r3 + 8006574: 7cfb ldrb r3, [r7, #19] + 8006576: 2201 movs r2, #1 + 8006578: 4618 mov r0, r3 + 800657a: f002 fdc1 bl 8009100 + ssd1306_pixel(sx1+1, sy1, 1); + 800657e: 7cfb ldrb r3, [r7, #19] + 8006580: 3301 adds r3, #1 + 8006582: b2db uxtb r3, r3 + 8006584: 7cb9 ldrb r1, [r7, #18] + 8006586: 2201 movs r2, #1 + 8006588: 4618 mov r0, r3 + 800658a: f002 fdb9 bl 8009100 + ssd1306_pixel(sx1, sy1-1, 1); + 800658e: 7cbb ldrb r3, [r7, #18] + 8006590: 3b01 subs r3, #1 + 8006592: b2d9 uxtb r1, r3 + 8006594: 7cfb ldrb r3, [r7, #19] + 8006596: 2201 movs r2, #1 + 8006598: 4618 mov r0, r3 + 800659a: f002 fdb1 bl 8009100 + ssd1306_pixel(sx1-1, sy1, 1); + 800659e: 7cfb ldrb r3, [r7, #19] + 80065a0: 3b01 subs r3, #1 + 80065a2: b2db uxtb r3, r3 + 80065a4: 7cb9 ldrb r1, [r7, #18] + 80065a6: 2201 movs r2, #1 + 80065a8: 4618 mov r0, r3 + 80065aa: f002 fda9 bl 8009100 + + //center pixel if device is selected + if (dev == current_radar_device) + 80065ae: 4b11 ldr r3, [pc, #68] ; (80065f4 ) + 80065b0: 781b ldrb r3, [r3, #0] + 80065b2: 7ffa ldrb r2, [r7, #31] + 80065b4: 429a cmp r2, r3 + 80065b6: d105 bne.n 80065c4 + { + ssd1306_pixel(sx1, sy1, 1); + 80065b8: 7cb9 ldrb r1, [r7, #18] + 80065ba: 7cfb ldrb r3, [r7, #19] + 80065bc: 2201 movs r2, #1 + 80065be: 4618 mov r0, r3 + 80065c0: f002 fd9e bl 8009100 + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 80065c4: 7ffb ldrb r3, [r7, #31] + 80065c6: 3301 adds r3, #1 + 80065c8: 77fb strb r3, [r7, #31] + 80065ca: 7ffb ldrb r3, [r7, #31] + 80065cc: 2b06 cmp r3, #6 + 80065ce: f67f af17 bls.w 8006400 + } + } + } + } + + ssd1306_update(); + 80065d2: f002 fd5d bl 8009090 +} + 80065d6: bf00 nop + 80065d8: 3734 adds r7, #52 ; 0x34 + 80065da: 46bd mov sp, r7 + 80065dc: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 80065e0: 20000738 .word 0x20000738 + 80065e4: 2000083c .word 0x2000083c + 80065e8: 20000830 .word 0x20000830 + 80065ec: 200007d0 .word 0x200007d0 + 80065f0: 0800cf40 .word 0x0800cf40 + 80065f4: 20000121 .word 0x20000121 + +080065f8 : + + + +//POINTS +void draw_points(void) +{ + 80065f8: b580 push {r7, lr} + 80065fa: b082 sub sp, #8 + 80065fc: af00 add r7, sp, #0 + + save_memory_point(1, "TEST1", 1); + +#endif + + read_memory_slots(); + 80065fe: f001 fb7d bl 8007cfc + + ssd1306_clear(); + 8006602: f002 fd65 bl 80090d0 + ssd1306_print(0, POINTS_COL, "POINTS", 0); + 8006606: 2300 movs r3, #0 + 8006608: 4a57 ldr r2, [pc, #348] ; (8006768 ) + 800660a: 2101 movs r1, #1 + 800660c: 2000 movs r0, #0 + 800660e: f002 fe66 bl 80092de + + for (uint8_t s = 1; s <= MEMORY_SLOTS_TOTAL; s++) + 8006612: 2301 movs r3, #1 + 8006614: 71fb strb r3, [r7, #7] + 8006616: e094 b.n 8006742 + { + ssd1306_print(POINTS_ROW + s - 1, POINTS_COL, pp_memory_slot[s]->slot_name, 0); //print slot name + 8006618: 79fb ldrb r3, [r7, #7] + 800661a: 3301 adds r3, #1 + 800661c: b2d8 uxtb r0, r3 + 800661e: 4b53 ldr r3, [pc, #332] ; (800676c ) + 8006620: 681a ldr r2, [r3, #0] + 8006622: 79fb ldrb r3, [r7, #7] + 8006624: 009b lsls r3, r3, #2 + 8006626: 4413 add r3, r2 + 8006628: 681b ldr r3, [r3, #0] + 800662a: 1c5a adds r2, r3, #1 + 800662c: 2300 movs r3, #0 + 800662e: 2101 movs r1, #1 + 8006630: f002 fe55 bl 80092de + + if (pp_memory_slot[s]->exist_flag == 1) + 8006634: 4b4d ldr r3, [pc, #308] ; (800676c ) + 8006636: 681a ldr r2, [r3, #0] + 8006638: 79fb ldrb r3, [r7, #7] + 800663a: 009b lsls r3, r3, #2 + 800663c: 4413 add r3, r2 + 800663e: 681b ldr r3, [r3, #0] + 8006640: 781b ldrb r3, [r3, #0] + 8006642: 2b01 cmp r3, #1 + 8006644: d172 bne.n 800672c + { + ssd1306_print(POINTS_ROW + s - 1, POINTS_NAME_COL, pp_memory_slot[s]->point_name, 0); //print point name + 8006646: 79fb ldrb r3, [r7, #7] + 8006648: 3301 adds r3, #1 + 800664a: b2d8 uxtb r0, r3 + 800664c: 4b47 ldr r3, [pc, #284] ; (800676c ) + 800664e: 681a ldr r2, [r3, #0] + 8006650: 79fb ldrb r3, [r7, #7] + 8006652: 009b lsls r3, r3, #2 + 8006654: 4413 add r3, r2 + 8006656: 681b ldr r3, [r3, #0] + 8006658: 1d1a adds r2, r3, #4 + 800665a: 2300 movs r3, #0 + 800665c: 2104 movs r1, #4 + 800665e: f002 fe3e bl 80092de + + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL, pp_memory_slot[s]->save_date[0], 0); //print point save date + 8006662: 79fb ldrb r3, [r7, #7] + 8006664: 3301 adds r3, #1 + 8006666: b2d8 uxtb r0, r3 + 8006668: 4b40 ldr r3, [pc, #256] ; (800676c ) + 800666a: 681a ldr r2, [r3, #0] + 800666c: 79fb ldrb r3, [r7, #7] + 800666e: 009b lsls r3, r3, #2 + 8006670: 4413 add r3, r2 + 8006672: 681b ldr r3, [r3, #0] + 8006674: 7a9a ldrb r2, [r3, #10] + 8006676: 2300 movs r3, #0 + 8006678: 210a movs r1, #10 + 800667a: f002 fe11 bl 80092a0 + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 1, pp_memory_slot[s]->save_date[1], 0); + 800667e: 79fb ldrb r3, [r7, #7] + 8006680: 3301 adds r3, #1 + 8006682: b2d8 uxtb r0, r3 + 8006684: 4b39 ldr r3, [pc, #228] ; (800676c ) + 8006686: 681a ldr r2, [r3, #0] + 8006688: 79fb ldrb r3, [r7, #7] + 800668a: 009b lsls r3, r3, #2 + 800668c: 4413 add r3, r2 + 800668e: 681b ldr r3, [r3, #0] + 8006690: 7ada ldrb r2, [r3, #11] + 8006692: 2300 movs r3, #0 + 8006694: 210b movs r1, #11 + 8006696: f002 fe03 bl 80092a0 + ssd1306_print(POINTS_ROW + s - 1, POINTS_DATE_COL + 2, ".", 0); + 800669a: 79fb ldrb r3, [r7, #7] + 800669c: 3301 adds r3, #1 + 800669e: b2d8 uxtb r0, r3 + 80066a0: 2300 movs r3, #0 + 80066a2: 4a33 ldr r2, [pc, #204] ; (8006770 ) + 80066a4: 210c movs r1, #12 + 80066a6: f002 fe1a bl 80092de + + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 3, pp_memory_slot[s]->save_date[2], 0); + 80066aa: 79fb ldrb r3, [r7, #7] + 80066ac: 3301 adds r3, #1 + 80066ae: b2d8 uxtb r0, r3 + 80066b0: 4b2e ldr r3, [pc, #184] ; (800676c ) + 80066b2: 681a ldr r2, [r3, #0] + 80066b4: 79fb ldrb r3, [r7, #7] + 80066b6: 009b lsls r3, r3, #2 + 80066b8: 4413 add r3, r2 + 80066ba: 681b ldr r3, [r3, #0] + 80066bc: 7b1a ldrb r2, [r3, #12] + 80066be: 2300 movs r3, #0 + 80066c0: 210d movs r1, #13 + 80066c2: f002 fded bl 80092a0 + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 4, pp_memory_slot[s]->save_date[3], 0); + 80066c6: 79fb ldrb r3, [r7, #7] + 80066c8: 3301 adds r3, #1 + 80066ca: b2d8 uxtb r0, r3 + 80066cc: 4b27 ldr r3, [pc, #156] ; (800676c ) + 80066ce: 681a ldr r2, [r3, #0] + 80066d0: 79fb ldrb r3, [r7, #7] + 80066d2: 009b lsls r3, r3, #2 + 80066d4: 4413 add r3, r2 + 80066d6: 681b ldr r3, [r3, #0] + 80066d8: 7b5a ldrb r2, [r3, #13] + 80066da: 2300 movs r3, #0 + 80066dc: 210e movs r1, #14 + 80066de: f002 fddf bl 80092a0 + ssd1306_print(POINTS_ROW + s - 1, POINTS_DATE_COL + 5, ".", 0); + 80066e2: 79fb ldrb r3, [r7, #7] + 80066e4: 3301 adds r3, #1 + 80066e6: b2d8 uxtb r0, r3 + 80066e8: 2300 movs r3, #0 + 80066ea: 4a21 ldr r2, [pc, #132] ; (8006770 ) + 80066ec: 210f movs r1, #15 + 80066ee: f002 fdf6 bl 80092de + + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 6, pp_memory_slot[s]->save_date[4], 0); + 80066f2: 79fb ldrb r3, [r7, #7] + 80066f4: 3301 adds r3, #1 + 80066f6: b2d8 uxtb r0, r3 + 80066f8: 4b1c ldr r3, [pc, #112] ; (800676c ) + 80066fa: 681a ldr r2, [r3, #0] + 80066fc: 79fb ldrb r3, [r7, #7] + 80066fe: 009b lsls r3, r3, #2 + 8006700: 4413 add r3, r2 + 8006702: 681b ldr r3, [r3, #0] + 8006704: 7b9a ldrb r2, [r3, #14] + 8006706: 2300 movs r3, #0 + 8006708: 2110 movs r1, #16 + 800670a: f002 fdc9 bl 80092a0 + ssd1306_char_pos(POINTS_ROW + s - 1, POINTS_DATE_COL + 7, pp_memory_slot[s]->save_date[5], 0); + 800670e: 79fb ldrb r3, [r7, #7] + 8006710: 3301 adds r3, #1 + 8006712: b2d8 uxtb r0, r3 + 8006714: 4b15 ldr r3, [pc, #84] ; (800676c ) + 8006716: 681a ldr r2, [r3, #0] + 8006718: 79fb ldrb r3, [r7, #7] + 800671a: 009b lsls r3, r3, #2 + 800671c: 4413 add r3, r2 + 800671e: 681b ldr r3, [r3, #0] + 8006720: 7bda ldrb r2, [r3, #15] + 8006722: 2300 movs r3, #0 + 8006724: 2111 movs r1, #17 + 8006726: f002 fdbb bl 80092a0 + 800672a: e007 b.n 800673c + } + else + { + ssd1306_print(POINTS_ROW + s - 1, POINTS_NAME_COL, "empty", 0); + 800672c: 79fb ldrb r3, [r7, #7] + 800672e: 3301 adds r3, #1 + 8006730: b2d8 uxtb r0, r3 + 8006732: 2300 movs r3, #0 + 8006734: 4a0f ldr r2, [pc, #60] ; (8006774 ) + 8006736: 2104 movs r1, #4 + 8006738: f002 fdd1 bl 80092de + for (uint8_t s = 1; s <= MEMORY_SLOTS_TOTAL; s++) + 800673c: 79fb ldrb r3, [r7, #7] + 800673e: 3301 adds r3, #1 + 8006740: 71fb strb r3, [r7, #7] + 8006742: 79fb ldrb r3, [r7, #7] + 8006744: 2b05 cmp r3, #5 + 8006746: f67f af67 bls.w 8006618 + } + } + + ssd1306_print(POINTS_ROW + current_slot_to_load - 1, POINTS_COL - 1, ">", 0); //print pointer + 800674a: 4b0b ldr r3, [pc, #44] ; (8006778 ) + 800674c: 781b ldrb r3, [r3, #0] + 800674e: 3301 adds r3, #1 + 8006750: b2d8 uxtb r0, r3 + 8006752: 2300 movs r3, #0 + 8006754: 4a09 ldr r2, [pc, #36] ; (800677c ) + 8006756: 2100 movs r1, #0 + 8006758: f002 fdc1 bl 80092de + + ssd1306_update(); + 800675c: f002 fc98 bl 8009090 +} + 8006760: bf00 nop + 8006762: 3708 adds r7, #8 + 8006764: 46bd mov sp, r7 + 8006766: bd80 pop {r7, pc} + 8006768: 0800cb7c .word 0x0800cb7c + 800676c: 200007d4 .word 0x200007d4 + 8006770: 0800ca28 .word 0x0800ca28 + 8006774: 0800cb84 .word 0x0800cb84 + 8006778: 20000033 .word 0x20000033 + 800677c: 0800ca14 .word 0x0800ca14 + +08006780 : + + + +void draw_each_point(void) +{ + 8006780: b580 push {r7, lr} + 8006782: af00 add r7, sp, #0 + #define EACH_POINT_ROW (2) + #define EACH_POINT_COL (1) + + ssd1306_clear(); + 8006784: f002 fca4 bl 80090d0 + + ssd1306_print(0, EACH_POINT_COL, "POINT ", 0); + 8006788: 2300 movs r3, #0 + 800678a: 4a15 ldr r2, [pc, #84] ; (80067e0 ) + 800678c: 2101 movs r1, #1 + 800678e: 2000 movs r0, #0 + 8006790: f002 fda5 bl 80092de + ssd1306_print_next(pp_memory_slot[current_slot_to_load]->slot_name, 0); + 8006794: 4b13 ldr r3, [pc, #76] ; (80067e4 ) + 8006796: 681a ldr r2, [r3, #0] + 8006798: 4b13 ldr r3, [pc, #76] ; (80067e8 ) + 800679a: 781b ldrb r3, [r3, #0] + 800679c: 009b lsls r3, r3, #2 + 800679e: 4413 add r3, r2 + 80067a0: 681b ldr r3, [r3, #0] + 80067a2: 3301 adds r3, #1 + 80067a4: 2100 movs r1, #0 + 80067a6: 4618 mov r0, r3 + 80067a8: f002 fdf8 bl 800939c + + ssd1306_print(EACH_POINT_ROW, EACH_POINT_COL, "Load", 0); + 80067ac: 2300 movs r3, #0 + 80067ae: 4a0f ldr r2, [pc, #60] ; (80067ec ) + 80067b0: 2101 movs r1, #1 + 80067b2: 2002 movs r0, #2 + 80067b4: f002 fd93 bl 80092de + ssd1306_print(EACH_POINT_ROW + 1, EACH_POINT_COL, "Delete", 0); + 80067b8: 2300 movs r3, #0 + 80067ba: 4a0d ldr r2, [pc, #52] ; (80067f0 ) + 80067bc: 2101 movs r1, #1 + 80067be: 2003 movs r0, #3 + 80067c0: f002 fd8d bl 80092de + ssd1306_print(EACH_POINT_ROW + get_current_item(), EACH_POINT_COL - 1, ">", 0); + 80067c4: f7fd fcce bl 8004164 + 80067c8: 4603 mov r3, r0 + 80067ca: 3302 adds r3, #2 + 80067cc: b2d8 uxtb r0, r3 + 80067ce: 2300 movs r3, #0 + 80067d0: 4a08 ldr r2, [pc, #32] ; (80067f4 ) + 80067d2: 2100 movs r1, #0 + 80067d4: f002 fd83 bl 80092de + + ssd1306_update(); + 80067d8: f002 fc5a bl 8009090 +} + 80067dc: bf00 nop + 80067de: bd80 pop {r7, pc} + 80067e0: 0800cb8c .word 0x0800cb8c + 80067e4: 200007d4 .word 0x200007d4 + 80067e8: 20000033 .word 0x20000033 + 80067ec: 0800cb94 .word 0x0800cb94 + 80067f0: 0800cadc .word 0x0800cadc + 80067f4: 0800ca14 .word 0x0800ca14 + +080067f8 : + + + +void draw_load_point(void) +{ + 80067f8: b580 push {r7, lr} + 80067fa: b082 sub sp, #8 + 80067fc: af00 add r7, sp, #0 + #define LOAD_POINT_ROW (2) + #define LOAD_POINT_COL (1) + + ssd1306_clear(); + 80067fe: f002 fc67 bl 80090d0 + + ssd1306_print(0, LOAD_POINT_COL, "Where to load ", 0); + 8006802: 2300 movs r3, #0 + 8006804: 4a34 ldr r2, [pc, #208] ; (80068d8 ) + 8006806: 2101 movs r1, #1 + 8006808: 2000 movs r0, #0 + 800680a: f002 fd68 bl 80092de + ssd1306_print_next(pp_memory_slot[current_slot_to_load]->slot_name, 0); + 800680e: 4b33 ldr r3, [pc, #204] ; (80068dc ) + 8006810: 681a ldr r2, [r3, #0] + 8006812: 4b33 ldr r3, [pc, #204] ; (80068e0 ) + 8006814: 781b ldrb r3, [r3, #0] + 8006816: 009b lsls r3, r3, #2 + 8006818: 4413 add r3, r2 + 800681a: 681b ldr r3, [r3, #0] + 800681c: 3301 adds r3, #1 + 800681e: 2100 movs r1, #0 + 8006820: 4618 mov r0, r3 + 8006822: f002 fdbb bl 800939c + ssd1306_print_next("?", 0); + 8006826: 2100 movs r1, #0 + 8006828: 482e ldr r0, [pc, #184] ; (80068e4 ) + 800682a: f002 fdb7 bl 800939c + + uint8_t another_device_to_load_row = LOAD_POINT_ROW; + 800682e: 2302 movs r3, #2 + 8006830: 71fb strb r3, [r7, #7] + uint8_t devices_enlisted_cntr = 0; + 8006832: 2300 movs r3, #0 + 8006834: 71bb strb r3, [r7, #6] + + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 8006836: 2301 movs r3, #1 + 8006838: 717b strb r3, [r7, #5] + 800683a: e02a b.n 8006892 + { + if (pp_dev_aux[dev]->exist_flag == 0) + 800683c: 4b2a ldr r3, [pc, #168] ; (80068e8 ) + 800683e: 681a ldr r2, [r3, #0] + 8006840: 797b ldrb r3, [r7, #5] + 8006842: 009b lsls r3, r3, #2 + 8006844: 4413 add r3, r2 + 8006846: 681b ldr r3, [r3, #0] + 8006848: 781b ldrb r3, [r3, #0] + 800684a: 2b00 cmp r3, #0 + 800684c: d11e bne.n 800688c + { + device_to_load_list[dev] = devices_enlisted_cntr++; //first nonexisting device will get index 0 + 800684e: 79bb ldrb r3, [r7, #6] + 8006850: 1c5a adds r2, r3, #1 + 8006852: 71ba strb r2, [r7, #6] + 8006854: 797a ldrb r2, [r7, #5] + 8006856: 4925 ldr r1, [pc, #148] ; (80068ec ) + 8006858: 548b strb r3, [r1, r2] + + if (current_device_to_load == 0) //if for the first time + 800685a: 4b25 ldr r3, [pc, #148] ; (80068f0 ) + 800685c: 781b ldrb r3, [r3, #0] + 800685e: 2b00 cmp r3, #0 + 8006860: d102 bne.n 8006868 + { + current_device_to_load = dev; + 8006862: 4a23 ldr r2, [pc, #140] ; (80068f0 ) + 8006864: 797b ldrb r3, [r7, #5] + 8006866: 7013 strb r3, [r2, #0] + } + + //Device + ssd1306_print(another_device_to_load_row, LOAD_POINT_COL, "Device ", 0); + 8006868: 79f8 ldrb r0, [r7, #7] + 800686a: 2300 movs r3, #0 + 800686c: 4a21 ldr r2, [pc, #132] ; (80068f4 ) + 800686e: 2101 movs r1, #1 + 8006870: f002 fd35 bl 80092de + + //Number + itoa32(dev, &buf[0]); + 8006874: 797b ldrb r3, [r7, #5] + 8006876: 4920 ldr r1, [pc, #128] ; (80068f8 ) + 8006878: 4618 mov r0, r3 + 800687a: f001 ffcd bl 8008818 + ssd1306_print_next(&buf[0], 0); + 800687e: 2100 movs r1, #0 + 8006880: 481d ldr r0, [pc, #116] ; (80068f8 ) + 8006882: f002 fd8b bl 800939c + + another_device_to_load_row++; + 8006886: 79fb ldrb r3, [r7, #7] + 8006888: 3301 adds r3, #1 + 800688a: 71fb strb r3, [r7, #7] + for (uint8_t dev = 1; dev <= DEVICES_IN_GROUP; dev++) + 800688c: 797b ldrb r3, [r7, #5] + 800688e: 3301 adds r3, #1 + 8006890: 717b strb r3, [r7, #5] + 8006892: 797b ldrb r3, [r7, #5] + 8006894: 2b06 cmp r3, #6 + 8006896: d9d1 bls.n 800683c + } + } + + if (devices_enlisted_cntr > 0) + 8006898: 79bb ldrb r3, [r7, #6] + 800689a: 2b00 cmp r3, #0 + 800689c: d00c beq.n 80068b8 + { + ssd1306_print(LOAD_POINT_ROW + device_to_load_list[current_device_to_load], LOAD_POINT_COL - 1, ">", 0); + 800689e: 4b14 ldr r3, [pc, #80] ; (80068f0 ) + 80068a0: 781b ldrb r3, [r3, #0] + 80068a2: 461a mov r2, r3 + 80068a4: 4b11 ldr r3, [pc, #68] ; (80068ec ) + 80068a6: 5c9b ldrb r3, [r3, r2] + 80068a8: 3302 adds r3, #2 + 80068aa: b2d8 uxtb r0, r3 + 80068ac: 2300 movs r3, #0 + 80068ae: 4a13 ldr r2, [pc, #76] ; (80068fc ) + 80068b0: 2100 movs r1, #0 + 80068b2: f002 fd14 bl 80092de + 80068b6: e008 b.n 80068ca + } + else + { + ssd1306_print(LOAD_POINT_ROW, LOAD_POINT_COL, "no empty devices", 0); + 80068b8: 2300 movs r3, #0 + 80068ba: 4a11 ldr r2, [pc, #68] ; (8006900 ) + 80068bc: 2101 movs r1, #1 + 80068be: 2002 movs r0, #2 + 80068c0: f002 fd0d bl 80092de + current_device_to_load = 0; + 80068c4: 4b0a ldr r3, [pc, #40] ; (80068f0 ) + 80068c6: 2200 movs r2, #0 + 80068c8: 701a strb r2, [r3, #0] + } + + ssd1306_update(); + 80068ca: f002 fbe1 bl 8009090 +} + 80068ce: bf00 nop + 80068d0: 3708 adds r7, #8 + 80068d2: 46bd mov sp, r7 + 80068d4: bd80 pop {r7, pc} + 80068d6: bf00 nop + 80068d8: 0800cb9c .word 0x0800cb9c + 80068dc: 200007d4 .word 0x200007d4 + 80068e0: 20000033 .word 0x20000033 + 80068e4: 0800caf4 .word 0x0800caf4 + 80068e8: 2000083c .word 0x2000083c + 80068ec: 200007ec .word 0x200007ec + 80068f0: 20000122 .word 0x20000122 + 80068f4: 0800cbac .word 0x0800cbac + 80068f8: 20000810 .word 0x20000810 + 80068fc: 0800ca14 .word 0x0800ca14 + 8006900: 0800cbb4 .word 0x0800cbb4 + +08006904 : + + + +void draw_delete_point(void) +{ + 8006904: b580 push {r7, lr} + 8006906: af00 add r7, sp, #0 + ssd1306_clear(); + 8006908: f002 fbe2 bl 80090d0 + ssd1306_print(0, 1, "Delete point ", 0); + 800690c: 2300 movs r3, #0 + 800690e: 4a12 ldr r2, [pc, #72] ; (8006958 ) + 8006910: 2101 movs r1, #1 + 8006912: 2000 movs r0, #0 + 8006914: f002 fce3 bl 80092de + ssd1306_print_next(pp_memory_slot[current_slot_to_load]->slot_name, 0); + 8006918: 4b10 ldr r3, [pc, #64] ; (800695c ) + 800691a: 681a ldr r2, [r3, #0] + 800691c: 4b10 ldr r3, [pc, #64] ; (8006960 ) + 800691e: 781b ldrb r3, [r3, #0] + 8006920: 009b lsls r3, r3, #2 + 8006922: 4413 add r3, r2 + 8006924: 681b ldr r3, [r3, #0] + 8006926: 3301 adds r3, #1 + 8006928: 2100 movs r1, #0 + 800692a: 4618 mov r0, r3 + 800692c: f002 fd36 bl 800939c + ssd1306_print_next("?", 0); + 8006930: 2100 movs r1, #0 + 8006932: 480c ldr r0, [pc, #48] ; (8006964 ) + 8006934: f002 fd32 bl 800939c + ssd1306_print(3, 1, "OK - delete", 0); + 8006938: 2300 movs r3, #0 + 800693a: 4a0b ldr r2, [pc, #44] ; (8006968 ) + 800693c: 2101 movs r1, #1 + 800693e: 2003 movs r0, #3 + 8006940: f002 fccd bl 80092de + ssd1306_print(4, 1, "ESC - cancel", 0); + 8006944: 2300 movs r3, #0 + 8006946: 4a09 ldr r2, [pc, #36] ; (800696c ) + 8006948: 2101 movs r1, #1 + 800694a: 2004 movs r0, #4 + 800694c: f002 fcc7 bl 80092de + ssd1306_update(); + 8006950: f002 fb9e bl 8009090 +} + 8006954: bf00 nop + 8006956: bd80 pop {r7, pc} + 8006958: 0800cbc8 .word 0x0800cbc8 + 800695c: 200007d4 .word 0x200007d4 + 8006960: 20000033 .word 0x20000033 + 8006964: 0800caf4 .word 0x0800caf4 + 8006968: 0800cb0c .word 0x0800cb0c + 800696c: 0800cb18 .word 0x0800cb18 + +08006970 : + + + +//SETTINGS +void draw_settings(void) +{ + 8006970: b580 push {r7, lr} + 8006972: af00 add r7, sp, #0 + #define SETTINGS_ROW (2) + #define SETTINGS_COL (1) + + ssd1306_clear(); + 8006974: f002 fbac bl 80090d0 + ssd1306_print(0, SETTINGS_COL, "SETTINGS", 0); + 8006978: 2300 movs r3, #0 + 800697a: 4a12 ldr r2, [pc, #72] ; (80069c4 ) + 800697c: 2101 movs r1, #1 + 800697e: 2000 movs r0, #0 + 8006980: f002 fcad bl 80092de + ssd1306_print(SETTINGS_ROW, SETTINGS_COL, "Edit", 0); + 8006984: 2300 movs r3, #0 + 8006986: 4a10 ldr r2, [pc, #64] ; (80069c8 ) + 8006988: 2101 movs r1, #1 + 800698a: 2002 movs r0, #2 + 800698c: f002 fca7 bl 80092de + ssd1306_print(SETTINGS_ROW + 1, SETTINGS_COL, "Restore", 0); + 8006990: 2300 movs r3, #0 + 8006992: 4a0e ldr r2, [pc, #56] ; (80069cc ) + 8006994: 2101 movs r1, #1 + 8006996: 2003 movs r0, #3 + 8006998: f002 fca1 bl 80092de + ssd1306_print(SETTINGS_ROW + 2, SETTINGS_COL, "Erase", 0); + 800699c: 2300 movs r3, #0 + 800699e: 4a0c ldr r2, [pc, #48] ; (80069d0 ) + 80069a0: 2101 movs r1, #1 + 80069a2: 2004 movs r0, #4 + 80069a4: f002 fc9b bl 80092de + ssd1306_print(SETTINGS_ROW + get_current_item(), SETTINGS_COL - 1, ">", 0); + 80069a8: f7fd fbdc bl 8004164 + 80069ac: 4603 mov r3, r0 + 80069ae: 3302 adds r3, #2 + 80069b0: b2d8 uxtb r0, r3 + 80069b2: 2300 movs r3, #0 + 80069b4: 4a07 ldr r2, [pc, #28] ; (80069d4 ) + 80069b6: 2100 movs r1, #0 + 80069b8: f002 fc91 bl 80092de + ssd1306_update(); + 80069bc: f002 fb68 bl 8009090 +} + 80069c0: bf00 nop + 80069c2: bd80 pop {r7, pc} + 80069c4: 0800cbd8 .word 0x0800cbd8 + 80069c8: 0800cbe4 .word 0x0800cbe4 + 80069cc: 0800cbec .word 0x0800cbec + 80069d0: 0800cbf4 .word 0x0800cbf4 + 80069d4: 0800ca14 .word 0x0800ca14 + +080069d8 : + + + +//INFO +void draw_info(void) +{ + 80069d8: b580 push {r7, lr} + 80069da: af00 add r7, sp, #0 + ssd1306_clear(); + 80069dc: f002 fb78 bl 80090d0 + + ssd1306_bitmap(&info_blank[0]); + 80069e0: 481a ldr r0, [pc, #104] ; (8006a4c ) + 80069e2: f002 fcf3 bl 80093cc + + ssd1306_print(0, 0, "LRNS", 0); + 80069e6: 2300 movs r3, #0 + 80069e8: 4a19 ldr r2, [pc, #100] ; (8006a50 ) + 80069ea: 2100 movs r1, #0 + 80069ec: 2000 movs r0, #0 + 80069ee: f002 fc76 bl 80092de + + ssd1306_print(2, 0, "HW/FW: ", 0); + 80069f2: 2300 movs r3, #0 + 80069f4: 4a17 ldr r2, [pc, #92] ; (8006a54 ) + 80069f6: 2100 movs r1, #0 + 80069f8: 2002 movs r0, #2 + 80069fa: f002 fc70 bl 80092de + ssd1306_print_next(HW_VERSION, 0); + 80069fe: 4b16 ldr r3, [pc, #88] ; (8006a58 ) + 8006a00: 681b ldr r3, [r3, #0] + 8006a02: 2100 movs r1, #0 + 8006a04: 4618 mov r0, r3 + 8006a06: f002 fcc9 bl 800939c + ssd1306_print_next("/", 0); + 8006a0a: 2100 movs r1, #0 + 8006a0c: 4813 ldr r0, [pc, #76] ; (8006a5c ) + 8006a0e: f002 fcc5 bl 800939c + ssd1306_print_next(FW_VERSION, 0); + 8006a12: 4b13 ldr r3, [pc, #76] ; (8006a60 ) + 8006a14: 681b ldr r3, [r3, #0] + 8006a16: 2100 movs r1, #0 + 8006a18: 4618 mov r0, r3 + 8006a1a: f002 fcbf bl 800939c + + ssd1306_print(3, 0, __TIME__, 0); + 8006a1e: 2300 movs r3, #0 + 8006a20: 4a10 ldr r2, [pc, #64] ; (8006a64 ) + 8006a22: 2100 movs r1, #0 + 8006a24: 2003 movs r0, #3 + 8006a26: f002 fc5a bl 80092de + ssd1306_print(4, 0, __DATE__, 0); + 8006a2a: 2300 movs r3, #0 + 8006a2c: 4a0e ldr r2, [pc, #56] ; (8006a68 ) + 8006a2e: 2100 movs r1, #0 + 8006a30: 2004 movs r0, #4 + 8006a32: f002 fc54 bl 80092de + + ssd1306_print(7, 0, "(C)2021 Feruz Topalov", 0); + 8006a36: 2300 movs r3, #0 + 8006a38: 4a0c ldr r2, [pc, #48] ; (8006a6c ) + 8006a3a: 2100 movs r1, #0 + 8006a3c: 2007 movs r0, #7 + 8006a3e: f002 fc4e bl 80092de + + ssd1306_update(); + 8006a42: f002 fb25 bl 8009090 +} + 8006a46: bf00 nop + 8006a48: bd80 pop {r7, pc} + 8006a4a: bf00 nop + 8006a4c: 0800e144 .word 0x0800e144 + 8006a50: 0800cbfc .word 0x0800cbfc + 8006a54: 0800cc04 .word 0x0800cc04 + 8006a58: 2000001c .word 0x2000001c + 8006a5c: 0800ca80 .word 0x0800ca80 + 8006a60: 20000018 .word 0x20000018 + 8006a64: 0800cc0c .word 0x0800cc0c + 8006a68: 0800cc18 .word 0x0800cc18 + 8006a6c: 0800cc24 .word 0x0800cc24 + +08006a70 : + + + +//EDIT SETTINGS +void draw_edit_settings(void) +{ + 8006a70: b580 push {r7, lr} + 8006a72: af00 add r7, sp, #0 + #define EDIT_SETTINGS_ROW (1) + #define EDIT_SETTINGS_COL (1) + #define EDIT_SETTINGS_PARAM_COL (15) + + ssd1306_clear(); + 8006a74: f002 fb2c bl 80090d0 + ssd1306_print(0, EDIT_SETTINGS_COL + 1, "EDIT SETTINGS", 0); + 8006a78: 2300 movs r3, #0 + 8006a7a: 4a57 ldr r2, [pc, #348] ; (8006bd8 ) + 8006a7c: 2102 movs r1, #2 + 8006a7e: 2000 movs r0, #0 + 8006a80: f002 fc2d bl 80092de + + ssd1306_print(EDIT_SETTINGS_ROW, EDIT_SETTINGS_COL, "Device number", 0); + 8006a84: 2300 movs r3, #0 + 8006a86: 4a55 ldr r2, [pc, #340] ; (8006bdc ) + 8006a88: 2101 movs r1, #1 + 8006a8a: 2001 movs r0, #1 + 8006a8c: f002 fc27 bl 80092de + itoa32(settings_copy.device_number, &buf[0]); + 8006a90: 4b53 ldr r3, [pc, #332] ; (8006be0 ) + 8006a92: 781b ldrb r3, [r3, #0] + 8006a94: 4953 ldr r1, [pc, #332] ; (8006be4 ) + 8006a96: 4618 mov r0, r3 + 8006a98: f001 febe bl 8008818 + ssd1306_print(EDIT_SETTINGS_ROW, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + 8006a9c: 2300 movs r3, #0 + 8006a9e: 4a51 ldr r2, [pc, #324] ; (8006be4 ) + 8006aa0: 210f movs r1, #15 + 8006aa2: 2001 movs r0, #1 + 8006aa4: f002 fc1b bl 80092de + + ssd1306_print(EDIT_SETTINGS_ROW + 1, EDIT_SETTINGS_COL, "Device ID", 0); + 8006aa8: 2300 movs r3, #0 + 8006aaa: 4a4f ldr r2, [pc, #316] ; (8006be8 ) + 8006aac: 2101 movs r1, #1 + 8006aae: 2002 movs r0, #2 + 8006ab0: f002 fc15 bl 80092de + buf[0] = settings_copy.device_id[0]; + 8006ab4: 4b4a ldr r3, [pc, #296] ; (8006be0 ) + 8006ab6: 785a ldrb r2, [r3, #1] + 8006ab8: 4b4a ldr r3, [pc, #296] ; (8006be4 ) + 8006aba: 701a strb r2, [r3, #0] + buf[1] = settings_copy.device_id[1]; + 8006abc: 4b48 ldr r3, [pc, #288] ; (8006be0 ) + 8006abe: 789a ldrb r2, [r3, #2] + 8006ac0: 4b48 ldr r3, [pc, #288] ; (8006be4 ) + 8006ac2: 705a strb r2, [r3, #1] + buf[2] = 0; + 8006ac4: 4b47 ldr r3, [pc, #284] ; (8006be4 ) + 8006ac6: 2200 movs r2, #0 + 8006ac8: 709a strb r2, [r3, #2] + ssd1306_print(EDIT_SETTINGS_ROW + 1, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + 8006aca: 2300 movs r3, #0 + 8006acc: 4a45 ldr r2, [pc, #276] ; (8006be4 ) + 8006ace: 210f movs r1, #15 + 8006ad0: 2002 movs r0, #2 + 8006ad2: f002 fc04 bl 80092de + + ssd1306_print(EDIT_SETTINGS_ROW + 2, EDIT_SETTINGS_COL, "Freq channel", 0); + 8006ad6: 2300 movs r3, #0 + 8006ad8: 4a44 ldr r2, [pc, #272] ; (8006bec ) + 8006ada: 2101 movs r1, #1 + 8006adc: 2003 movs r0, #3 + 8006ade: f002 fbfe bl 80092de + itoa32(settings_copy.freq_channel, &buf[0]); + 8006ae2: 4b3f ldr r3, [pc, #252] ; (8006be0 ) + 8006ae4: 78db ldrb r3, [r3, #3] + 8006ae6: 493f ldr r1, [pc, #252] ; (8006be4 ) + 8006ae8: 4618 mov r0, r3 + 8006aea: f001 fe95 bl 8008818 + ssd1306_print(EDIT_SETTINGS_ROW + 2, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + 8006aee: 2300 movs r3, #0 + 8006af0: 4a3c ldr r2, [pc, #240] ; (8006be4 ) + 8006af2: 210f movs r1, #15 + 8006af4: 2003 movs r0, #3 + 8006af6: f002 fbf2 bl 80092de + + ssd1306_print(EDIT_SETTINGS_ROW + 3, EDIT_SETTINGS_COL, "TX power", 0); + 8006afa: 2300 movs r3, #0 + 8006afc: 4a3c ldr r2, [pc, #240] ; (8006bf0 ) + 8006afe: 2101 movs r1, #1 + 8006b00: 2004 movs r0, #4 + 8006b02: f002 fbec bl 80092de + itoa32(p_get_tx_power_values[settings_copy.tx_power_opt], &buf[0]); + 8006b06: 4b3b ldr r3, [pc, #236] ; (8006bf4 ) + 8006b08: 681b ldr r3, [r3, #0] + 8006b0a: 4a35 ldr r2, [pc, #212] ; (8006be0 ) + 8006b0c: 7912 ldrb r2, [r2, #4] + 8006b0e: 4413 add r3, r2 + 8006b10: 781b ldrb r3, [r3, #0] + 8006b12: 4934 ldr r1, [pc, #208] ; (8006be4 ) + 8006b14: 4618 mov r0, r3 + 8006b16: f001 fe7f bl 8008818 + ssd1306_print(EDIT_SETTINGS_ROW + 3, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + 8006b1a: 2300 movs r3, #0 + 8006b1c: 4a31 ldr r2, [pc, #196] ; (8006be4 ) + 8006b1e: 210f movs r1, #15 + 8006b20: 2004 movs r0, #4 + 8006b22: f002 fbdc bl 80092de + ssd1306_print_next(" mW", 0); + 8006b26: 2100 movs r1, #0 + 8006b28: 4833 ldr r0, [pc, #204] ; (8006bf8 ) + 8006b2a: f002 fc37 bl 800939c + + ssd1306_print(EDIT_SETTINGS_ROW + 4, EDIT_SETTINGS_COL, "Send interval", 0); + 8006b2e: 2300 movs r3, #0 + 8006b30: 4a32 ldr r2, [pc, #200] ; (8006bfc ) + 8006b32: 2101 movs r1, #1 + 8006b34: 2005 movs r0, #5 + 8006b36: f002 fbd2 bl 80092de + itoa32(p_send_interval_values[settings_copy.send_interval_opt], &buf[0]); + 8006b3a: 4b31 ldr r3, [pc, #196] ; (8006c00 ) + 8006b3c: 681b ldr r3, [r3, #0] + 8006b3e: 4a28 ldr r2, [pc, #160] ; (8006be0 ) + 8006b40: 7952 ldrb r2, [r2, #5] + 8006b42: 4413 add r3, r2 + 8006b44: 781b ldrb r3, [r3, #0] + 8006b46: 4927 ldr r1, [pc, #156] ; (8006be4 ) + 8006b48: 4618 mov r0, r3 + 8006b4a: f001 fe65 bl 8008818 + ssd1306_print(EDIT_SETTINGS_ROW + 4, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + 8006b4e: 2300 movs r3, #0 + 8006b50: 4a24 ldr r2, [pc, #144] ; (8006be4 ) + 8006b52: 210f movs r1, #15 + 8006b54: 2005 movs r0, #5 + 8006b56: f002 fbc2 bl 80092de + ssd1306_print_next(" s", 0); + 8006b5a: 2100 movs r1, #0 + 8006b5c: 4829 ldr r0, [pc, #164] ; (8006c04 ) + 8006b5e: f002 fc1d bl 800939c + + ssd1306_print(EDIT_SETTINGS_ROW + 5, EDIT_SETTINGS_COL, "Timeout thr", 0); + 8006b62: 2300 movs r3, #0 + 8006b64: 4a28 ldr r2, [pc, #160] ; (8006c08 ) + 8006b66: 2101 movs r1, #1 + 8006b68: 2006 movs r0, #6 + 8006b6a: f002 fbb8 bl 80092de + itoa32(settings_copy.timeout_threshold.as_integer, &buf[0]); + 8006b6e: 4b1c ldr r3, [pc, #112] ; (8006be0 ) + 8006b70: 88db ldrh r3, [r3, #6] + 8006b72: 491c ldr r1, [pc, #112] ; (8006be4 ) + 8006b74: 4618 mov r0, r3 + 8006b76: f001 fe4f bl 8008818 + ssd1306_print(EDIT_SETTINGS_ROW + 5, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + 8006b7a: 2300 movs r3, #0 + 8006b7c: 4a19 ldr r2, [pc, #100] ; (8006be4 ) + 8006b7e: 210f movs r1, #15 + 8006b80: 2006 movs r0, #6 + 8006b82: f002 fbac bl 80092de + ssd1306_print_next(" s", 0); + 8006b86: 2100 movs r1, #0 + 8006b88: 481e ldr r0, [pc, #120] ; (8006c04 ) + 8006b8a: f002 fc07 bl 800939c + + ssd1306_print(EDIT_SETTINGS_ROW + 6, EDIT_SETTINGS_COL, "Fence thr", 0); + 8006b8e: 2300 movs r3, #0 + 8006b90: 4a1e ldr r2, [pc, #120] ; (8006c0c ) + 8006b92: 2101 movs r1, #1 + 8006b94: 2007 movs r0, #7 + 8006b96: f002 fba2 bl 80092de + itoa32(settings_copy.fence_threshold.as_integer, &buf[0]); + 8006b9a: 4b11 ldr r3, [pc, #68] ; (8006be0 ) + 8006b9c: 891b ldrh r3, [r3, #8] + 8006b9e: 4911 ldr r1, [pc, #68] ; (8006be4 ) + 8006ba0: 4618 mov r0, r3 + 8006ba2: f001 fe39 bl 8008818 + ssd1306_print(EDIT_SETTINGS_ROW + 6, EDIT_SETTINGS_PARAM_COL, &buf[0], 0); + 8006ba6: 2300 movs r3, #0 + 8006ba8: 4a0e ldr r2, [pc, #56] ; (8006be4 ) + 8006baa: 210f movs r1, #15 + 8006bac: 2007 movs r0, #7 + 8006bae: f002 fb96 bl 80092de + ssd1306_print_next(" m", 0); + 8006bb2: 2100 movs r1, #0 + 8006bb4: 4816 ldr r0, [pc, #88] ; (8006c10 ) + 8006bb6: f002 fbf1 bl 800939c + + ssd1306_print(EDIT_SETTINGS_ROW + get_current_item(), EDIT_SETTINGS_COL - 1, ">", 0); + 8006bba: f7fd fad3 bl 8004164 + 8006bbe: 4603 mov r3, r0 + 8006bc0: 3301 adds r3, #1 + 8006bc2: b2d8 uxtb r0, r3 + 8006bc4: 2300 movs r3, #0 + 8006bc6: 4a13 ldr r2, [pc, #76] ; (8006c14 ) + 8006bc8: 2100 movs r1, #0 + 8006bca: f002 fb88 bl 80092de + ssd1306_update(); + 8006bce: f002 fa5f bl 8009090 +} + 8006bd2: bf00 nop + 8006bd4: bd80 pop {r7, pc} + 8006bd6: bf00 nop + 8006bd8: 0800cc3c .word 0x0800cc3c + 8006bdc: 0800cc4c .word 0x0800cc4c + 8006be0: 200007e0 .word 0x200007e0 + 8006be4: 20000810 .word 0x20000810 + 8006be8: 0800cc5c .word 0x0800cc5c + 8006bec: 0800cc68 .word 0x0800cc68 + 8006bf0: 0800cc78 .word 0x0800cc78 + 8006bf4: 2000080c .word 0x2000080c + 8006bf8: 0800cc84 .word 0x0800cc84 + 8006bfc: 0800cc88 .word 0x0800cc88 + 8006c00: 200007cc .word 0x200007cc + 8006c04: 0800cc98 .word 0x0800cc98 + 8006c08: 0800cc9c .word 0x0800cc9c + 8006c0c: 0800cca8 .word 0x0800cca8 + 8006c10: 0800ccb4 .word 0x0800ccb4 + 8006c14: 0800ca14 .word 0x0800ca14 + +08006c18 : + + + +//SET DEV NUM +void draw_set_dev_num(void) +{ + 8006c18: b580 push {r7, lr} + 8006c1a: af00 add r7, sp, #0 + #define SET_DEV_NUM_ROW (2) + #define SET_DEV_NUM_COL (1) + #define SET_DEV_NUM_PARAM_COL (15) + + ssd1306_clear(); + 8006c1c: f002 fa58 bl 80090d0 + ssd1306_print(0, SET_DEV_NUM_COL, "SET DEV NUM", 0); + 8006c20: 2300 movs r3, #0 + 8006c22: 4a10 ldr r2, [pc, #64] ; (8006c64 ) + 8006c24: 2101 movs r1, #1 + 8006c26: 2000 movs r0, #0 + 8006c28: f002 fb59 bl 80092de + + ssd1306_print(SET_DEV_NUM_ROW, SET_DEV_NUM_COL, "Device number", 0); + 8006c2c: 2300 movs r3, #0 + 8006c2e: 4a0e ldr r2, [pc, #56] ; (8006c68 ) + 8006c30: 2101 movs r1, #1 + 8006c32: 2002 movs r0, #2 + 8006c34: f002 fb53 bl 80092de + itoa32(settings_copy.device_number, &buf[0]); + 8006c38: 4b0c ldr r3, [pc, #48] ; (8006c6c ) + 8006c3a: 781b ldrb r3, [r3, #0] + 8006c3c: 490c ldr r1, [pc, #48] ; (8006c70 ) + 8006c3e: 4618 mov r0, r3 + 8006c40: f001 fdea bl 8008818 + ssd1306_print(SET_DEV_NUM_ROW, SET_DEV_NUM_PARAM_COL, &buf[0], 0); + 8006c44: 2300 movs r3, #0 + 8006c46: 4a0a ldr r2, [pc, #40] ; (8006c70 ) + 8006c48: 210f movs r1, #15 + 8006c4a: 2002 movs r0, #2 + 8006c4c: f002 fb47 bl 80092de + ssd1306_print(SET_DEV_NUM_ROW + 1, SET_DEV_NUM_PARAM_COL, "^", 0); + 8006c50: 2300 movs r3, #0 + 8006c52: 4a08 ldr r2, [pc, #32] ; (8006c74 ) + 8006c54: 210f movs r1, #15 + 8006c56: 2003 movs r0, #3 + 8006c58: f002 fb41 bl 80092de + ssd1306_update(); + 8006c5c: f002 fa18 bl 8009090 +} + 8006c60: bf00 nop + 8006c62: bd80 pop {r7, pc} + 8006c64: 0800ccb8 .word 0x0800ccb8 + 8006c68: 0800cc4c .word 0x0800cc4c + 8006c6c: 200007e0 .word 0x200007e0 + 8006c70: 20000810 .word 0x20000810 + 8006c74: 0800cb60 .word 0x0800cb60 + +08006c78 : + + + +//SET DEV ID +void draw_set_dev_id(void) +{ + 8006c78: b580 push {r7, lr} + 8006c7a: af00 add r7, sp, #0 + #define SET_DEV_ID_ROW (2) + #define SET_DEV_ID_COL (1) + #define SET_DEV_ID_PARAM_COL (15) + + ssd1306_clear(); + 8006c7c: f002 fa28 bl 80090d0 + ssd1306_print(0, SET_DEV_NUM_COL, "SET DEV ID", 0); + 8006c80: 2300 movs r3, #0 + 8006c82: 4a17 ldr r2, [pc, #92] ; (8006ce0 ) + 8006c84: 2101 movs r1, #1 + 8006c86: 2000 movs r0, #0 + 8006c88: f002 fb29 bl 80092de + + ssd1306_print(SET_DEV_ID_ROW, SET_DEV_ID_COL, "Device ID", 0); + 8006c8c: 2300 movs r3, #0 + 8006c8e: 4a15 ldr r2, [pc, #84] ; (8006ce4 ) + 8006c90: 2101 movs r1, #1 + 8006c92: 2002 movs r0, #2 + 8006c94: f002 fb23 bl 80092de + buf[0] = settings_copy.device_id[0]; + 8006c98: 4b13 ldr r3, [pc, #76] ; (8006ce8 ) + 8006c9a: 785a ldrb r2, [r3, #1] + 8006c9c: 4b13 ldr r3, [pc, #76] ; (8006cec ) + 8006c9e: 701a strb r2, [r3, #0] + buf[1] = settings_copy.device_id[1]; + 8006ca0: 4b11 ldr r3, [pc, #68] ; (8006ce8 ) + 8006ca2: 789a ldrb r2, [r3, #2] + 8006ca4: 4b11 ldr r3, [pc, #68] ; (8006cec ) + 8006ca6: 705a strb r2, [r3, #1] + buf[2] = 0; + 8006ca8: 4b10 ldr r3, [pc, #64] ; (8006cec ) + 8006caa: 2200 movs r2, #0 + 8006cac: 709a strb r2, [r3, #2] + ssd1306_print(SET_DEV_ID_ROW, SET_DEV_ID_PARAM_COL, &buf[0], 0); + 8006cae: 2300 movs r3, #0 + 8006cb0: 4a0e ldr r2, [pc, #56] ; (8006cec ) + 8006cb2: 210f movs r1, #15 + 8006cb4: 2002 movs r0, #2 + 8006cb6: f002 fb12 bl 80092de + ssd1306_print(SET_DEV_ID_ROW + 1, SET_DEV_ID_PARAM_COL + device_id_current_symbol, "^", 0); + 8006cba: 4b0d ldr r3, [pc, #52] ; (8006cf0 ) + 8006cbc: 781b ldrb r3, [r3, #0] + 8006cbe: 330f adds r3, #15 + 8006cc0: b2d9 uxtb r1, r3 + 8006cc2: 2300 movs r3, #0 + 8006cc4: 4a0b ldr r2, [pc, #44] ; (8006cf4 ) + 8006cc6: 2003 movs r0, #3 + 8006cc8: f002 fb09 bl 80092de + ssd1306_print(SET_DEV_ID_ROW + 3, SET_DEV_ID_COL, "Long OK - apply", 0); + 8006ccc: 2300 movs r3, #0 + 8006cce: 4a0a ldr r2, [pc, #40] ; (8006cf8 ) + 8006cd0: 2101 movs r1, #1 + 8006cd2: 2005 movs r0, #5 + 8006cd4: f002 fb03 bl 80092de + ssd1306_update(); + 8006cd8: f002 f9da bl 8009090 +} + 8006cdc: bf00 nop + 8006cde: bd80 pop {r7, pc} + 8006ce0: 0800ccc4 .word 0x0800ccc4 + 8006ce4: 0800cc5c .word 0x0800cc5c + 8006ce8: 200007e0 .word 0x200007e0 + 8006cec: 20000810 .word 0x20000810 + 8006cf0: 2000011f .word 0x2000011f + 8006cf4: 0800cb60 .word 0x0800cb60 + 8006cf8: 0800ccd0 .word 0x0800ccd0 + +08006cfc : + + + +//SET FREQ CH +void draw_set_freq_ch(void) +{ + 8006cfc: b580 push {r7, lr} + 8006cfe: af00 add r7, sp, #0 + #define SET_FREQ_CH_ROW (2) + #define SET_FREQ_CH_COL (1) + #define SET_FREQ_CH_PARAM_COL (16) + + ssd1306_clear(); + 8006d00: f002 f9e6 bl 80090d0 + ssd1306_print(0, SET_FREQ_CH_COL, "SET FREQ CH", 0); + 8006d04: 2300 movs r3, #0 + 8006d06: 4a10 ldr r2, [pc, #64] ; (8006d48 ) + 8006d08: 2101 movs r1, #1 + 8006d0a: 2000 movs r0, #0 + 8006d0c: f002 fae7 bl 80092de + + ssd1306_print(SET_FREQ_CH_ROW, SET_FREQ_CH_COL, "Freq channel", 0); + 8006d10: 2300 movs r3, #0 + 8006d12: 4a0e ldr r2, [pc, #56] ; (8006d4c ) + 8006d14: 2101 movs r1, #1 + 8006d16: 2002 movs r0, #2 + 8006d18: f002 fae1 bl 80092de + itoa32(settings_copy.freq_channel, &buf[0]); + 8006d1c: 4b0c ldr r3, [pc, #48] ; (8006d50 ) + 8006d1e: 78db ldrb r3, [r3, #3] + 8006d20: 490c ldr r1, [pc, #48] ; (8006d54 ) + 8006d22: 4618 mov r0, r3 + 8006d24: f001 fd78 bl 8008818 + ssd1306_print_viceversa(SET_FREQ_CH_ROW, SET_FREQ_CH_PARAM_COL, &buf[0], 0); + 8006d28: 2300 movs r3, #0 + 8006d2a: 4a0a ldr r2, [pc, #40] ; (8006d54 ) + 8006d2c: 2110 movs r1, #16 + 8006d2e: 2002 movs r0, #2 + 8006d30: f002 faf8 bl 8009324 + ssd1306_print(SET_FREQ_CH_ROW + 1, SET_FREQ_CH_PARAM_COL, "^", 0); + 8006d34: 2300 movs r3, #0 + 8006d36: 4a08 ldr r2, [pc, #32] ; (8006d58 ) + 8006d38: 2110 movs r1, #16 + 8006d3a: 2003 movs r0, #3 + 8006d3c: f002 facf bl 80092de + ssd1306_update(); + 8006d40: f002 f9a6 bl 8009090 +} + 8006d44: bf00 nop + 8006d46: bd80 pop {r7, pc} + 8006d48: 0800cce0 .word 0x0800cce0 + 8006d4c: 0800cc68 .word 0x0800cc68 + 8006d50: 200007e0 .word 0x200007e0 + 8006d54: 20000810 .word 0x20000810 + 8006d58: 0800cb60 .word 0x0800cb60 + +08006d5c : + + + +//SET TX POW +void draw_set_tx_pow(void) +{ + 8006d5c: b580 push {r7, lr} + 8006d5e: af00 add r7, sp, #0 + #define SET_TX_POW_ROW (2) + #define SET_TX_POW_COL (1) + #define SET_TX_POW_PARAM_COL (15) + + ssd1306_clear(); + 8006d60: f002 f9b6 bl 80090d0 + ssd1306_print(0, SET_TX_POW_COL, "SET TX POW", 0); + 8006d64: 2300 movs r3, #0 + 8006d66: 4a14 ldr r2, [pc, #80] ; (8006db8 ) + 8006d68: 2101 movs r1, #1 + 8006d6a: 2000 movs r0, #0 + 8006d6c: f002 fab7 bl 80092de + + ssd1306_print(SET_TX_POW_ROW, SET_TX_POW_COL, "TX power", 0); + 8006d70: 2300 movs r3, #0 + 8006d72: 4a12 ldr r2, [pc, #72] ; (8006dbc ) + 8006d74: 2101 movs r1, #1 + 8006d76: 2002 movs r0, #2 + 8006d78: f002 fab1 bl 80092de + itoa32(p_get_tx_power_values[settings_copy.tx_power_opt], &buf[0]); + 8006d7c: 4b10 ldr r3, [pc, #64] ; (8006dc0 ) + 8006d7e: 681b ldr r3, [r3, #0] + 8006d80: 4a10 ldr r2, [pc, #64] ; (8006dc4 ) + 8006d82: 7912 ldrb r2, [r2, #4] + 8006d84: 4413 add r3, r2 + 8006d86: 781b ldrb r3, [r3, #0] + 8006d88: 490f ldr r1, [pc, #60] ; (8006dc8 ) + 8006d8a: 4618 mov r0, r3 + 8006d8c: f001 fd44 bl 8008818 + ssd1306_print(SET_TX_POW_ROW, SET_TX_POW_PARAM_COL, &buf[0], 0); + 8006d90: 2300 movs r3, #0 + 8006d92: 4a0d ldr r2, [pc, #52] ; (8006dc8 ) + 8006d94: 210f movs r1, #15 + 8006d96: 2002 movs r0, #2 + 8006d98: f002 faa1 bl 80092de + ssd1306_print_next(" mW", 0); + 8006d9c: 2100 movs r1, #0 + 8006d9e: 480b ldr r0, [pc, #44] ; (8006dcc ) + 8006da0: f002 fafc bl 800939c + ssd1306_print(SET_TX_POW_ROW + 1, SET_TX_POW_PARAM_COL, "^", 0); + 8006da4: 2300 movs r3, #0 + 8006da6: 4a0a ldr r2, [pc, #40] ; (8006dd0 ) + 8006da8: 210f movs r1, #15 + 8006daa: 2003 movs r0, #3 + 8006dac: f002 fa97 bl 80092de + ssd1306_update(); + 8006db0: f002 f96e bl 8009090 +} + 8006db4: bf00 nop + 8006db6: bd80 pop {r7, pc} + 8006db8: 0800ccec .word 0x0800ccec + 8006dbc: 0800cc78 .word 0x0800cc78 + 8006dc0: 2000080c .word 0x2000080c + 8006dc4: 200007e0 .word 0x200007e0 + 8006dc8: 20000810 .word 0x20000810 + 8006dcc: 0800cc84 .word 0x0800cc84 + 8006dd0: 0800cb60 .word 0x0800cb60 + +08006dd4 : + + + +//SET SEND INTRVL +void draw_set_send_intvl(void) +{ + 8006dd4: b580 push {r7, lr} + 8006dd6: af00 add r7, sp, #0 + #define SET_SEND_INTVL_ROW (2) + #define SET_SEND_INTVL_COL (1) + #define SET_SEND_INTVL_PARAM_COL (16) + + ssd1306_clear(); + 8006dd8: f002 f97a bl 80090d0 + ssd1306_print(0, SET_SEND_INTVL_COL, "SET SEND INTVL", 0); + 8006ddc: 2300 movs r3, #0 + 8006dde: 4a14 ldr r2, [pc, #80] ; (8006e30 ) + 8006de0: 2101 movs r1, #1 + 8006de2: 2000 movs r0, #0 + 8006de4: f002 fa7b bl 80092de + + ssd1306_print(SET_SEND_INTVL_ROW, SET_SEND_INTVL_COL, "Send interval", 0); + 8006de8: 2300 movs r3, #0 + 8006dea: 4a12 ldr r2, [pc, #72] ; (8006e34 ) + 8006dec: 2101 movs r1, #1 + 8006dee: 2002 movs r0, #2 + 8006df0: f002 fa75 bl 80092de + itoa32(p_send_interval_values[settings_copy.send_interval_opt], &buf[0]); + 8006df4: 4b10 ldr r3, [pc, #64] ; (8006e38 ) + 8006df6: 681b ldr r3, [r3, #0] + 8006df8: 4a10 ldr r2, [pc, #64] ; (8006e3c ) + 8006dfa: 7952 ldrb r2, [r2, #5] + 8006dfc: 4413 add r3, r2 + 8006dfe: 781b ldrb r3, [r3, #0] + 8006e00: 490f ldr r1, [pc, #60] ; (8006e40 ) + 8006e02: 4618 mov r0, r3 + 8006e04: f001 fd08 bl 8008818 + ssd1306_print(SET_SEND_INTVL_ROW, SET_SEND_INTVL_PARAM_COL, &buf[0], 0); + 8006e08: 2300 movs r3, #0 + 8006e0a: 4a0d ldr r2, [pc, #52] ; (8006e40 ) + 8006e0c: 2110 movs r1, #16 + 8006e0e: 2002 movs r0, #2 + 8006e10: f002 fa65 bl 80092de + ssd1306_print_next(" s", 0); + 8006e14: 2100 movs r1, #0 + 8006e16: 480b ldr r0, [pc, #44] ; (8006e44 ) + 8006e18: f002 fac0 bl 800939c + ssd1306_print(SET_SEND_INTVL_ROW + 1, SET_SEND_INTVL_PARAM_COL, "^", 0); + 8006e1c: 2300 movs r3, #0 + 8006e1e: 4a0a ldr r2, [pc, #40] ; (8006e48 ) + 8006e20: 2110 movs r1, #16 + 8006e22: 2003 movs r0, #3 + 8006e24: f002 fa5b bl 80092de + ssd1306_update(); + 8006e28: f002 f932 bl 8009090 +} + 8006e2c: bf00 nop + 8006e2e: bd80 pop {r7, pc} + 8006e30: 0800ccf8 .word 0x0800ccf8 + 8006e34: 0800cc88 .word 0x0800cc88 + 8006e38: 200007cc .word 0x200007cc + 8006e3c: 200007e0 .word 0x200007e0 + 8006e40: 20000810 .word 0x20000810 + 8006e44: 0800cc98 .word 0x0800cc98 + 8006e48: 0800cb60 .word 0x0800cb60 + +08006e4c : + + + +//SET TIMEOUT THR +void draw_set_to_thr(void) +{ + 8006e4c: b580 push {r7, lr} + 8006e4e: af00 add r7, sp, #0 + #define SET_TO_THR_ROW (2) + #define SET_TO_THR_COL (1) + #define SET_TO_THR_PARAM_COL (14) + + ssd1306_clear(); + 8006e50: f002 f93e bl 80090d0 + ssd1306_print(0, SET_TO_THR_COL, "SET TO THR", 0); + 8006e54: 2300 movs r3, #0 + 8006e56: 4a12 ldr r2, [pc, #72] ; (8006ea0 ) + 8006e58: 2101 movs r1, #1 + 8006e5a: 2000 movs r0, #0 + 8006e5c: f002 fa3f bl 80092de + + ssd1306_print(SET_TO_THR_ROW, SET_TO_THR_COL, "Timeout thr", 0); + 8006e60: 2300 movs r3, #0 + 8006e62: 4a10 ldr r2, [pc, #64] ; (8006ea4 ) + 8006e64: 2101 movs r1, #1 + 8006e66: 2002 movs r0, #2 + 8006e68: f002 fa39 bl 80092de + itoa32(settings_copy.timeout_threshold.as_integer, &buf[0]); + 8006e6c: 4b0e ldr r3, [pc, #56] ; (8006ea8 ) + 8006e6e: 88db ldrh r3, [r3, #6] + 8006e70: 490e ldr r1, [pc, #56] ; (8006eac ) + 8006e72: 4618 mov r0, r3 + 8006e74: f001 fcd0 bl 8008818 + ssd1306_print(SET_TO_THR_ROW, SET_TO_THR_PARAM_COL, &buf[0], 0); + 8006e78: 2300 movs r3, #0 + 8006e7a: 4a0c ldr r2, [pc, #48] ; (8006eac ) + 8006e7c: 210e movs r1, #14 + 8006e7e: 2002 movs r0, #2 + 8006e80: f002 fa2d bl 80092de + ssd1306_print_next(" s", 0); + 8006e84: 2100 movs r1, #0 + 8006e86: 480a ldr r0, [pc, #40] ; (8006eb0 ) + 8006e88: f002 fa88 bl 800939c + ssd1306_print(SET_TO_THR_ROW + 1, SET_TO_THR_PARAM_COL, "^", 0); + 8006e8c: 2300 movs r3, #0 + 8006e8e: 4a09 ldr r2, [pc, #36] ; (8006eb4 ) + 8006e90: 210e movs r1, #14 + 8006e92: 2003 movs r0, #3 + 8006e94: f002 fa23 bl 80092de + ssd1306_update(); + 8006e98: f002 f8fa bl 8009090 +} + 8006e9c: bf00 nop + 8006e9e: bd80 pop {r7, pc} + 8006ea0: 0800cd08 .word 0x0800cd08 + 8006ea4: 0800cc9c .word 0x0800cc9c + 8006ea8: 200007e0 .word 0x200007e0 + 8006eac: 20000810 .word 0x20000810 + 8006eb0: 0800cc98 .word 0x0800cc98 + 8006eb4: 0800cb60 .word 0x0800cb60 + +08006eb8 : + + + +//SET TIMEOUT THR +void draw_set_fnc_thr(void) +{ + 8006eb8: b580 push {r7, lr} + 8006eba: af00 add r7, sp, #0 + #define SET_FNC_THR_ROW (2) + #define SET_FNC_THR_COL (1) + #define SET_FNC_THR_PARAM_COL (14) + + ssd1306_clear(); + 8006ebc: f002 f908 bl 80090d0 + ssd1306_print(0, SET_FNC_THR_COL, "SET FNC THR", 0); + 8006ec0: 2300 movs r3, #0 + 8006ec2: 4a12 ldr r2, [pc, #72] ; (8006f0c ) + 8006ec4: 2101 movs r1, #1 + 8006ec6: 2000 movs r0, #0 + 8006ec8: f002 fa09 bl 80092de + + ssd1306_print(SET_FNC_THR_ROW, SET_FNC_THR_COL, "Fence thr", 0); + 8006ecc: 2300 movs r3, #0 + 8006ece: 4a10 ldr r2, [pc, #64] ; (8006f10 ) + 8006ed0: 2101 movs r1, #1 + 8006ed2: 2002 movs r0, #2 + 8006ed4: f002 fa03 bl 80092de + itoa32(settings_copy.fence_threshold.as_integer, &buf[0]); + 8006ed8: 4b0e ldr r3, [pc, #56] ; (8006f14 ) + 8006eda: 891b ldrh r3, [r3, #8] + 8006edc: 490e ldr r1, [pc, #56] ; (8006f18 ) + 8006ede: 4618 mov r0, r3 + 8006ee0: f001 fc9a bl 8008818 + ssd1306_print(SET_FNC_THR_ROW, SET_FNC_THR_PARAM_COL, &buf[0], 0); + 8006ee4: 2300 movs r3, #0 + 8006ee6: 4a0c ldr r2, [pc, #48] ; (8006f18 ) + 8006ee8: 210e movs r1, #14 + 8006eea: 2002 movs r0, #2 + 8006eec: f002 f9f7 bl 80092de + ssd1306_print_next(" m", 0); + 8006ef0: 2100 movs r1, #0 + 8006ef2: 480a ldr r0, [pc, #40] ; (8006f1c ) + 8006ef4: f002 fa52 bl 800939c + ssd1306_print(SET_FNC_THR_ROW + 1, SET_FNC_THR_PARAM_COL, "^", 0); + 8006ef8: 2300 movs r3, #0 + 8006efa: 4a09 ldr r2, [pc, #36] ; (8006f20 ) + 8006efc: 210e movs r1, #14 + 8006efe: 2003 movs r0, #3 + 8006f00: f002 f9ed bl 80092de + ssd1306_update(); + 8006f04: f002 f8c4 bl 8009090 +} + 8006f08: bf00 nop + 8006f0a: bd80 pop {r7, pc} + 8006f0c: 0800cd14 .word 0x0800cd14 + 8006f10: 0800cca8 .word 0x0800cca8 + 8006f14: 200007e0 .word 0x200007e0 + 8006f18: 20000810 .word 0x20000810 + 8006f1c: 0800ccb4 .word 0x0800ccb4 + 8006f20: 0800cb60 .word 0x0800cb60 + +08006f24 : + + + +//CONFIRM SETTINGS SAVE +void draw_confirm_settings_save(void) +{ + 8006f24: b580 push {r7, lr} + 8006f26: af00 add r7, sp, #0 + if (flag_settings_changed) + 8006f28: 4b10 ldr r3, [pc, #64] ; (8006f6c ) + 8006f2a: 781b ldrb r3, [r3, #0] + 8006f2c: 2b00 cmp r3, #0 + 8006f2e: d016 beq.n 8006f5e + { + ssd1306_clear(); + 8006f30: f002 f8ce bl 80090d0 + ssd1306_print(0, 1, "Settings changed", 0); + 8006f34: 2300 movs r3, #0 + 8006f36: 4a0e ldr r2, [pc, #56] ; (8006f70 ) + 8006f38: 2101 movs r1, #1 + 8006f3a: 2000 movs r0, #0 + 8006f3c: f002 f9cf bl 80092de + ssd1306_print(3, 1, "OK - save & restart", 0); + 8006f40: 2300 movs r3, #0 + 8006f42: 4a0c ldr r2, [pc, #48] ; (8006f74 ) + 8006f44: 2101 movs r1, #1 + 8006f46: 2003 movs r0, #3 + 8006f48: f002 f9c9 bl 80092de + ssd1306_print(4, 1, "ESC - cancel changes", 0); + 8006f4c: 2300 movs r3, #0 + 8006f4e: 4a0a ldr r2, [pc, #40] ; (8006f78 ) + 8006f50: 2101 movs r1, #1 + 8006f52: 2004 movs r0, #4 + 8006f54: f002 f9c3 bl 80092de + ssd1306_update(); + 8006f58: f002 f89a bl 8009090 + else + { + current_menu = M_SETTINGS; + draw_current_menu(); + } +} + 8006f5c: e004 b.n 8006f68 + current_menu = M_SETTINGS; + 8006f5e: 4b07 ldr r3, [pc, #28] ; (8006f7c ) + 8006f60: 220e movs r2, #14 + 8006f62: 701a strb r2, [r3, #0] + draw_current_menu(); + 8006f64: f7fd f9c0 bl 80042e8 +} + 8006f68: bf00 nop + 8006f6a: bd80 pop {r7, pc} + 8006f6c: 2000011e .word 0x2000011e + 8006f70: 0800cd20 .word 0x0800cd20 + 8006f74: 0800cd34 .word 0x0800cd34 + 8006f78: 0800cd48 .word 0x0800cd48 + 8006f7c: 200007fa .word 0x200007fa + +08006f80 : + + + +//RESTORE DEFAULTS +void draw_restore_defaults(void) +{ + 8006f80: b580 push {r7, lr} + 8006f82: af00 add r7, sp, #0 + ssd1306_clear(); + 8006f84: f002 f8a4 bl 80090d0 + ssd1306_print(0, 1, "Restore defaults?", 0); + 8006f88: 2300 movs r3, #0 + 8006f8a: 4a0a ldr r2, [pc, #40] ; (8006fb4 ) + 8006f8c: 2101 movs r1, #1 + 8006f8e: 2000 movs r0, #0 + 8006f90: f002 f9a5 bl 80092de + ssd1306_print(3, 1, "OK - restore & reset", 0); + 8006f94: 2300 movs r3, #0 + 8006f96: 4a08 ldr r2, [pc, #32] ; (8006fb8 ) + 8006f98: 2101 movs r1, #1 + 8006f9a: 2003 movs r0, #3 + 8006f9c: f002 f99f bl 80092de + ssd1306_print(4, 1, "ESC - cancel", 0); + 8006fa0: 2300 movs r3, #0 + 8006fa2: 4a06 ldr r2, [pc, #24] ; (8006fbc ) + 8006fa4: 2101 movs r1, #1 + 8006fa6: 2004 movs r0, #4 + 8006fa8: f002 f999 bl 80092de + ssd1306_update(); + 8006fac: f002 f870 bl 8009090 +} + 8006fb0: bf00 nop + 8006fb2: bd80 pop {r7, pc} + 8006fb4: 0800cd60 .word 0x0800cd60 + 8006fb8: 0800cd74 .word 0x0800cd74 + 8006fbc: 0800cb18 .word 0x0800cb18 + +08006fc0 : + + + +//ERASE ALL +void draw_erase_all(void) +{ + 8006fc0: b580 push {r7, lr} + 8006fc2: af00 add r7, sp, #0 + ssd1306_clear(); + 8006fc4: f002 f884 bl 80090d0 + ssd1306_print(0, 1, "Erase all EEPROM?", 0); + 8006fc8: 2300 movs r3, #0 + 8006fca: 4a0a ldr r2, [pc, #40] ; (8006ff4 ) + 8006fcc: 2101 movs r1, #1 + 8006fce: 2000 movs r0, #0 + 8006fd0: f002 f985 bl 80092de + ssd1306_print(3, 1, "OK - erase & reset", 0); + 8006fd4: 2300 movs r3, #0 + 8006fd6: 4a08 ldr r2, [pc, #32] ; (8006ff8 ) + 8006fd8: 2101 movs r1, #1 + 8006fda: 2003 movs r0, #3 + 8006fdc: f002 f97f bl 80092de + ssd1306_print(4, 1, "ESC - cancel", 0); + 8006fe0: 2300 movs r3, #0 + 8006fe2: 4a06 ldr r2, [pc, #24] ; (8006ffc ) + 8006fe4: 2101 movs r1, #1 + 8006fe6: 2004 movs r0, #4 + 8006fe8: f002 f979 bl 80092de + ssd1306_update(); + 8006fec: f002 f850 bl 8009090 +} + 8006ff0: bf00 nop + 8006ff2: bd80 pop {r7, pc} + 8006ff4: 0800cd8c .word 0x0800cd8c + 8006ff8: 0800cda0 .word 0x0800cda0 + 8006ffc: 0800cb18 .word 0x0800cb18 + +08007000 : + + + +void devices_ok(void) +{ + 8007000: b580 push {r7, lr} + 8007002: af00 add r7, sp, #0 + if (pp_dev_aux[current_each_device]->exist_flag == 0) + 8007004: 4b09 ldr r3, [pc, #36] ; (800702c ) + 8007006: 681a ldr r2, [r3, #0] + 8007008: 4b09 ldr r3, [pc, #36] ; (8007030 ) + 800700a: 781b ldrb r3, [r3, #0] + 800700c: 009b lsls r3, r3, #2 + 800700e: 4413 add r3, r2 + 8007010: 681b ldr r3, [r3, #0] + 8007012: 781b ldrb r3, [r3, #0] + 8007014: 2b00 cmp r3, #0 + 8007016: d101 bne.n 800701c + { + each_device_up(); + 8007018: f000 f80e bl 8007038 + } + + current_menu = M_EACH_DEVICE; + 800701c: 4b05 ldr r3, [pc, #20] ; (8007034 ) + 800701e: 2203 movs r2, #3 + 8007020: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007022: f7fd f961 bl 80042e8 +} + 8007026: bf00 nop + 8007028: bd80 pop {r7, pc} + 800702a: bf00 nop + 800702c: 2000083c .word 0x2000083c + 8007030: 20000032 .word 0x20000032 + 8007034: 200007fa .word 0x200007fa + +08007038 : + + + +void each_device_up(void) +{ + 8007038: b580 push {r7, lr} + 800703a: af00 add r7, sp, #0 + do + { + if (current_each_device == DEVICE_NUMBER_FIRST) + 800703c: 4b0d ldr r3, [pc, #52] ; (8007074 ) + 800703e: 781b ldrb r3, [r3, #0] + 8007040: 2b01 cmp r3, #1 + 8007042: d103 bne.n 800704c + { + current_each_device = DEVICE_NUMBER_LAST; + 8007044: 4b0b ldr r3, [pc, #44] ; (8007074 ) + 8007046: 2206 movs r2, #6 + 8007048: 701a strb r2, [r3, #0] + 800704a: e005 b.n 8007058 + } + else + { + current_each_device--; + 800704c: 4b09 ldr r3, [pc, #36] ; (8007074 ) + 800704e: 781b ldrb r3, [r3, #0] + 8007050: 3b01 subs r3, #1 + 8007052: b2da uxtb r2, r3 + 8007054: 4b07 ldr r3, [pc, #28] ; (8007074 ) + 8007056: 701a strb r2, [r3, #0] + } + } + while (pp_dev_aux[current_each_device]->exist_flag == 0); + 8007058: 4b07 ldr r3, [pc, #28] ; (8007078 ) + 800705a: 681a ldr r2, [r3, #0] + 800705c: 4b05 ldr r3, [pc, #20] ; (8007074 ) + 800705e: 781b ldrb r3, [r3, #0] + 8007060: 009b lsls r3, r3, #2 + 8007062: 4413 add r3, r2 + 8007064: 681b ldr r3, [r3, #0] + 8007066: 781b ldrb r3, [r3, #0] + 8007068: 2b00 cmp r3, #0 + 800706a: d0e7 beq.n 800703c + + draw_current_menu(); + 800706c: f7fd f93c bl 80042e8 +} + 8007070: bf00 nop + 8007072: bd80 pop {r7, pc} + 8007074: 20000032 .word 0x20000032 + 8007078: 2000083c .word 0x2000083c + +0800707c : + + + +void each_device_down(void) +{ + 800707c: b580 push {r7, lr} + 800707e: af00 add r7, sp, #0 + do + { + if (current_each_device == DEVICE_NUMBER_LAST) + 8007080: 4b0d ldr r3, [pc, #52] ; (80070b8 ) + 8007082: 781b ldrb r3, [r3, #0] + 8007084: 2b06 cmp r3, #6 + 8007086: d103 bne.n 8007090 + { + current_each_device = DEVICE_NUMBER_FIRST; + 8007088: 4b0b ldr r3, [pc, #44] ; (80070b8 ) + 800708a: 2201 movs r2, #1 + 800708c: 701a strb r2, [r3, #0] + 800708e: e005 b.n 800709c + } + else + { + current_each_device++; + 8007090: 4b09 ldr r3, [pc, #36] ; (80070b8 ) + 8007092: 781b ldrb r3, [r3, #0] + 8007094: 3301 adds r3, #1 + 8007096: b2da uxtb r2, r3 + 8007098: 4b07 ldr r3, [pc, #28] ; (80070b8 ) + 800709a: 701a strb r2, [r3, #0] + } + } + while (pp_dev_aux[current_each_device]->exist_flag == 0); + 800709c: 4b07 ldr r3, [pc, #28] ; (80070bc ) + 800709e: 681a ldr r2, [r3, #0] + 80070a0: 4b05 ldr r3, [pc, #20] ; (80070b8 ) + 80070a2: 781b ldrb r3, [r3, #0] + 80070a4: 009b lsls r3, r3, #2 + 80070a6: 4413 add r3, r2 + 80070a8: 681b ldr r3, [r3, #0] + 80070aa: 781b ldrb r3, [r3, #0] + 80070ac: 2b00 cmp r3, #0 + 80070ae: d0e7 beq.n 8007080 + + draw_current_menu(); + 80070b0: f7fd f91a bl 80042e8 +} + 80070b4: bf00 nop + 80070b6: bd80 pop {r7, pc} + 80070b8: 20000032 .word 0x20000032 + 80070bc: 2000083c .word 0x2000083c + +080070c0 : + + + +void each_device_ok(void) +{ + 80070c0: b580 push {r7, lr} + 80070c2: af00 add r7, sp, #0 + current_menu = M_EACH_DEVICE_SUBMENU; + 80070c4: 4b03 ldr r3, [pc, #12] ; (80070d4 ) + 80070c6: 2204 movs r2, #4 + 80070c8: 701a strb r2, [r3, #0] + draw_current_menu(); + 80070ca: f7fd f90d bl 80042e8 +} + 80070ce: bf00 nop + 80070d0: bd80 pop {r7, pc} + 80070d2: bf00 nop + 80070d4: 200007fa .word 0x200007fa + +080070d8 : + + + +void save_device_up(void) +{ + 80070d8: b580 push {r7, lr} + 80070da: af00 add r7, sp, #0 + if (current_slot_to_save != 0) + 80070dc: 4b0f ldr r3, [pc, #60] ; (800711c ) + 80070de: 781b ldrb r3, [r3, #0] + 80070e0: 2b00 cmp r3, #0 + 80070e2: d019 beq.n 8007118 + { + do + { + if (current_slot_to_save == MEMORY_SLOT_FIRST) + 80070e4: 4b0d ldr r3, [pc, #52] ; (800711c ) + 80070e6: 781b ldrb r3, [r3, #0] + 80070e8: 2b01 cmp r3, #1 + 80070ea: d103 bne.n 80070f4 + { + current_slot_to_save = MEMORY_SLOT_LAST; + 80070ec: 4b0b ldr r3, [pc, #44] ; (800711c ) + 80070ee: 2205 movs r2, #5 + 80070f0: 701a strb r2, [r3, #0] + 80070f2: e005 b.n 8007100 + } + else + { + current_slot_to_save--; + 80070f4: 4b09 ldr r3, [pc, #36] ; (800711c ) + 80070f6: 781b ldrb r3, [r3, #0] + 80070f8: 3b01 subs r3, #1 + 80070fa: b2da uxtb r2, r3 + 80070fc: 4b07 ldr r3, [pc, #28] ; (800711c ) + 80070fe: 701a strb r2, [r3, #0] + } + } + while (pp_memory_slot[current_slot_to_save]->exist_flag == 1); + 8007100: 4b07 ldr r3, [pc, #28] ; (8007120 ) + 8007102: 681a ldr r2, [r3, #0] + 8007104: 4b05 ldr r3, [pc, #20] ; (800711c ) + 8007106: 781b ldrb r3, [r3, #0] + 8007108: 009b lsls r3, r3, #2 + 800710a: 4413 add r3, r2 + 800710c: 681b ldr r3, [r3, #0] + 800710e: 781b ldrb r3, [r3, #0] + 8007110: 2b01 cmp r3, #1 + 8007112: d0e7 beq.n 80070e4 + + draw_current_menu(); + 8007114: f7fd f8e8 bl 80042e8 + } +} + 8007118: bf00 nop + 800711a: bd80 pop {r7, pc} + 800711c: 20000123 .word 0x20000123 + 8007120: 200007d4 .word 0x200007d4 + +08007124 : + + + +void save_device_down(void) +{ + 8007124: b580 push {r7, lr} + 8007126: af00 add r7, sp, #0 + if (current_slot_to_save != 0) + 8007128: 4b0f ldr r3, [pc, #60] ; (8007168 ) + 800712a: 781b ldrb r3, [r3, #0] + 800712c: 2b00 cmp r3, #0 + 800712e: d019 beq.n 8007164 + { + do + { + if (current_slot_to_save == MEMORY_SLOT_LAST) + 8007130: 4b0d ldr r3, [pc, #52] ; (8007168 ) + 8007132: 781b ldrb r3, [r3, #0] + 8007134: 2b05 cmp r3, #5 + 8007136: d103 bne.n 8007140 + { + current_slot_to_save = MEMORY_SLOT_FIRST; + 8007138: 4b0b ldr r3, [pc, #44] ; (8007168 ) + 800713a: 2201 movs r2, #1 + 800713c: 701a strb r2, [r3, #0] + 800713e: e005 b.n 800714c + } + else + { + current_slot_to_save++; + 8007140: 4b09 ldr r3, [pc, #36] ; (8007168 ) + 8007142: 781b ldrb r3, [r3, #0] + 8007144: 3301 adds r3, #1 + 8007146: b2da uxtb r2, r3 + 8007148: 4b07 ldr r3, [pc, #28] ; (8007168 ) + 800714a: 701a strb r2, [r3, #0] + } + } + while (pp_memory_slot[current_slot_to_save]->exist_flag == 1); + 800714c: 4b07 ldr r3, [pc, #28] ; (800716c ) + 800714e: 681a ldr r2, [r3, #0] + 8007150: 4b05 ldr r3, [pc, #20] ; (8007168 ) + 8007152: 781b ldrb r3, [r3, #0] + 8007154: 009b lsls r3, r3, #2 + 8007156: 4413 add r3, r2 + 8007158: 681b ldr r3, [r3, #0] + 800715a: 781b ldrb r3, [r3, #0] + 800715c: 2b01 cmp r3, #1 + 800715e: d0e7 beq.n 8007130 + + draw_current_menu(); + 8007160: f7fd f8c2 bl 80042e8 + } +} + 8007164: bf00 nop + 8007166: bd80 pop {r7, pc} + 8007168: 20000123 .word 0x20000123 + 800716c: 200007d4 .word 0x200007d4 + +08007170 : + + + +void save_device_ok(void) +{ + 8007170: b580 push {r7, lr} + 8007172: af00 add r7, sp, #0 + if (current_slot_to_save != 0) + 8007174: 4b05 ldr r3, [pc, #20] ; (800718c ) + 8007176: 781b ldrb r3, [r3, #0] + 8007178: 2b00 cmp r3, #0 + 800717a: d004 beq.n 8007186 + { + current_menu = M_SAVE_DEVICE_AS; + 800717c: 4b04 ldr r3, [pc, #16] ; (8007190 ) + 800717e: 2207 movs r2, #7 + 8007180: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007182: f7fd f8b1 bl 80042e8 + } +} + 8007186: bf00 nop + 8007188: bd80 pop {r7, pc} + 800718a: bf00 nop + 800718c: 20000123 .word 0x20000123 + 8007190: 200007fa .word 0x200007fa + +08007194 : + + + +void save_device_esc(void) +{ + 8007194: b580 push {r7, lr} + 8007196: af00 add r7, sp, #0 + current_slot_to_save = 0; + 8007198: 4b04 ldr r3, [pc, #16] ; (80071ac ) + 800719a: 2200 movs r2, #0 + 800719c: 701a strb r2, [r3, #0] + current_menu = M_EACH_DEVICE_SUBMENU; + 800719e: 4b04 ldr r3, [pc, #16] ; (80071b0 ) + 80071a0: 2204 movs r2, #4 + 80071a2: 701a strb r2, [r3, #0] + draw_current_menu(); + 80071a4: f7fd f8a0 bl 80042e8 +} + 80071a8: bf00 nop + 80071aa: bd80 pop {r7, pc} + 80071ac: 20000123 .word 0x20000123 + 80071b0: 200007fa .word 0x200007fa + +080071b4 : + + + +void save_device_as_up(void) +{ + 80071b4: b580 push {r7, lr} + 80071b6: af00 add r7, sp, #0 + if (point_to_save_name[point_name_current_symbol] == POINT_NAME_LAST_SYMBOL) + 80071b8: 4b0c ldr r3, [pc, #48] ; (80071ec ) + 80071ba: 781b ldrb r3, [r3, #0] + 80071bc: 461a mov r2, r3 + 80071be: 4b0c ldr r3, [pc, #48] ; (80071f0 ) + 80071c0: 5c9b ldrb r3, [r3, r2] + 80071c2: 2b7e cmp r3, #126 ; 0x7e + 80071c4: d106 bne.n 80071d4 + { + point_to_save_name[point_name_current_symbol] = POINT_NAME_FIRST_SYMBOL; + 80071c6: 4b09 ldr r3, [pc, #36] ; (80071ec ) + 80071c8: 781b ldrb r3, [r3, #0] + 80071ca: 461a mov r2, r3 + 80071cc: 4b08 ldr r3, [pc, #32] ; (80071f0 ) + 80071ce: 2120 movs r1, #32 + 80071d0: 5499 strb r1, [r3, r2] + 80071d2: e007 b.n 80071e4 + } + else + { + point_to_save_name[point_name_current_symbol]++; + 80071d4: 4b05 ldr r3, [pc, #20] ; (80071ec ) + 80071d6: 781b ldrb r3, [r3, #0] + 80071d8: 4a05 ldr r2, [pc, #20] ; (80071f0 ) + 80071da: 5cd2 ldrb r2, [r2, r3] + 80071dc: 3201 adds r2, #1 + 80071de: b2d1 uxtb r1, r2 + 80071e0: 4a03 ldr r2, [pc, #12] ; (80071f0 ) + 80071e2: 54d1 strb r1, [r2, r3] + } + + draw_current_menu(); + 80071e4: f7fd f880 bl 80042e8 +} + 80071e8: bf00 nop + 80071ea: bd80 pop {r7, pc} + 80071ec: 20000120 .word 0x20000120 + 80071f0: 20000828 .word 0x20000828 + +080071f4 : + + + +void save_device_as_down(void) +{ + 80071f4: b580 push {r7, lr} + 80071f6: af00 add r7, sp, #0 + if (point_to_save_name[point_name_current_symbol] == POINT_NAME_FIRST_SYMBOL) + 80071f8: 4b0c ldr r3, [pc, #48] ; (800722c ) + 80071fa: 781b ldrb r3, [r3, #0] + 80071fc: 461a mov r2, r3 + 80071fe: 4b0c ldr r3, [pc, #48] ; (8007230 ) + 8007200: 5c9b ldrb r3, [r3, r2] + 8007202: 2b20 cmp r3, #32 + 8007204: d106 bne.n 8007214 + { + point_to_save_name[point_name_current_symbol] = POINT_NAME_LAST_SYMBOL; + 8007206: 4b09 ldr r3, [pc, #36] ; (800722c ) + 8007208: 781b ldrb r3, [r3, #0] + 800720a: 461a mov r2, r3 + 800720c: 4b08 ldr r3, [pc, #32] ; (8007230 ) + 800720e: 217e movs r1, #126 ; 0x7e + 8007210: 5499 strb r1, [r3, r2] + 8007212: e007 b.n 8007224 + } + else + { + point_to_save_name[point_name_current_symbol]--; + 8007214: 4b05 ldr r3, [pc, #20] ; (800722c ) + 8007216: 781b ldrb r3, [r3, #0] + 8007218: 4a05 ldr r2, [pc, #20] ; (8007230 ) + 800721a: 5cd2 ldrb r2, [r2, r3] + 800721c: 3a01 subs r2, #1 + 800721e: b2d1 uxtb r1, r2 + 8007220: 4a03 ldr r2, [pc, #12] ; (8007230 ) + 8007222: 54d1 strb r1, [r2, r3] + } + + draw_current_menu(); + 8007224: f7fd f860 bl 80042e8 +} + 8007228: bf00 nop + 800722a: bd80 pop {r7, pc} + 800722c: 20000120 .word 0x20000120 + 8007230: 20000828 .word 0x20000828 + +08007234 : + + + +void save_device_as_ok(void) +{ + 8007234: b580 push {r7, lr} + 8007236: af00 add r7, sp, #0 + if (++point_name_current_symbol == MEMORY_POINT_NAME_LENGTH) + 8007238: 4b08 ldr r3, [pc, #32] ; (800725c ) + 800723a: 781b ldrb r3, [r3, #0] + 800723c: 3301 adds r3, #1 + 800723e: b2da uxtb r2, r3 + 8007240: 4b06 ldr r3, [pc, #24] ; (800725c ) + 8007242: 701a strb r2, [r3, #0] + 8007244: 4b05 ldr r3, [pc, #20] ; (800725c ) + 8007246: 781b ldrb r3, [r3, #0] + 8007248: 2b05 cmp r3, #5 + 800724a: d102 bne.n 8007252 + { + point_name_current_symbol = 0; + 800724c: 4b03 ldr r3, [pc, #12] ; (800725c ) + 800724e: 2200 movs r2, #0 + 8007250: 701a strb r2, [r3, #0] + } + + draw_current_menu(); + 8007252: f7fd f849 bl 80042e8 +} + 8007256: bf00 nop + 8007258: bd80 pop {r7, pc} + 800725a: bf00 nop + 800725c: 20000120 .word 0x20000120 + +08007260 : + + + +void save_device_as_ok_long(void) +{ + 8007260: b580 push {r7, lr} + 8007262: af00 add r7, sp, #0 + save_memory_point(current_each_device, &point_to_save_name[0], current_slot_to_save); + 8007264: 4b0c ldr r3, [pc, #48] ; (8007298 ) + 8007266: 7818 ldrb r0, [r3, #0] + 8007268: 4b0c ldr r3, [pc, #48] ; (800729c ) + 800726a: 781b ldrb r3, [r3, #0] + 800726c: 461a mov r2, r3 + 800726e: 490c ldr r1, [pc, #48] ; (80072a0 ) + 8007270: f000 fdf8 bl 8007e64 + + current_each_device = device_number; + 8007274: 4b0b ldr r3, [pc, #44] ; (80072a4 ) + 8007276: 781a ldrb r2, [r3, #0] + 8007278: 4b07 ldr r3, [pc, #28] ; (8007298 ) + 800727a: 701a strb r2, [r3, #0] + current_slot_to_save = 0; + 800727c: 4b07 ldr r3, [pc, #28] ; (800729c ) + 800727e: 2200 movs r2, #0 + 8007280: 701a strb r2, [r3, #0] + point_name_current_symbol = 0; + 8007282: 4b09 ldr r3, [pc, #36] ; (80072a8 ) + 8007284: 2200 movs r2, #0 + 8007286: 701a strb r2, [r3, #0] + + current_menu = M_SAVED_POPUP; + 8007288: 4b08 ldr r3, [pc, #32] ; (80072ac ) + 800728a: 2208 movs r2, #8 + 800728c: 701a strb r2, [r3, #0] + draw_current_menu(); + 800728e: f7fd f82b bl 80042e8 +} + 8007292: bf00 nop + 8007294: bd80 pop {r7, pc} + 8007296: bf00 nop + 8007298: 20000032 .word 0x20000032 + 800729c: 20000123 .word 0x20000123 + 80072a0: 20000828 .word 0x20000828 + 80072a4: 20000738 .word 0x20000738 + 80072a8: 20000120 .word 0x20000120 + 80072ac: 200007fa .word 0x200007fa + +080072b0 : + + + +void save_device_as_esc(void) +{ + 80072b0: b580 push {r7, lr} + 80072b2: af00 add r7, sp, #0 + point_name_current_symbol = 0; + 80072b4: 4b04 ldr r3, [pc, #16] ; (80072c8 ) + 80072b6: 2200 movs r2, #0 + 80072b8: 701a strb r2, [r3, #0] + current_menu = M_SAVE_DEVICE; + 80072ba: 4b04 ldr r3, [pc, #16] ; (80072cc ) + 80072bc: 2206 movs r2, #6 + 80072be: 701a strb r2, [r3, #0] + draw_current_menu(); + 80072c0: f7fd f812 bl 80042e8 +} + 80072c4: bf00 nop + 80072c6: bd80 pop {r7, pc} + 80072c8: 20000120 .word 0x20000120 + 80072cc: 200007fa .word 0x200007fa + +080072d0 : + + + +void saved_popup_esc(void) +{ + 80072d0: b580 push {r7, lr} + 80072d2: af00 add r7, sp, #0 + current_each_device = device_number; + 80072d4: 4b08 ldr r3, [pc, #32] ; (80072f8 ) + 80072d6: 781a ldrb r2, [r3, #0] + 80072d8: 4b08 ldr r3, [pc, #32] ; (80072fc ) + 80072da: 701a strb r2, [r3, #0] + current_slot_to_save = 0; + 80072dc: 4b08 ldr r3, [pc, #32] ; (8007300 ) + 80072de: 2200 movs r2, #0 + 80072e0: 701a strb r2, [r3, #0] + point_name_current_symbol = 0; + 80072e2: 4b08 ldr r3, [pc, #32] ; (8007304 ) + 80072e4: 2200 movs r2, #0 + 80072e6: 701a strb r2, [r3, #0] + + current_menu = M_DEVICES; + 80072e8: 4b07 ldr r3, [pc, #28] ; (8007308 ) + 80072ea: 2202 movs r2, #2 + 80072ec: 701a strb r2, [r3, #0] + draw_current_menu(); + 80072ee: f7fc fffb bl 80042e8 +} + 80072f2: bf00 nop + 80072f4: bd80 pop {r7, pc} + 80072f6: bf00 nop + 80072f8: 20000738 .word 0x20000738 + 80072fc: 20000032 .word 0x20000032 + 8007300: 20000123 .word 0x20000123 + 8007304: 20000120 .word 0x20000120 + 8007308: 200007fa .word 0x200007fa + +0800730c : + + + +void radar_up(void) +{ + 800730c: b580 push {r7, lr} + 800730e: af00 add r7, sp, #0 + if (current_radar_device != 0) + 8007310: 4b12 ldr r3, [pc, #72] ; (800735c ) + 8007312: 781b ldrb r3, [r3, #0] + 8007314: 2b00 cmp r3, #0 + 8007316: d01f beq.n 8007358 + { + do + { + do + { + if (current_radar_device == DEVICE_NUMBER_FIRST) + 8007318: 4b10 ldr r3, [pc, #64] ; (800735c ) + 800731a: 781b ldrb r3, [r3, #0] + 800731c: 2b01 cmp r3, #1 + 800731e: d103 bne.n 8007328 + { + current_radar_device = DEVICE_NUMBER_LAST; + 8007320: 4b0e ldr r3, [pc, #56] ; (800735c ) + 8007322: 2206 movs r2, #6 + 8007324: 701a strb r2, [r3, #0] + 8007326: e005 b.n 8007334 + } + else + { + current_radar_device--; + 8007328: 4b0c ldr r3, [pc, #48] ; (800735c ) + 800732a: 781b ldrb r3, [r3, #0] + 800732c: 3b01 subs r3, #1 + 800732e: b2da uxtb r2, r3 + 8007330: 4b0a ldr r3, [pc, #40] ; (800735c ) + 8007332: 701a strb r2, [r3, #0] + } + } + while (pp_dev_aux[current_radar_device]->exist_flag == 0); + 8007334: 4b0a ldr r3, [pc, #40] ; (8007360 ) + 8007336: 681a ldr r2, [r3, #0] + 8007338: 4b08 ldr r3, [pc, #32] ; (800735c ) + 800733a: 781b ldrb r3, [r3, #0] + 800733c: 009b lsls r3, r3, #2 + 800733e: 4413 add r3, r2 + 8007340: 681b ldr r3, [r3, #0] + 8007342: 781b ldrb r3, [r3, #0] + 8007344: 2b00 cmp r3, #0 + 8007346: d0e7 beq.n 8007318 + } + while (current_radar_device == device_number); + 8007348: 4b04 ldr r3, [pc, #16] ; (800735c ) + 800734a: 781a ldrb r2, [r3, #0] + 800734c: 4b05 ldr r3, [pc, #20] ; (8007364 ) + 800734e: 781b ldrb r3, [r3, #0] + 8007350: 429a cmp r2, r3 + 8007352: d0e1 beq.n 8007318 + + draw_current_menu(); + 8007354: f7fc ffc8 bl 80042e8 + } +} + 8007358: bf00 nop + 800735a: bd80 pop {r7, pc} + 800735c: 20000121 .word 0x20000121 + 8007360: 2000083c .word 0x2000083c + 8007364: 20000738 .word 0x20000738 + +08007368 : + + + +void radar_down(void) +{ + 8007368: b580 push {r7, lr} + 800736a: af00 add r7, sp, #0 + if (current_radar_device != 0) + 800736c: 4b12 ldr r3, [pc, #72] ; (80073b8 ) + 800736e: 781b ldrb r3, [r3, #0] + 8007370: 2b00 cmp r3, #0 + 8007372: d01f beq.n 80073b4 + { + do + { + do + { + if (current_radar_device == DEVICE_NUMBER_LAST) + 8007374: 4b10 ldr r3, [pc, #64] ; (80073b8 ) + 8007376: 781b ldrb r3, [r3, #0] + 8007378: 2b06 cmp r3, #6 + 800737a: d103 bne.n 8007384 + { + current_radar_device = DEVICE_NUMBER_FIRST; + 800737c: 4b0e ldr r3, [pc, #56] ; (80073b8 ) + 800737e: 2201 movs r2, #1 + 8007380: 701a strb r2, [r3, #0] + 8007382: e005 b.n 8007390 + } + else + { + current_radar_device++; + 8007384: 4b0c ldr r3, [pc, #48] ; (80073b8 ) + 8007386: 781b ldrb r3, [r3, #0] + 8007388: 3301 adds r3, #1 + 800738a: b2da uxtb r2, r3 + 800738c: 4b0a ldr r3, [pc, #40] ; (80073b8 ) + 800738e: 701a strb r2, [r3, #0] + } + } + while (pp_dev_aux[current_radar_device]->exist_flag == 0); + 8007390: 4b0a ldr r3, [pc, #40] ; (80073bc ) + 8007392: 681a ldr r2, [r3, #0] + 8007394: 4b08 ldr r3, [pc, #32] ; (80073b8 ) + 8007396: 781b ldrb r3, [r3, #0] + 8007398: 009b lsls r3, r3, #2 + 800739a: 4413 add r3, r2 + 800739c: 681b ldr r3, [r3, #0] + 800739e: 781b ldrb r3, [r3, #0] + 80073a0: 2b00 cmp r3, #0 + 80073a2: d0e7 beq.n 8007374 + } + while (current_radar_device == device_number); + 80073a4: 4b04 ldr r3, [pc, #16] ; (80073b8 ) + 80073a6: 781a ldrb r2, [r3, #0] + 80073a8: 4b05 ldr r3, [pc, #20] ; (80073c0 ) + 80073aa: 781b ldrb r3, [r3, #0] + 80073ac: 429a cmp r2, r3 + 80073ae: d0e1 beq.n 8007374 + + draw_current_menu(); + 80073b0: f7fc ff9a bl 80042e8 + } +} + 80073b4: bf00 nop + 80073b6: bd80 pop {r7, pc} + 80073b8: 20000121 .word 0x20000121 + 80073bc: 2000083c .word 0x2000083c + 80073c0: 20000738 .word 0x20000738 + +080073c4 : + + + +void radar_ok(void) +{ + 80073c4: b580 push {r7, lr} + 80073c6: af00 add r7, sp, #0 + if (current_radar_device != 0) + 80073c8: 4b09 ldr r3, [pc, #36] ; (80073f0 ) + 80073ca: 781b ldrb r3, [r3, #0] + 80073cc: 2b00 cmp r3, #0 + 80073ce: d00d beq.n 80073ec + { + radar_list_hide[current_radar_device] ^= 1; //Invert hide flag + 80073d0: 4b07 ldr r3, [pc, #28] ; (80073f0 ) + 80073d2: 781b ldrb r3, [r3, #0] + 80073d4: 461a mov r2, r3 + 80073d6: 4b07 ldr r3, [pc, #28] ; (80073f4 ) + 80073d8: 5c9b ldrb r3, [r3, r2] + 80073da: 4a05 ldr r2, [pc, #20] ; (80073f0 ) + 80073dc: 7812 ldrb r2, [r2, #0] + 80073de: f083 0301 eor.w r3, r3, #1 + 80073e2: b2d9 uxtb r1, r3 + 80073e4: 4b03 ldr r3, [pc, #12] ; (80073f4 ) + 80073e6: 5499 strb r1, [r3, r2] + + draw_current_menu(); + 80073e8: f7fc ff7e bl 80042e8 + } +} + 80073ec: bf00 nop + 80073ee: bd80 pop {r7, pc} + 80073f0: 20000121 .word 0x20000121 + 80073f4: 20000830 .word 0x20000830 + +080073f8 : + + + +void points_up(void) +{ + 80073f8: b580 push {r7, lr} + 80073fa: af00 add r7, sp, #0 + if (current_slot_to_load == MEMORY_SLOT_FIRST) + 80073fc: 4b08 ldr r3, [pc, #32] ; (8007420 ) + 80073fe: 781b ldrb r3, [r3, #0] + 8007400: 2b01 cmp r3, #1 + 8007402: d103 bne.n 800740c + { + current_slot_to_load = MEMORY_SLOT_LAST; + 8007404: 4b06 ldr r3, [pc, #24] ; (8007420 ) + 8007406: 2205 movs r2, #5 + 8007408: 701a strb r2, [r3, #0] + 800740a: e005 b.n 8007418 + } + else + { + current_slot_to_load--; + 800740c: 4b04 ldr r3, [pc, #16] ; (8007420 ) + 800740e: 781b ldrb r3, [r3, #0] + 8007410: 3b01 subs r3, #1 + 8007412: b2da uxtb r2, r3 + 8007414: 4b02 ldr r3, [pc, #8] ; (8007420 ) + 8007416: 701a strb r2, [r3, #0] + } + + draw_current_menu(); + 8007418: f7fc ff66 bl 80042e8 +} + 800741c: bf00 nop + 800741e: bd80 pop {r7, pc} + 8007420: 20000033 .word 0x20000033 + +08007424 : + + + +void points_down(void) +{ + 8007424: b580 push {r7, lr} + 8007426: af00 add r7, sp, #0 + if (current_slot_to_load == MEMORY_SLOT_LAST) + 8007428: 4b08 ldr r3, [pc, #32] ; (800744c ) + 800742a: 781b ldrb r3, [r3, #0] + 800742c: 2b05 cmp r3, #5 + 800742e: d103 bne.n 8007438 + { + current_slot_to_load = MEMORY_SLOT_FIRST; + 8007430: 4b06 ldr r3, [pc, #24] ; (800744c ) + 8007432: 2201 movs r2, #1 + 8007434: 701a strb r2, [r3, #0] + 8007436: e005 b.n 8007444 + } + else + { + current_slot_to_load++; + 8007438: 4b04 ldr r3, [pc, #16] ; (800744c ) + 800743a: 781b ldrb r3, [r3, #0] + 800743c: 3301 adds r3, #1 + 800743e: b2da uxtb r2, r3 + 8007440: 4b02 ldr r3, [pc, #8] ; (800744c ) + 8007442: 701a strb r2, [r3, #0] + } + + draw_current_menu(); + 8007444: f7fc ff50 bl 80042e8 +} + 8007448: bf00 nop + 800744a: bd80 pop {r7, pc} + 800744c: 20000033 .word 0x20000033 + +08007450 : + + + +void points_ok(void) +{ + 8007450: b580 push {r7, lr} + 8007452: af00 add r7, sp, #0 + if (pp_memory_slot[current_slot_to_load]->exist_flag == 1) + 8007454: 4b08 ldr r3, [pc, #32] ; (8007478 ) + 8007456: 681a ldr r2, [r3, #0] + 8007458: 4b08 ldr r3, [pc, #32] ; (800747c ) + 800745a: 781b ldrb r3, [r3, #0] + 800745c: 009b lsls r3, r3, #2 + 800745e: 4413 add r3, r2 + 8007460: 681b ldr r3, [r3, #0] + 8007462: 781b ldrb r3, [r3, #0] + 8007464: 2b01 cmp r3, #1 + 8007466: d104 bne.n 8007472 + { + current_menu = M_EACH_POINT; + 8007468: 4b05 ldr r3, [pc, #20] ; (8007480 ) + 800746a: 220b movs r2, #11 + 800746c: 701a strb r2, [r3, #0] + draw_current_menu(); + 800746e: f7fc ff3b bl 80042e8 + } +} + 8007472: bf00 nop + 8007474: bd80 pop {r7, pc} + 8007476: bf00 nop + 8007478: 200007d4 .word 0x200007d4 + 800747c: 20000033 .word 0x20000033 + 8007480: 200007fa .word 0x200007fa + +08007484 : + + + +void points_esc(void) +{ + 8007484: b580 push {r7, lr} + 8007486: af00 add r7, sp, #0 + current_slot_to_load = MEMORY_SLOT_FIRST; + 8007488: 4b04 ldr r3, [pc, #16] ; (800749c ) + 800748a: 2201 movs r2, #1 + 800748c: 701a strb r2, [r3, #0] + current_menu = M_MAIN; + 800748e: 4b04 ldr r3, [pc, #16] ; (80074a0 ) + 8007490: 2201 movs r2, #1 + 8007492: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007494: f7fc ff28 bl 80042e8 +} + 8007498: bf00 nop + 800749a: bd80 pop {r7, pc} + 800749c: 20000033 .word 0x20000033 + 80074a0: 200007fa .word 0x200007fa + +080074a4 : + + + +void load_point_up(void) +{ + 80074a4: b580 push {r7, lr} + 80074a6: af00 add r7, sp, #0 + if (current_device_to_load != 0) + 80074a8: 4b12 ldr r3, [pc, #72] ; (80074f4 ) + 80074aa: 781b ldrb r3, [r3, #0] + 80074ac: 2b00 cmp r3, #0 + 80074ae: d01f beq.n 80074f0 + { + do + { + do + { + if (current_device_to_load == DEVICE_NUMBER_FIRST) + 80074b0: 4b10 ldr r3, [pc, #64] ; (80074f4 ) + 80074b2: 781b ldrb r3, [r3, #0] + 80074b4: 2b01 cmp r3, #1 + 80074b6: d103 bne.n 80074c0 + { + current_device_to_load = DEVICE_NUMBER_LAST; + 80074b8: 4b0e ldr r3, [pc, #56] ; (80074f4 ) + 80074ba: 2206 movs r2, #6 + 80074bc: 701a strb r2, [r3, #0] + 80074be: e005 b.n 80074cc + } + else + { + current_device_to_load--; + 80074c0: 4b0c ldr r3, [pc, #48] ; (80074f4 ) + 80074c2: 781b ldrb r3, [r3, #0] + 80074c4: 3b01 subs r3, #1 + 80074c6: b2da uxtb r2, r3 + 80074c8: 4b0a ldr r3, [pc, #40] ; (80074f4 ) + 80074ca: 701a strb r2, [r3, #0] + } + } + while (pp_dev_aux[current_device_to_load]->exist_flag == 1); + 80074cc: 4b0a ldr r3, [pc, #40] ; (80074f8 ) + 80074ce: 681a ldr r2, [r3, #0] + 80074d0: 4b08 ldr r3, [pc, #32] ; (80074f4 ) + 80074d2: 781b ldrb r3, [r3, #0] + 80074d4: 009b lsls r3, r3, #2 + 80074d6: 4413 add r3, r2 + 80074d8: 681b ldr r3, [r3, #0] + 80074da: 781b ldrb r3, [r3, #0] + 80074dc: 2b01 cmp r3, #1 + 80074de: d0e7 beq.n 80074b0 + } + while (current_device_to_load == device_number); + 80074e0: 4b04 ldr r3, [pc, #16] ; (80074f4 ) + 80074e2: 781a ldrb r2, [r3, #0] + 80074e4: 4b05 ldr r3, [pc, #20] ; (80074fc ) + 80074e6: 781b ldrb r3, [r3, #0] + 80074e8: 429a cmp r2, r3 + 80074ea: d0e1 beq.n 80074b0 + + draw_current_menu(); + 80074ec: f7fc fefc bl 80042e8 + } +} + 80074f0: bf00 nop + 80074f2: bd80 pop {r7, pc} + 80074f4: 20000122 .word 0x20000122 + 80074f8: 2000083c .word 0x2000083c + 80074fc: 20000738 .word 0x20000738 + +08007500 : + + + +void load_point_down(void) +{ + 8007500: b580 push {r7, lr} + 8007502: af00 add r7, sp, #0 + if (current_device_to_load != 0) + 8007504: 4b12 ldr r3, [pc, #72] ; (8007550 ) + 8007506: 781b ldrb r3, [r3, #0] + 8007508: 2b00 cmp r3, #0 + 800750a: d01f beq.n 800754c + { + do + { + do + { + if (current_device_to_load == DEVICE_NUMBER_LAST) + 800750c: 4b10 ldr r3, [pc, #64] ; (8007550 ) + 800750e: 781b ldrb r3, [r3, #0] + 8007510: 2b06 cmp r3, #6 + 8007512: d103 bne.n 800751c + { + current_device_to_load = DEVICE_NUMBER_FIRST; + 8007514: 4b0e ldr r3, [pc, #56] ; (8007550 ) + 8007516: 2201 movs r2, #1 + 8007518: 701a strb r2, [r3, #0] + 800751a: e005 b.n 8007528 + } + else + { + current_device_to_load++; + 800751c: 4b0c ldr r3, [pc, #48] ; (8007550 ) + 800751e: 781b ldrb r3, [r3, #0] + 8007520: 3301 adds r3, #1 + 8007522: b2da uxtb r2, r3 + 8007524: 4b0a ldr r3, [pc, #40] ; (8007550 ) + 8007526: 701a strb r2, [r3, #0] + } + } + while (pp_dev_aux[current_device_to_load]->exist_flag == 1); + 8007528: 4b0a ldr r3, [pc, #40] ; (8007554 ) + 800752a: 681a ldr r2, [r3, #0] + 800752c: 4b08 ldr r3, [pc, #32] ; (8007550 ) + 800752e: 781b ldrb r3, [r3, #0] + 8007530: 009b lsls r3, r3, #2 + 8007532: 4413 add r3, r2 + 8007534: 681b ldr r3, [r3, #0] + 8007536: 781b ldrb r3, [r3, #0] + 8007538: 2b01 cmp r3, #1 + 800753a: d0e7 beq.n 800750c + } + while (current_device_to_load == device_number); + 800753c: 4b04 ldr r3, [pc, #16] ; (8007550 ) + 800753e: 781a ldrb r2, [r3, #0] + 8007540: 4b05 ldr r3, [pc, #20] ; (8007558 ) + 8007542: 781b ldrb r3, [r3, #0] + 8007544: 429a cmp r2, r3 + 8007546: d0e1 beq.n 800750c + + draw_current_menu(); + 8007548: f7fc fece bl 80042e8 + } +} + 800754c: bf00 nop + 800754e: bd80 pop {r7, pc} + 8007550: 20000122 .word 0x20000122 + 8007554: 2000083c .word 0x2000083c + 8007558: 20000738 .word 0x20000738 + +0800755c : + + + +void load_point_ok(void) +{ + 800755c: b580 push {r7, lr} + 800755e: af00 add r7, sp, #0 + if (current_device_to_load != 0) + 8007560: 4b0c ldr r3, [pc, #48] ; (8007594 ) + 8007562: 781b ldrb r3, [r3, #0] + 8007564: 2b00 cmp r3, #0 + 8007566: d012 beq.n 800758e + { + load_memory_point(current_device_to_load, current_slot_to_load); + 8007568: 4b0a ldr r3, [pc, #40] ; (8007594 ) + 800756a: 781a ldrb r2, [r3, #0] + 800756c: 4b0a ldr r3, [pc, #40] ; (8007598 ) + 800756e: 781b ldrb r3, [r3, #0] + 8007570: 4619 mov r1, r3 + 8007572: 4610 mov r0, r2 + 8007574: f000 fd22 bl 8007fbc + + current_slot_to_load = MEMORY_SLOT_FIRST; + 8007578: 4b07 ldr r3, [pc, #28] ; (8007598 ) + 800757a: 2201 movs r2, #1 + 800757c: 701a strb r2, [r3, #0] + current_device_to_load = 0; + 800757e: 4b05 ldr r3, [pc, #20] ; (8007594 ) + 8007580: 2200 movs r2, #0 + 8007582: 701a strb r2, [r3, #0] + current_menu = M_MAIN; + 8007584: 4b05 ldr r3, [pc, #20] ; (800759c ) + 8007586: 2201 movs r2, #1 + 8007588: 701a strb r2, [r3, #0] + draw_current_menu(); + 800758a: f7fc fead bl 80042e8 + } +} + 800758e: bf00 nop + 8007590: bd80 pop {r7, pc} + 8007592: bf00 nop + 8007594: 20000122 .word 0x20000122 + 8007598: 20000033 .word 0x20000033 + 800759c: 200007fa .word 0x200007fa + +080075a0 : + + + +void load_point_esc(void) +{ + 80075a0: b580 push {r7, lr} + 80075a2: af00 add r7, sp, #0 + current_device_to_load = 0; + 80075a4: 4b04 ldr r3, [pc, #16] ; (80075b8 ) + 80075a6: 2200 movs r2, #0 + 80075a8: 701a strb r2, [r3, #0] + current_menu = M_EACH_POINT; + 80075aa: 4b04 ldr r3, [pc, #16] ; (80075bc ) + 80075ac: 220b movs r2, #11 + 80075ae: 701a strb r2, [r3, #0] + draw_current_menu(); + 80075b0: f7fc fe9a bl 80042e8 +} + 80075b4: bf00 nop + 80075b6: bd80 pop {r7, pc} + 80075b8: 20000122 .word 0x20000122 + 80075bc: 200007fa .word 0x200007fa + +080075c0 : + + + +void delete_point_ok(void) +{ + 80075c0: b580 push {r7, lr} + 80075c2: af00 add r7, sp, #0 + delete_memory_point(current_slot_to_load); + 80075c4: 4b08 ldr r3, [pc, #32] ; (80075e8 ) + 80075c6: 781b ldrb r3, [r3, #0] + 80075c8: 4618 mov r0, r3 + 80075ca: f000 fdd7 bl 800817c + + reset_current_item_in_menu(M_EACH_POINT); + 80075ce: 200b movs r0, #11 + 80075d0: f7fc fe5a bl 8004288 + current_slot_to_load = MEMORY_SLOT_FIRST; + 80075d4: 4b04 ldr r3, [pc, #16] ; (80075e8 ) + 80075d6: 2201 movs r2, #1 + 80075d8: 701a strb r2, [r3, #0] + current_menu = M_POINTS; + 80075da: 4b04 ldr r3, [pc, #16] ; (80075ec ) + 80075dc: 220a movs r2, #10 + 80075de: 701a strb r2, [r3, #0] + draw_current_menu(); + 80075e0: f7fc fe82 bl 80042e8 +} + 80075e4: bf00 nop + 80075e6: bd80 pop {r7, pc} + 80075e8: 20000033 .word 0x20000033 + 80075ec: 200007fa .word 0x200007fa + +080075f0 : + + + +void set_dev_num_up(void) +{ + 80075f0: b580 push {r7, lr} + 80075f2: af00 add r7, sp, #0 + if (settings_copy.device_number == DEVICE_NUMBER_LAST) + 80075f4: 4b08 ldr r3, [pc, #32] ; (8007618 ) + 80075f6: 781b ldrb r3, [r3, #0] + 80075f8: 2b06 cmp r3, #6 + 80075fa: d103 bne.n 8007604 + { + settings_copy.device_number = DEVICE_NUMBER_FIRST; + 80075fc: 4b06 ldr r3, [pc, #24] ; (8007618 ) + 80075fe: 2201 movs r2, #1 + 8007600: 701a strb r2, [r3, #0] + 8007602: e005 b.n 8007610 + } + else + { + settings_copy.device_number++; + 8007604: 4b04 ldr r3, [pc, #16] ; (8007618 ) + 8007606: 781b ldrb r3, [r3, #0] + 8007608: 3301 adds r3, #1 + 800760a: b2da uxtb r2, r3 + 800760c: 4b02 ldr r3, [pc, #8] ; (8007618 ) + 800760e: 701a strb r2, [r3, #0] + } + + draw_current_menu(); + 8007610: f7fc fe6a bl 80042e8 +} + 8007614: bf00 nop + 8007616: bd80 pop {r7, pc} + 8007618: 200007e0 .word 0x200007e0 + +0800761c : + + + +void set_dev_num_down(void) +{ + 800761c: b580 push {r7, lr} + 800761e: af00 add r7, sp, #0 + if (settings_copy.device_number == DEVICE_NUMBER_FIRST) + 8007620: 4b08 ldr r3, [pc, #32] ; (8007644 ) + 8007622: 781b ldrb r3, [r3, #0] + 8007624: 2b01 cmp r3, #1 + 8007626: d103 bne.n 8007630 + { + settings_copy.device_number = DEVICE_NUMBER_LAST; + 8007628: 4b06 ldr r3, [pc, #24] ; (8007644 ) + 800762a: 2206 movs r2, #6 + 800762c: 701a strb r2, [r3, #0] + 800762e: e005 b.n 800763c + } + else + { + settings_copy.device_number--; + 8007630: 4b04 ldr r3, [pc, #16] ; (8007644 ) + 8007632: 781b ldrb r3, [r3, #0] + 8007634: 3b01 subs r3, #1 + 8007636: b2da uxtb r2, r3 + 8007638: 4b02 ldr r3, [pc, #8] ; (8007644 ) + 800763a: 701a strb r2, [r3, #0] + } + + draw_current_menu(); + 800763c: f7fc fe54 bl 80042e8 +} + 8007640: bf00 nop + 8007642: bd80 pop {r7, pc} + 8007644: 200007e0 .word 0x200007e0 + +08007648 : + + + +void set_dev_num_ok(void) +{ + 8007648: b580 push {r7, lr} + 800764a: af00 add r7, sp, #0 + if (settings_copy.device_number != device_number) + 800764c: 4b07 ldr r3, [pc, #28] ; (800766c ) + 800764e: 781a ldrb r2, [r3, #0] + 8007650: 4b07 ldr r3, [pc, #28] ; (8007670 ) + 8007652: 781b ldrb r3, [r3, #0] + 8007654: 429a cmp r2, r3 + 8007656: d002 beq.n 800765e + { + flag_settings_changed = 1; + 8007658: 4b06 ldr r3, [pc, #24] ; (8007674 ) + 800765a: 2201 movs r2, #1 + 800765c: 701a strb r2, [r3, #0] + } + + current_menu = M_EDIT_SETTINGS; + 800765e: 4b06 ldr r3, [pc, #24] ; (8007678 ) + 8007660: 2210 movs r2, #16 + 8007662: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007664: f7fc fe40 bl 80042e8 +} + 8007668: bf00 nop + 800766a: bd80 pop {r7, pc} + 800766c: 200007e0 .word 0x200007e0 + 8007670: 20000738 .word 0x20000738 + 8007674: 2000011e .word 0x2000011e + 8007678: 200007fa .word 0x200007fa + +0800767c : + + + +void set_dev_num_esc(void) +{ + 800767c: b580 push {r7, lr} + 800767e: af00 add r7, sp, #0 + settings_copy.device_number = device_number; //exit no save, reset value + 8007680: 4b05 ldr r3, [pc, #20] ; (8007698 ) + 8007682: 781a ldrb r2, [r3, #0] + 8007684: 4b05 ldr r3, [pc, #20] ; (800769c ) + 8007686: 701a strb r2, [r3, #0] + current_menu = M_EDIT_SETTINGS; + 8007688: 4b05 ldr r3, [pc, #20] ; (80076a0 ) + 800768a: 2210 movs r2, #16 + 800768c: 701a strb r2, [r3, #0] + draw_current_menu(); + 800768e: f7fc fe2b bl 80042e8 +} + 8007692: bf00 nop + 8007694: bd80 pop {r7, pc} + 8007696: bf00 nop + 8007698: 20000738 .word 0x20000738 + 800769c: 200007e0 .word 0x200007e0 + 80076a0: 200007fa .word 0x200007fa + +080076a4 : + + + +void confirm_settings_save_ok(void) +{ + 80076a4: b580 push {r7, lr} + 80076a6: af00 add r7, sp, #0 + settings_save(&settings_copy); + 80076a8: 4803 ldr r0, [pc, #12] ; (80076b8 ) + 80076aa: f001 f9cd bl 8008a48 + NVIC_SystemReset(); + 80076ae: f7fc fbbb bl 8003e28 +} + 80076b2: bf00 nop + 80076b4: bd80 pop {r7, pc} + 80076b6: bf00 nop + 80076b8: 200007e0 .word 0x200007e0 + +080076bc : + + + +void set_dev_id_up(void) +{ + 80076bc: b580 push {r7, lr} + 80076be: af00 add r7, sp, #0 + if (settings_copy.device_id[device_id_current_symbol] == DEVICE_ID_LAST_SYMBOL) + 80076c0: 4b0f ldr r3, [pc, #60] ; (8007700 ) + 80076c2: 781b ldrb r3, [r3, #0] + 80076c4: 461a mov r2, r3 + 80076c6: 4b0f ldr r3, [pc, #60] ; (8007704 ) + 80076c8: 4413 add r3, r2 + 80076ca: 785b ldrb r3, [r3, #1] + 80076cc: 2b5a cmp r3, #90 ; 0x5a + 80076ce: d107 bne.n 80076e0 + { + settings_copy.device_id[device_id_current_symbol] = DEVICE_ID_FIRST_SYMBOL; + 80076d0: 4b0b ldr r3, [pc, #44] ; (8007700 ) + 80076d2: 781b ldrb r3, [r3, #0] + 80076d4: 461a mov r2, r3 + 80076d6: 4b0b ldr r3, [pc, #44] ; (8007704 ) + 80076d8: 4413 add r3, r2 + 80076da: 2241 movs r2, #65 ; 0x41 + 80076dc: 705a strb r2, [r3, #1] + 80076de: e00a b.n 80076f6 + } + else + { + settings_copy.device_id[device_id_current_symbol]++; + 80076e0: 4b07 ldr r3, [pc, #28] ; (8007700 ) + 80076e2: 781b ldrb r3, [r3, #0] + 80076e4: 4a07 ldr r2, [pc, #28] ; (8007704 ) + 80076e6: 441a add r2, r3 + 80076e8: 7852 ldrb r2, [r2, #1] + 80076ea: 3201 adds r2, #1 + 80076ec: b2d1 uxtb r1, r2 + 80076ee: 4a05 ldr r2, [pc, #20] ; (8007704 ) + 80076f0: 4413 add r3, r2 + 80076f2: 460a mov r2, r1 + 80076f4: 705a strb r2, [r3, #1] + } + + draw_current_menu(); + 80076f6: f7fc fdf7 bl 80042e8 +} + 80076fa: bf00 nop + 80076fc: bd80 pop {r7, pc} + 80076fe: bf00 nop + 8007700: 2000011f .word 0x2000011f + 8007704: 200007e0 .word 0x200007e0 + +08007708 : + + + +void set_dev_id_down(void) +{ + 8007708: b580 push {r7, lr} + 800770a: af00 add r7, sp, #0 + if (settings_copy.device_id[device_id_current_symbol] == DEVICE_ID_FIRST_SYMBOL) + 800770c: 4b0f ldr r3, [pc, #60] ; (800774c ) + 800770e: 781b ldrb r3, [r3, #0] + 8007710: 461a mov r2, r3 + 8007712: 4b0f ldr r3, [pc, #60] ; (8007750 ) + 8007714: 4413 add r3, r2 + 8007716: 785b ldrb r3, [r3, #1] + 8007718: 2b41 cmp r3, #65 ; 0x41 + 800771a: d107 bne.n 800772c + { + settings_copy.device_id[device_id_current_symbol] = DEVICE_ID_LAST_SYMBOL; + 800771c: 4b0b ldr r3, [pc, #44] ; (800774c ) + 800771e: 781b ldrb r3, [r3, #0] + 8007720: 461a mov r2, r3 + 8007722: 4b0b ldr r3, [pc, #44] ; (8007750 ) + 8007724: 4413 add r3, r2 + 8007726: 225a movs r2, #90 ; 0x5a + 8007728: 705a strb r2, [r3, #1] + 800772a: e00a b.n 8007742 + } + else + { + settings_copy.device_id[device_id_current_symbol]--; + 800772c: 4b07 ldr r3, [pc, #28] ; (800774c ) + 800772e: 781b ldrb r3, [r3, #0] + 8007730: 4a07 ldr r2, [pc, #28] ; (8007750 ) + 8007732: 441a add r2, r3 + 8007734: 7852 ldrb r2, [r2, #1] + 8007736: 3a01 subs r2, #1 + 8007738: b2d1 uxtb r1, r2 + 800773a: 4a05 ldr r2, [pc, #20] ; (8007750 ) + 800773c: 4413 add r3, r2 + 800773e: 460a mov r2, r1 + 8007740: 705a strb r2, [r3, #1] + } + + draw_current_menu(); + 8007742: f7fc fdd1 bl 80042e8 +} + 8007746: bf00 nop + 8007748: bd80 pop {r7, pc} + 800774a: bf00 nop + 800774c: 2000011f .word 0x2000011f + 8007750: 200007e0 .word 0x200007e0 + +08007754 : + + + +void set_dev_id_ok(void) +{ + 8007754: b580 push {r7, lr} + 8007756: af00 add r7, sp, #0 + if (++device_id_current_symbol == DEVICE_ID_LEN) + 8007758: 4b08 ldr r3, [pc, #32] ; (800777c ) + 800775a: 781b ldrb r3, [r3, #0] + 800775c: 3301 adds r3, #1 + 800775e: b2da uxtb r2, r3 + 8007760: 4b06 ldr r3, [pc, #24] ; (800777c ) + 8007762: 701a strb r2, [r3, #0] + 8007764: 4b05 ldr r3, [pc, #20] ; (800777c ) + 8007766: 781b ldrb r3, [r3, #0] + 8007768: 2b02 cmp r3, #2 + 800776a: d102 bne.n 8007772 + { + device_id_current_symbol = 0; + 800776c: 4b03 ldr r3, [pc, #12] ; (800777c ) + 800776e: 2200 movs r2, #0 + 8007770: 701a strb r2, [r3, #0] + } + + draw_current_menu(); + 8007772: f7fc fdb9 bl 80042e8 +} + 8007776: bf00 nop + 8007778: bd80 pop {r7, pc} + 800777a: bf00 nop + 800777c: 2000011f .word 0x2000011f + +08007780 : + + + +void set_dev_id_ok_long(void) +{ + 8007780: b580 push {r7, lr} + 8007782: b082 sub sp, #8 + 8007784: af00 add r7, sp, #0 + for (uint8_t i = 0; i < DEVICE_ID_LEN; i++) + 8007786: 2300 movs r3, #0 + 8007788: 71fb strb r3, [r7, #7] + 800778a: e011 b.n 80077b0 + { + if (settings_copy.device_id[i] != p_settings->device_id[i]) + 800778c: 79fb ldrb r3, [r7, #7] + 800778e: 4a0e ldr r2, [pc, #56] ; (80077c8 ) + 8007790: 4413 add r3, r2 + 8007792: 785a ldrb r2, [r3, #1] + 8007794: 4b0d ldr r3, [pc, #52] ; (80077cc ) + 8007796: 6819 ldr r1, [r3, #0] + 8007798: 79fb ldrb r3, [r7, #7] + 800779a: 440b add r3, r1 + 800779c: 785b ldrb r3, [r3, #1] + 800779e: 429a cmp r2, r3 + 80077a0: d003 beq.n 80077aa + { + flag_settings_changed = 1; + 80077a2: 4b0b ldr r3, [pc, #44] ; (80077d0 ) + 80077a4: 2201 movs r2, #1 + 80077a6: 701a strb r2, [r3, #0] + break; + 80077a8: e005 b.n 80077b6 + for (uint8_t i = 0; i < DEVICE_ID_LEN; i++) + 80077aa: 79fb ldrb r3, [r7, #7] + 80077ac: 3301 adds r3, #1 + 80077ae: 71fb strb r3, [r7, #7] + 80077b0: 79fb ldrb r3, [r7, #7] + 80077b2: 2b01 cmp r3, #1 + 80077b4: d9ea bls.n 800778c + } + } + + current_menu = M_EDIT_SETTINGS; + 80077b6: 4b07 ldr r3, [pc, #28] ; (80077d4 ) + 80077b8: 2210 movs r2, #16 + 80077ba: 701a strb r2, [r3, #0] + draw_current_menu(); + 80077bc: f7fc fd94 bl 80042e8 +} + 80077c0: bf00 nop + 80077c2: 3708 adds r7, #8 + 80077c4: 46bd mov sp, r7 + 80077c6: bd80 pop {r7, pc} + 80077c8: 200007e0 .word 0x200007e0 + 80077cc: 2000061c .word 0x2000061c + 80077d0: 2000011e .word 0x2000011e + 80077d4: 200007fa .word 0x200007fa + +080077d8 : + + + +void set_dev_id_esc(void) +{ + 80077d8: b580 push {r7, lr} + 80077da: b082 sub sp, #8 + 80077dc: af00 add r7, sp, #0 + for (uint8_t i = 0; i < DEVICE_ID_LEN; i++) + 80077de: 2300 movs r3, #0 + 80077e0: 71fb strb r3, [r7, #7] + 80077e2: e00c b.n 80077fe + { + settings_copy.device_id[i] = p_settings->device_id[i]; //exit no save, reset value + 80077e4: 4b0d ldr r3, [pc, #52] ; (800781c ) + 80077e6: 6819 ldr r1, [r3, #0] + 80077e8: 79fa ldrb r2, [r7, #7] + 80077ea: 79fb ldrb r3, [r7, #7] + 80077ec: 440a add r2, r1 + 80077ee: 7851 ldrb r1, [r2, #1] + 80077f0: 4a0b ldr r2, [pc, #44] ; (8007820 ) + 80077f2: 4413 add r3, r2 + 80077f4: 460a mov r2, r1 + 80077f6: 705a strb r2, [r3, #1] + for (uint8_t i = 0; i < DEVICE_ID_LEN; i++) + 80077f8: 79fb ldrb r3, [r7, #7] + 80077fa: 3301 adds r3, #1 + 80077fc: 71fb strb r3, [r7, #7] + 80077fe: 79fb ldrb r3, [r7, #7] + 8007800: 2b01 cmp r3, #1 + 8007802: d9ef bls.n 80077e4 + } + device_id_current_symbol = 0; + 8007804: 4b07 ldr r3, [pc, #28] ; (8007824 ) + 8007806: 2200 movs r2, #0 + 8007808: 701a strb r2, [r3, #0] + + current_menu = M_EDIT_SETTINGS; + 800780a: 4b07 ldr r3, [pc, #28] ; (8007828 ) + 800780c: 2210 movs r2, #16 + 800780e: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007810: f7fc fd6a bl 80042e8 +} + 8007814: bf00 nop + 8007816: 3708 adds r7, #8 + 8007818: 46bd mov sp, r7 + 800781a: bd80 pop {r7, pc} + 800781c: 2000061c .word 0x2000061c + 8007820: 200007e0 .word 0x200007e0 + 8007824: 2000011f .word 0x2000011f + 8007828: 200007fa .word 0x200007fa + +0800782c : + + + +void set_freq_ch_up(void) +{ + 800782c: b580 push {r7, lr} + 800782e: af00 add r7, sp, #0 + if (settings_copy.freq_channel == FREQ_CHANNEL_LAST) + 8007830: 4b08 ldr r3, [pc, #32] ; (8007854 ) + 8007832: 78db ldrb r3, [r3, #3] + 8007834: 2b45 cmp r3, #69 ; 0x45 + 8007836: d103 bne.n 8007840 + { + settings_copy.freq_channel = FREQ_CHANNEL_FIRST; + 8007838: 4b06 ldr r3, [pc, #24] ; (8007854 ) + 800783a: 2201 movs r2, #1 + 800783c: 70da strb r2, [r3, #3] + 800783e: e005 b.n 800784c + } + else + { + settings_copy.freq_channel++; + 8007840: 4b04 ldr r3, [pc, #16] ; (8007854 ) + 8007842: 78db ldrb r3, [r3, #3] + 8007844: 3301 adds r3, #1 + 8007846: b2da uxtb r2, r3 + 8007848: 4b02 ldr r3, [pc, #8] ; (8007854 ) + 800784a: 70da strb r2, [r3, #3] + } + + draw_current_menu(); + 800784c: f7fc fd4c bl 80042e8 +} + 8007850: bf00 nop + 8007852: bd80 pop {r7, pc} + 8007854: 200007e0 .word 0x200007e0 + +08007858 : + + + +void set_freq_ch_down(void) +{ + 8007858: b580 push {r7, lr} + 800785a: af00 add r7, sp, #0 + if (settings_copy.freq_channel == FREQ_CHANNEL_FIRST) + 800785c: 4b08 ldr r3, [pc, #32] ; (8007880 ) + 800785e: 78db ldrb r3, [r3, #3] + 8007860: 2b01 cmp r3, #1 + 8007862: d103 bne.n 800786c + { + settings_copy.freq_channel = FREQ_CHANNEL_LAST; + 8007864: 4b06 ldr r3, [pc, #24] ; (8007880 ) + 8007866: 2245 movs r2, #69 ; 0x45 + 8007868: 70da strb r2, [r3, #3] + 800786a: e005 b.n 8007878 + } + else + { + settings_copy.freq_channel--; + 800786c: 4b04 ldr r3, [pc, #16] ; (8007880 ) + 800786e: 78db ldrb r3, [r3, #3] + 8007870: 3b01 subs r3, #1 + 8007872: b2da uxtb r2, r3 + 8007874: 4b02 ldr r3, [pc, #8] ; (8007880 ) + 8007876: 70da strb r2, [r3, #3] + } + + draw_current_menu(); + 8007878: f7fc fd36 bl 80042e8 +} + 800787c: bf00 nop + 800787e: bd80 pop {r7, pc} + 8007880: 200007e0 .word 0x200007e0 + +08007884 : + + + +void set_freq_ch_ok(void) +{ + 8007884: b580 push {r7, lr} + 8007886: af00 add r7, sp, #0 + if (settings_copy.freq_channel != p_settings->freq_channel) + 8007888: 4b08 ldr r3, [pc, #32] ; (80078ac ) + 800788a: 78da ldrb r2, [r3, #3] + 800788c: 4b08 ldr r3, [pc, #32] ; (80078b0 ) + 800788e: 681b ldr r3, [r3, #0] + 8007890: 78db ldrb r3, [r3, #3] + 8007892: 429a cmp r2, r3 + 8007894: d002 beq.n 800789c + { + flag_settings_changed = 1; + 8007896: 4b07 ldr r3, [pc, #28] ; (80078b4 ) + 8007898: 2201 movs r2, #1 + 800789a: 701a strb r2, [r3, #0] + } + + current_menu = M_EDIT_SETTINGS; + 800789c: 4b06 ldr r3, [pc, #24] ; (80078b8 ) + 800789e: 2210 movs r2, #16 + 80078a0: 701a strb r2, [r3, #0] + draw_current_menu(); + 80078a2: f7fc fd21 bl 80042e8 +} + 80078a6: bf00 nop + 80078a8: bd80 pop {r7, pc} + 80078aa: bf00 nop + 80078ac: 200007e0 .word 0x200007e0 + 80078b0: 2000061c .word 0x2000061c + 80078b4: 2000011e .word 0x2000011e + 80078b8: 200007fa .word 0x200007fa + +080078bc : + + + +void set_freq_ch_esc(void) +{ + 80078bc: b580 push {r7, lr} + 80078be: af00 add r7, sp, #0 + settings_copy.freq_channel = p_settings->freq_channel; //exit no save, reset value + 80078c0: 4b05 ldr r3, [pc, #20] ; (80078d8 ) + 80078c2: 681b ldr r3, [r3, #0] + 80078c4: 78da ldrb r2, [r3, #3] + 80078c6: 4b05 ldr r3, [pc, #20] ; (80078dc ) + 80078c8: 70da strb r2, [r3, #3] + current_menu = M_EDIT_SETTINGS; + 80078ca: 4b05 ldr r3, [pc, #20] ; (80078e0 ) + 80078cc: 2210 movs r2, #16 + 80078ce: 701a strb r2, [r3, #0] + draw_current_menu(); + 80078d0: f7fc fd0a bl 80042e8 +} + 80078d4: bf00 nop + 80078d6: bd80 pop {r7, pc} + 80078d8: 2000061c .word 0x2000061c + 80078dc: 200007e0 .word 0x200007e0 + 80078e0: 200007fa .word 0x200007fa + +080078e4 : + + + +void set_tx_pow_up(void) +{ + 80078e4: b580 push {r7, lr} + 80078e6: af00 add r7, sp, #0 + if (settings_copy.tx_power_opt == TX_POWER_LAST_OPTION) + 80078e8: 4b08 ldr r3, [pc, #32] ; (800790c ) + 80078ea: 791b ldrb r3, [r3, #4] + 80078ec: 2b03 cmp r3, #3 + 80078ee: d103 bne.n 80078f8 + { + settings_copy.tx_power_opt = TX_POWER_FIRST_OPTION; + 80078f0: 4b06 ldr r3, [pc, #24] ; (800790c ) + 80078f2: 2200 movs r2, #0 + 80078f4: 711a strb r2, [r3, #4] + 80078f6: e005 b.n 8007904 + } + else + { + settings_copy.tx_power_opt++; + 80078f8: 4b04 ldr r3, [pc, #16] ; (800790c ) + 80078fa: 791b ldrb r3, [r3, #4] + 80078fc: 3301 adds r3, #1 + 80078fe: b2da uxtb r2, r3 + 8007900: 4b02 ldr r3, [pc, #8] ; (800790c ) + 8007902: 711a strb r2, [r3, #4] + } + + draw_current_menu(); + 8007904: f7fc fcf0 bl 80042e8 +} + 8007908: bf00 nop + 800790a: bd80 pop {r7, pc} + 800790c: 200007e0 .word 0x200007e0 + +08007910 : + + + +void set_tx_pow_down(void) +{ + 8007910: b580 push {r7, lr} + 8007912: af00 add r7, sp, #0 + if (settings_copy.tx_power_opt == TX_POWER_FIRST_OPTION) + 8007914: 4b08 ldr r3, [pc, #32] ; (8007938 ) + 8007916: 791b ldrb r3, [r3, #4] + 8007918: 2b00 cmp r3, #0 + 800791a: d103 bne.n 8007924 + { + settings_copy.tx_power_opt = TX_POWER_LAST_OPTION; + 800791c: 4b06 ldr r3, [pc, #24] ; (8007938 ) + 800791e: 2203 movs r2, #3 + 8007920: 711a strb r2, [r3, #4] + 8007922: e005 b.n 8007930 + } + else + { + settings_copy.tx_power_opt--; + 8007924: 4b04 ldr r3, [pc, #16] ; (8007938 ) + 8007926: 791b ldrb r3, [r3, #4] + 8007928: 3b01 subs r3, #1 + 800792a: b2da uxtb r2, r3 + 800792c: 4b02 ldr r3, [pc, #8] ; (8007938 ) + 800792e: 711a strb r2, [r3, #4] + } + + draw_current_menu(); + 8007930: f7fc fcda bl 80042e8 +} + 8007934: bf00 nop + 8007936: bd80 pop {r7, pc} + 8007938: 200007e0 .word 0x200007e0 + +0800793c : + + + +void set_tx_pow_ok(void) +{ + 800793c: b580 push {r7, lr} + 800793e: af00 add r7, sp, #0 + if (settings_copy.tx_power_opt != p_settings->tx_power_opt) + 8007940: 4b08 ldr r3, [pc, #32] ; (8007964 ) + 8007942: 791a ldrb r2, [r3, #4] + 8007944: 4b08 ldr r3, [pc, #32] ; (8007968 ) + 8007946: 681b ldr r3, [r3, #0] + 8007948: 791b ldrb r3, [r3, #4] + 800794a: 429a cmp r2, r3 + 800794c: d002 beq.n 8007954 + { + flag_settings_changed = 1; + 800794e: 4b07 ldr r3, [pc, #28] ; (800796c ) + 8007950: 2201 movs r2, #1 + 8007952: 701a strb r2, [r3, #0] + } + + current_menu = M_EDIT_SETTINGS; + 8007954: 4b06 ldr r3, [pc, #24] ; (8007970 ) + 8007956: 2210 movs r2, #16 + 8007958: 701a strb r2, [r3, #0] + draw_current_menu(); + 800795a: f7fc fcc5 bl 80042e8 +} + 800795e: bf00 nop + 8007960: bd80 pop {r7, pc} + 8007962: bf00 nop + 8007964: 200007e0 .word 0x200007e0 + 8007968: 2000061c .word 0x2000061c + 800796c: 2000011e .word 0x2000011e + 8007970: 200007fa .word 0x200007fa + +08007974 : + + + +void set_tx_pow_esc(void) +{ + 8007974: b580 push {r7, lr} + 8007976: af00 add r7, sp, #0 + settings_copy.tx_power_opt = p_settings->tx_power_opt; //exit no save, reset value + 8007978: 4b05 ldr r3, [pc, #20] ; (8007990 ) + 800797a: 681b ldr r3, [r3, #0] + 800797c: 791a ldrb r2, [r3, #4] + 800797e: 4b05 ldr r3, [pc, #20] ; (8007994 ) + 8007980: 711a strb r2, [r3, #4] + current_menu = M_EDIT_SETTINGS; + 8007982: 4b05 ldr r3, [pc, #20] ; (8007998 ) + 8007984: 2210 movs r2, #16 + 8007986: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007988: f7fc fcae bl 80042e8 +} + 800798c: bf00 nop + 800798e: bd80 pop {r7, pc} + 8007990: 2000061c .word 0x2000061c + 8007994: 200007e0 .word 0x200007e0 + 8007998: 200007fa .word 0x200007fa + +0800799c : + + + +void set_send_intvl_up(void) +{ + 800799c: b580 push {r7, lr} + 800799e: af00 add r7, sp, #0 + if (settings_copy.send_interval_opt == SEND_INTERVAL_LAST_OPTION) + 80079a0: 4b08 ldr r3, [pc, #32] ; (80079c4 ) + 80079a2: 795b ldrb r3, [r3, #5] + 80079a4: 2b04 cmp r3, #4 + 80079a6: d103 bne.n 80079b0 + { + settings_copy.send_interval_opt = SEND_INTERVAL_FIRST_OPTION; + 80079a8: 4b06 ldr r3, [pc, #24] ; (80079c4 ) + 80079aa: 2200 movs r2, #0 + 80079ac: 715a strb r2, [r3, #5] + 80079ae: e005 b.n 80079bc + } + else + { + settings_copy.send_interval_opt++; + 80079b0: 4b04 ldr r3, [pc, #16] ; (80079c4 ) + 80079b2: 795b ldrb r3, [r3, #5] + 80079b4: 3301 adds r3, #1 + 80079b6: b2da uxtb r2, r3 + 80079b8: 4b02 ldr r3, [pc, #8] ; (80079c4 ) + 80079ba: 715a strb r2, [r3, #5] + } + + draw_current_menu(); + 80079bc: f7fc fc94 bl 80042e8 +} + 80079c0: bf00 nop + 80079c2: bd80 pop {r7, pc} + 80079c4: 200007e0 .word 0x200007e0 + +080079c8 : + + + +void set_send_intvl_down(void) +{ + 80079c8: b580 push {r7, lr} + 80079ca: af00 add r7, sp, #0 + if (settings_copy.send_interval_opt == SEND_INTERVAL_FIRST_OPTION) + 80079cc: 4b08 ldr r3, [pc, #32] ; (80079f0 ) + 80079ce: 795b ldrb r3, [r3, #5] + 80079d0: 2b00 cmp r3, #0 + 80079d2: d103 bne.n 80079dc + { + settings_copy.send_interval_opt = SEND_INTERVAL_LAST_OPTION; + 80079d4: 4b06 ldr r3, [pc, #24] ; (80079f0 ) + 80079d6: 2204 movs r2, #4 + 80079d8: 715a strb r2, [r3, #5] + 80079da: e005 b.n 80079e8 + } + else + { + settings_copy.send_interval_opt--; + 80079dc: 4b04 ldr r3, [pc, #16] ; (80079f0 ) + 80079de: 795b ldrb r3, [r3, #5] + 80079e0: 3b01 subs r3, #1 + 80079e2: b2da uxtb r2, r3 + 80079e4: 4b02 ldr r3, [pc, #8] ; (80079f0 ) + 80079e6: 715a strb r2, [r3, #5] + } + + draw_current_menu(); + 80079e8: f7fc fc7e bl 80042e8 +} + 80079ec: bf00 nop + 80079ee: bd80 pop {r7, pc} + 80079f0: 200007e0 .word 0x200007e0 + +080079f4 : + + + +void set_send_intvl_ok(void) +{ + 80079f4: b580 push {r7, lr} + 80079f6: af00 add r7, sp, #0 + if (settings_copy.send_interval_opt != p_settings->send_interval_opt) + 80079f8: 4b08 ldr r3, [pc, #32] ; (8007a1c ) + 80079fa: 795a ldrb r2, [r3, #5] + 80079fc: 4b08 ldr r3, [pc, #32] ; (8007a20 ) + 80079fe: 681b ldr r3, [r3, #0] + 8007a00: 795b ldrb r3, [r3, #5] + 8007a02: 429a cmp r2, r3 + 8007a04: d002 beq.n 8007a0c + { + flag_settings_changed = 1; + 8007a06: 4b07 ldr r3, [pc, #28] ; (8007a24 ) + 8007a08: 2201 movs r2, #1 + 8007a0a: 701a strb r2, [r3, #0] + } + + current_menu = M_EDIT_SETTINGS; + 8007a0c: 4b06 ldr r3, [pc, #24] ; (8007a28 ) + 8007a0e: 2210 movs r2, #16 + 8007a10: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007a12: f7fc fc69 bl 80042e8 +} + 8007a16: bf00 nop + 8007a18: bd80 pop {r7, pc} + 8007a1a: bf00 nop + 8007a1c: 200007e0 .word 0x200007e0 + 8007a20: 2000061c .word 0x2000061c + 8007a24: 2000011e .word 0x2000011e + 8007a28: 200007fa .word 0x200007fa + +08007a2c : + + + +void set_send_intvl_esc(void) +{ + 8007a2c: b580 push {r7, lr} + 8007a2e: af00 add r7, sp, #0 + settings_copy.send_interval_opt = p_settings->send_interval_opt; //exit no save, reset value + 8007a30: 4b05 ldr r3, [pc, #20] ; (8007a48 ) + 8007a32: 681b ldr r3, [r3, #0] + 8007a34: 795a ldrb r2, [r3, #5] + 8007a36: 4b05 ldr r3, [pc, #20] ; (8007a4c ) + 8007a38: 715a strb r2, [r3, #5] + current_menu = M_EDIT_SETTINGS; + 8007a3a: 4b05 ldr r3, [pc, #20] ; (8007a50 ) + 8007a3c: 2210 movs r2, #16 + 8007a3e: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007a40: f7fc fc52 bl 80042e8 +} + 8007a44: bf00 nop + 8007a46: bd80 pop {r7, pc} + 8007a48: 2000061c .word 0x2000061c + 8007a4c: 200007e0 .word 0x200007e0 + 8007a50: 200007fa .word 0x200007fa + +08007a54 : + + + +void set_to_thr_up(void) +{ + 8007a54: b580 push {r7, lr} + 8007a56: af00 add r7, sp, #0 + #define TIMEOUT_THRESHOLD_MAX (3600) + #define TIMEOUT_THRESHOLD_STEP (10) + + if (settings_copy.timeout_threshold.as_integer < TIMEOUT_THRESHOLD_MAX) + 8007a58: 4b07 ldr r3, [pc, #28] ; (8007a78 ) + 8007a5a: 88db ldrh r3, [r3, #6] + 8007a5c: f5b3 6f61 cmp.w r3, #3600 ; 0xe10 + 8007a60: d205 bcs.n 8007a6e + { + settings_copy.timeout_threshold.as_integer += TIMEOUT_THRESHOLD_STEP; + 8007a62: 4b05 ldr r3, [pc, #20] ; (8007a78 ) + 8007a64: 88db ldrh r3, [r3, #6] + 8007a66: 330a adds r3, #10 + 8007a68: b29a uxth r2, r3 + 8007a6a: 4b03 ldr r3, [pc, #12] ; (8007a78 ) + 8007a6c: 80da strh r2, [r3, #6] + } + + draw_current_menu(); + 8007a6e: f7fc fc3b bl 80042e8 +} + 8007a72: bf00 nop + 8007a74: bd80 pop {r7, pc} + 8007a76: bf00 nop + 8007a78: 200007e0 .word 0x200007e0 + +08007a7c : + + + +void set_to_thr_down(void) +{ + 8007a7c: b580 push {r7, lr} + 8007a7e: af00 add r7, sp, #0 + #define TIMEOUT_THRESHOLD_MIN (0) + + if (settings_copy.timeout_threshold.as_integer > TIMEOUT_THRESHOLD_MIN) + 8007a80: 4b06 ldr r3, [pc, #24] ; (8007a9c ) + 8007a82: 88db ldrh r3, [r3, #6] + 8007a84: 2b00 cmp r3, #0 + 8007a86: d005 beq.n 8007a94 + { + settings_copy.timeout_threshold.as_integer -= TIMEOUT_THRESHOLD_STEP; + 8007a88: 4b04 ldr r3, [pc, #16] ; (8007a9c ) + 8007a8a: 88db ldrh r3, [r3, #6] + 8007a8c: 3b0a subs r3, #10 + 8007a8e: b29a uxth r2, r3 + 8007a90: 4b02 ldr r3, [pc, #8] ; (8007a9c ) + 8007a92: 80da strh r2, [r3, #6] + } + + draw_current_menu(); + 8007a94: f7fc fc28 bl 80042e8 +} + 8007a98: bf00 nop + 8007a9a: bd80 pop {r7, pc} + 8007a9c: 200007e0 .word 0x200007e0 + +08007aa0 : + + + +void set_to_thr_ok(void) +{ + 8007aa0: b580 push {r7, lr} + 8007aa2: af00 add r7, sp, #0 + if (settings_copy.timeout_threshold.as_integer != p_settings->timeout_threshold.as_integer) + 8007aa4: 4b08 ldr r3, [pc, #32] ; (8007ac8 ) + 8007aa6: 88da ldrh r2, [r3, #6] + 8007aa8: 4b08 ldr r3, [pc, #32] ; (8007acc ) + 8007aaa: 681b ldr r3, [r3, #0] + 8007aac: 88db ldrh r3, [r3, #6] + 8007aae: 429a cmp r2, r3 + 8007ab0: d002 beq.n 8007ab8 + { + flag_settings_changed = 1; + 8007ab2: 4b07 ldr r3, [pc, #28] ; (8007ad0 ) + 8007ab4: 2201 movs r2, #1 + 8007ab6: 701a strb r2, [r3, #0] + } + + current_menu = M_EDIT_SETTINGS; + 8007ab8: 4b06 ldr r3, [pc, #24] ; (8007ad4 ) + 8007aba: 2210 movs r2, #16 + 8007abc: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007abe: f7fc fc13 bl 80042e8 +} + 8007ac2: bf00 nop + 8007ac4: bd80 pop {r7, pc} + 8007ac6: bf00 nop + 8007ac8: 200007e0 .word 0x200007e0 + 8007acc: 2000061c .word 0x2000061c + 8007ad0: 2000011e .word 0x2000011e + 8007ad4: 200007fa .word 0x200007fa + +08007ad8 : + + + +void set_to_thr_esc(void) +{ + 8007ad8: b580 push {r7, lr} + 8007ada: af00 add r7, sp, #0 + settings_copy.timeout_threshold.as_integer = p_settings->timeout_threshold.as_integer; //exit no save, reset value + 8007adc: 4b05 ldr r3, [pc, #20] ; (8007af4 ) + 8007ade: 681b ldr r3, [r3, #0] + 8007ae0: 88da ldrh r2, [r3, #6] + 8007ae2: 4b05 ldr r3, [pc, #20] ; (8007af8 ) + 8007ae4: 80da strh r2, [r3, #6] + current_menu = M_EDIT_SETTINGS; + 8007ae6: 4b05 ldr r3, [pc, #20] ; (8007afc ) + 8007ae8: 2210 movs r2, #16 + 8007aea: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007aec: f7fc fbfc bl 80042e8 +} + 8007af0: bf00 nop + 8007af2: bd80 pop {r7, pc} + 8007af4: 2000061c .word 0x2000061c + 8007af8: 200007e0 .word 0x200007e0 + 8007afc: 200007fa .word 0x200007fa + +08007b00 : + + + +void set_fnc_thr_up(void) +{ + 8007b00: b580 push {r7, lr} + 8007b02: af00 add r7, sp, #0 + #define FENCE_THRESHOLD_MAX (3600) + #define FENCE_THRESHOLD_STEP (10) + + if (settings_copy.fence_threshold.as_integer < FENCE_THRESHOLD_MAX) + 8007b04: 4b07 ldr r3, [pc, #28] ; (8007b24 ) + 8007b06: 891b ldrh r3, [r3, #8] + 8007b08: f5b3 6f61 cmp.w r3, #3600 ; 0xe10 + 8007b0c: d205 bcs.n 8007b1a + { + settings_copy.fence_threshold.as_integer += FENCE_THRESHOLD_STEP; + 8007b0e: 4b05 ldr r3, [pc, #20] ; (8007b24 ) + 8007b10: 891b ldrh r3, [r3, #8] + 8007b12: 330a adds r3, #10 + 8007b14: b29a uxth r2, r3 + 8007b16: 4b03 ldr r3, [pc, #12] ; (8007b24 ) + 8007b18: 811a strh r2, [r3, #8] + } + + draw_current_menu(); + 8007b1a: f7fc fbe5 bl 80042e8 +} + 8007b1e: bf00 nop + 8007b20: bd80 pop {r7, pc} + 8007b22: bf00 nop + 8007b24: 200007e0 .word 0x200007e0 + +08007b28 : + + + +void set_fnc_thr_down(void) +{ + 8007b28: b580 push {r7, lr} + 8007b2a: af00 add r7, sp, #0 + #define FENCE_THRESHOLD_MIN (0) + + if (settings_copy.fence_threshold.as_integer > FENCE_THRESHOLD_MIN) + 8007b2c: 4b06 ldr r3, [pc, #24] ; (8007b48 ) + 8007b2e: 891b ldrh r3, [r3, #8] + 8007b30: 2b00 cmp r3, #0 + 8007b32: d005 beq.n 8007b40 + { + settings_copy.fence_threshold.as_integer -= FENCE_THRESHOLD_STEP; + 8007b34: 4b04 ldr r3, [pc, #16] ; (8007b48 ) + 8007b36: 891b ldrh r3, [r3, #8] + 8007b38: 3b0a subs r3, #10 + 8007b3a: b29a uxth r2, r3 + 8007b3c: 4b02 ldr r3, [pc, #8] ; (8007b48 ) + 8007b3e: 811a strh r2, [r3, #8] + } + + draw_current_menu(); + 8007b40: f7fc fbd2 bl 80042e8 +} + 8007b44: bf00 nop + 8007b46: bd80 pop {r7, pc} + 8007b48: 200007e0 .word 0x200007e0 + +08007b4c : + + + +void set_fnc_thr_ok(void) +{ + 8007b4c: b580 push {r7, lr} + 8007b4e: af00 add r7, sp, #0 + if (settings_copy.fence_threshold.as_integer != p_settings->fence_threshold.as_integer) + 8007b50: 4b08 ldr r3, [pc, #32] ; (8007b74 ) + 8007b52: 891a ldrh r2, [r3, #8] + 8007b54: 4b08 ldr r3, [pc, #32] ; (8007b78 ) + 8007b56: 681b ldr r3, [r3, #0] + 8007b58: 891b ldrh r3, [r3, #8] + 8007b5a: 429a cmp r2, r3 + 8007b5c: d002 beq.n 8007b64 + { + flag_settings_changed = 1; + 8007b5e: 4b07 ldr r3, [pc, #28] ; (8007b7c ) + 8007b60: 2201 movs r2, #1 + 8007b62: 701a strb r2, [r3, #0] + } + + current_menu = M_EDIT_SETTINGS; + 8007b64: 4b06 ldr r3, [pc, #24] ; (8007b80 ) + 8007b66: 2210 movs r2, #16 + 8007b68: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007b6a: f7fc fbbd bl 80042e8 +} + 8007b6e: bf00 nop + 8007b70: bd80 pop {r7, pc} + 8007b72: bf00 nop + 8007b74: 200007e0 .word 0x200007e0 + 8007b78: 2000061c .word 0x2000061c + 8007b7c: 2000011e .word 0x2000011e + 8007b80: 200007fa .word 0x200007fa + +08007b84 : + + + +void set_fnc_thr_esc(void) +{ + 8007b84: b580 push {r7, lr} + 8007b86: af00 add r7, sp, #0 + settings_copy.fence_threshold.as_integer = p_settings->fence_threshold.as_integer; //exit no save, reset value + 8007b88: 4b05 ldr r3, [pc, #20] ; (8007ba0 ) + 8007b8a: 681b ldr r3, [r3, #0] + 8007b8c: 891a ldrh r2, [r3, #8] + 8007b8e: 4b05 ldr r3, [pc, #20] ; (8007ba4 ) + 8007b90: 811a strh r2, [r3, #8] + current_menu = M_EDIT_SETTINGS; + 8007b92: 4b05 ldr r3, [pc, #20] ; (8007ba8 ) + 8007b94: 2210 movs r2, #16 + 8007b96: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007b98: f7fc fba6 bl 80042e8 +} + 8007b9c: bf00 nop + 8007b9e: bd80 pop {r7, pc} + 8007ba0: 2000061c .word 0x2000061c + 8007ba4: 200007e0 .word 0x200007e0 + 8007ba8: 200007fa .word 0x200007fa + +08007bac : + + + +void confirm_settings_save_esc(void) +{ + 8007bac: b580 push {r7, lr} + 8007bae: af00 add r7, sp, #0 + settings_copy = *p_settings; //reset to no changes state + 8007bb0: 4b09 ldr r3, [pc, #36] ; (8007bd8 ) + 8007bb2: 681a ldr r2, [r3, #0] + 8007bb4: 4b09 ldr r3, [pc, #36] ; (8007bdc ) + 8007bb6: 6810 ldr r0, [r2, #0] + 8007bb8: 6851 ldr r1, [r2, #4] + 8007bba: 6018 str r0, [r3, #0] + 8007bbc: 6059 str r1, [r3, #4] + 8007bbe: 8912 ldrh r2, [r2, #8] + 8007bc0: 811a strh r2, [r3, #8] + flag_settings_changed = 0; //clear flag + 8007bc2: 4b07 ldr r3, [pc, #28] ; (8007be0 ) + 8007bc4: 2200 movs r2, #0 + 8007bc6: 701a strb r2, [r3, #0] + current_menu = M_SETTINGS; + 8007bc8: 4b06 ldr r3, [pc, #24] ; (8007be4 ) + 8007bca: 220e movs r2, #14 + 8007bcc: 701a strb r2, [r3, #0] + draw_current_menu(); + 8007bce: f7fc fb8b bl 80042e8 +} + 8007bd2: bf00 nop + 8007bd4: bd80 pop {r7, pc} + 8007bd6: bf00 nop + 8007bd8: 2000061c .word 0x2000061c + 8007bdc: 200007e0 .word 0x200007e0 + 8007be0: 2000011e .word 0x2000011e + 8007be4: 200007fa .word 0x200007fa + +08007be8 : + + + +void restore_defaults_ok(void) +{ + 8007be8: b580 push {r7, lr} + 8007bea: af00 add r7, sp, #0 + settings_save_default(); + 8007bec: f000 fef0 bl 80089d0 + NVIC_SystemReset(); + 8007bf0: f7fc f91a bl 8003e28 +} + 8007bf4: bf00 nop + 8007bf6: bd80 pop {r7, pc} + +08007bf8 : + + + +void erase_all_ok(void) +{ + 8007bf8: b580 push {r7, lr} + 8007bfa: af00 add r7, sp, #0 + ssd1306_clear(); + 8007bfc: f001 fa68 bl 80090d0 + ssd1306_print(0, 1, "WAIT...", 0); + 8007c00: 2300 movs r3, #0 + 8007c02: 4a06 ldr r2, [pc, #24] ; (8007c1c ) + 8007c04: 2101 movs r1, #1 + 8007c06: 2000 movs r0, #0 + 8007c08: f001 fb69 bl 80092de + ssd1306_update(); + 8007c0c: f001 fa40 bl 8009090 + m24c64_erase_all(); + 8007c10: f7fb ff15 bl 8003a3e + NVIC_SystemReset(); + 8007c14: f7fc f908 bl 8003e28 +} + 8007c18: bf00 nop + 8007c1a: bd80 pop {r7, pc} + 8007c1c: 0800cdb4 .word 0x0800cdb4 + +08007c20 : +char *memory_slot_names[MEMORY_SLOTS_TOTAL + 1] = MEMORY_SLOT_NAMES; + + + +struct memory_slot_struct **get_memory_slot(void) +{ + 8007c20: b480 push {r7} + 8007c22: b083 sub sp, #12 + 8007c24: af00 add r7, sp, #0 + for (uint8_t slot = 1; slot <= MEMORY_SLOTS_TOTAL; slot++) + 8007c26: 2301 movs r3, #1 + 8007c28: 71fb strb r3, [r7, #7] + 8007c2a: e00c b.n 8007c46 + { + p_memory_slot[slot] = &memory_slot[slot]; + 8007c2c: 79fa ldrb r2, [r7, #7] + 8007c2e: 79f9 ldrb r1, [r7, #7] + 8007c30: 4613 mov r3, r2 + 8007c32: 011b lsls r3, r3, #4 + 8007c34: 4413 add r3, r2 + 8007c36: 4a08 ldr r2, [pc, #32] ; (8007c58 ) + 8007c38: 4413 add r3, r2 + 8007c3a: 4a08 ldr r2, [pc, #32] ; (8007c5c ) + 8007c3c: f842 3021 str.w r3, [r2, r1, lsl #2] + for (uint8_t slot = 1; slot <= MEMORY_SLOTS_TOTAL; slot++) + 8007c40: 79fb ldrb r3, [r7, #7] + 8007c42: 3301 adds r3, #1 + 8007c44: 71fb strb r3, [r7, #7] + 8007c46: 79fb ldrb r3, [r7, #7] + 8007c48: 2b05 cmp r3, #5 + 8007c4a: d9ef bls.n 8007c2c + } + + return &p_memory_slot[0]; + 8007c4c: 4b03 ldr r3, [pc, #12] ; (8007c5c ) +} + 8007c4e: 4618 mov r0, r3 + 8007c50: 370c adds r7, #12 + 8007c52: 46bd mov sp, r7 + 8007c54: bc80 pop {r7} + 8007c56: 4770 bx lr + 8007c58: 20000878 .word 0x20000878 + 8007c5c: 20000860 .word 0x20000860 + +08007c60 : + + + +void init_points(void) +{ + 8007c60: b580 push {r7, lr} + 8007c62: b082 sub sp, #8 + 8007c64: af00 add r7, sp, #0 + p_gps_raw = get_gps_raw(); + 8007c66: f7fa fce9 bl 800263c + 8007c6a: 4602 mov r2, r0 + 8007c6c: 4b1e ldr r3, [pc, #120] ; (8007ce8 ) + 8007c6e: 601a str r2, [r3, #0] + pp_gps_air = get_gps_air(); + 8007c70: f7fb fc1e bl 80034b0 + 8007c74: 4602 mov r2, r0 + 8007c76: 4b1d ldr r3, [pc, #116] ; (8007cec ) + 8007c78: 601a str r2, [r3, #0] + pp_dev_aux = get_dev_aux(); + 8007c7a: f7fb fc59 bl 8003530 + 8007c7e: 4602 mov r2, r0 + 8007c80: 4b1b ldr r3, [pc, #108] ; (8007cf0 ) + 8007c82: 601a str r2, [r3, #0] + + for (uint8_t slot = 1; slot <= MEMORY_SLOTS_TOTAL; slot++) + 8007c84: 2301 movs r3, #1 + 8007c86: 71fb strb r3, [r7, #7] + 8007c88: e027 b.n 8007cda + { + memory_slot[slot].slot_name[0] = memory_slot_names[slot][0]; //init slot names + 8007c8a: 79fb ldrb r3, [r7, #7] + 8007c8c: 4a19 ldr r2, [pc, #100] ; (8007cf4 ) + 8007c8e: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8007c92: 79fa ldrb r2, [r7, #7] + 8007c94: 7818 ldrb r0, [r3, #0] + 8007c96: 4918 ldr r1, [pc, #96] ; (8007cf8 ) + 8007c98: 4613 mov r3, r2 + 8007c9a: 011b lsls r3, r3, #4 + 8007c9c: 4413 add r3, r2 + 8007c9e: 440b add r3, r1 + 8007ca0: 3301 adds r3, #1 + 8007ca2: 4602 mov r2, r0 + 8007ca4: 701a strb r2, [r3, #0] + memory_slot[slot].slot_name[1] = memory_slot_names[slot][1]; + 8007ca6: 79fb ldrb r3, [r7, #7] + 8007ca8: 4a12 ldr r2, [pc, #72] ; (8007cf4 ) + 8007caa: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8007cae: 79fa ldrb r2, [r7, #7] + 8007cb0: 7858 ldrb r0, [r3, #1] + 8007cb2: 4911 ldr r1, [pc, #68] ; (8007cf8 ) + 8007cb4: 4613 mov r3, r2 + 8007cb6: 011b lsls r3, r3, #4 + 8007cb8: 4413 add r3, r2 + 8007cba: 440b add r3, r1 + 8007cbc: 3302 adds r3, #2 + 8007cbe: 4602 mov r2, r0 + 8007cc0: 701a strb r2, [r3, #0] + memory_slot[slot].slot_name[2] = 0; + 8007cc2: 79fa ldrb r2, [r7, #7] + 8007cc4: 490c ldr r1, [pc, #48] ; (8007cf8 ) + 8007cc6: 4613 mov r3, r2 + 8007cc8: 011b lsls r3, r3, #4 + 8007cca: 4413 add r3, r2 + 8007ccc: 440b add r3, r1 + 8007cce: 3303 adds r3, #3 + 8007cd0: 2200 movs r2, #0 + 8007cd2: 701a strb r2, [r3, #0] + for (uint8_t slot = 1; slot <= MEMORY_SLOTS_TOTAL; slot++) + 8007cd4: 79fb ldrb r3, [r7, #7] + 8007cd6: 3301 adds r3, #1 + 8007cd8: 71fb strb r3, [r7, #7] + 8007cda: 79fb ldrb r3, [r7, #7] + 8007cdc: 2b05 cmp r3, #5 + 8007cde: d9d4 bls.n 8007c8a + } +} + 8007ce0: bf00 nop + 8007ce2: 3708 adds r7, #8 + 8007ce4: 46bd mov sp, r7 + 8007ce6: bd80 pop {r7, pc} + 8007ce8: 20000808 .word 0x20000808 + 8007cec: 20000804 .word 0x20000804 + 8007cf0: 2000083c .word 0x2000083c + 8007cf4: 20000038 .word 0x20000038 + 8007cf8: 20000878 .word 0x20000878 + +08007cfc : + + + +void read_memory_slots(void) +{ + 8007cfc: b580 push {r7, lr} + 8007cfe: b082 sub sp, #8 + 8007d00: af00 add r7, sp, #0 + for (uint8_t slot = 1; slot <= MEMORY_SLOTS_TOTAL; slot++) + 8007d02: 2301 movs r3, #1 + 8007d04: 71fb strb r3, [r7, #7] + 8007d06: e0a1 b.n 8007e4c + { + + clear_point_buffer(); + 8007d08: f000 fa4a bl 80081a0 + m24c64_read_page(&point_buffer[0], slot); + 8007d0c: 79fb ldrb r3, [r7, #7] + 8007d0e: 4619 mov r1, r3 + 8007d10: 4852 ldr r0, [pc, #328] ; (8007e5c ) + 8007d12: f7fb fd2d bl 8003770 + + if (point_buffer[MEMORY_POINT_EXIST_FLAG_POS] == POINT_EXIST_FLAG_DEFAULT) + 8007d16: 4b51 ldr r3, [pc, #324] ; (8007e5c ) + 8007d18: 781b ldrb r3, [r3, #0] + 8007d1a: 2baa cmp r3, #170 ; 0xaa + 8007d1c: f040 808b bne.w 8007e36 + { + memory_slot[slot].exist_flag = 1; + 8007d20: 79fa ldrb r2, [r7, #7] + 8007d22: 494f ldr r1, [pc, #316] ; (8007e60 ) + 8007d24: 4613 mov r3, r2 + 8007d26: 011b lsls r3, r3, #4 + 8007d28: 4413 add r3, r2 + 8007d2a: 440b add r3, r1 + 8007d2c: 2201 movs r2, #1 + 8007d2e: 701a strb r2, [r3, #0] + + memory_slot[slot].point_name[0] = point_buffer[MEMORY_POINT_NAME_POS]; + 8007d30: 79fa ldrb r2, [r7, #7] + 8007d32: 4b4a ldr r3, [pc, #296] ; (8007e5c ) + 8007d34: 7858 ldrb r0, [r3, #1] + 8007d36: 494a ldr r1, [pc, #296] ; (8007e60 ) + 8007d38: 4613 mov r3, r2 + 8007d3a: 011b lsls r3, r3, #4 + 8007d3c: 4413 add r3, r2 + 8007d3e: 440b add r3, r1 + 8007d40: 3304 adds r3, #4 + 8007d42: 4602 mov r2, r0 + 8007d44: 701a strb r2, [r3, #0] + memory_slot[slot].point_name[1] = point_buffer[MEMORY_POINT_NAME_POS + 1]; + 8007d46: 79fa ldrb r2, [r7, #7] + 8007d48: 4b44 ldr r3, [pc, #272] ; (8007e5c ) + 8007d4a: 7898 ldrb r0, [r3, #2] + 8007d4c: 4944 ldr r1, [pc, #272] ; (8007e60 ) + 8007d4e: 4613 mov r3, r2 + 8007d50: 011b lsls r3, r3, #4 + 8007d52: 4413 add r3, r2 + 8007d54: 440b add r3, r1 + 8007d56: 3305 adds r3, #5 + 8007d58: 4602 mov r2, r0 + 8007d5a: 701a strb r2, [r3, #0] + memory_slot[slot].point_name[2] = point_buffer[MEMORY_POINT_NAME_POS + 2]; + 8007d5c: 79fa ldrb r2, [r7, #7] + 8007d5e: 4b3f ldr r3, [pc, #252] ; (8007e5c ) + 8007d60: 78d8 ldrb r0, [r3, #3] + 8007d62: 493f ldr r1, [pc, #252] ; (8007e60 ) + 8007d64: 4613 mov r3, r2 + 8007d66: 011b lsls r3, r3, #4 + 8007d68: 4413 add r3, r2 + 8007d6a: 440b add r3, r1 + 8007d6c: 3306 adds r3, #6 + 8007d6e: 4602 mov r2, r0 + 8007d70: 701a strb r2, [r3, #0] + memory_slot[slot].point_name[3] = point_buffer[MEMORY_POINT_NAME_POS + 3]; + 8007d72: 79fa ldrb r2, [r7, #7] + 8007d74: 4b39 ldr r3, [pc, #228] ; (8007e5c ) + 8007d76: 7918 ldrb r0, [r3, #4] + 8007d78: 4939 ldr r1, [pc, #228] ; (8007e60 ) + 8007d7a: 4613 mov r3, r2 + 8007d7c: 011b lsls r3, r3, #4 + 8007d7e: 4413 add r3, r2 + 8007d80: 440b add r3, r1 + 8007d82: 3307 adds r3, #7 + 8007d84: 4602 mov r2, r0 + 8007d86: 701a strb r2, [r3, #0] + memory_slot[slot].point_name[4] = point_buffer[MEMORY_POINT_NAME_POS + 4]; + 8007d88: 79fa ldrb r2, [r7, #7] + 8007d8a: 4b34 ldr r3, [pc, #208] ; (8007e5c ) + 8007d8c: 7958 ldrb r0, [r3, #5] + 8007d8e: 4934 ldr r1, [pc, #208] ; (8007e60 ) + 8007d90: 4613 mov r3, r2 + 8007d92: 011b lsls r3, r3, #4 + 8007d94: 4413 add r3, r2 + 8007d96: 440b add r3, r1 + 8007d98: 3308 adds r3, #8 + 8007d9a: 4602 mov r2, r0 + 8007d9c: 701a strb r2, [r3, #0] + memory_slot[slot].point_name[5] = 0; + 8007d9e: 79fa ldrb r2, [r7, #7] + 8007da0: 492f ldr r1, [pc, #188] ; (8007e60 ) + 8007da2: 4613 mov r3, r2 + 8007da4: 011b lsls r3, r3, #4 + 8007da6: 4413 add r3, r2 + 8007da8: 440b add r3, r1 + 8007daa: 3309 adds r3, #9 + 8007dac: 2200 movs r2, #0 + 8007dae: 701a strb r2, [r3, #0] + + memory_slot[slot].save_date[0] = point_buffer[MEMORY_POINT_DAY_POS]; + 8007db0: 79fa ldrb r2, [r7, #7] + 8007db2: 4b2a ldr r3, [pc, #168] ; (8007e5c ) + 8007db4: 7998 ldrb r0, [r3, #6] + 8007db6: 492a ldr r1, [pc, #168] ; (8007e60 ) + 8007db8: 4613 mov r3, r2 + 8007dba: 011b lsls r3, r3, #4 + 8007dbc: 4413 add r3, r2 + 8007dbe: 440b add r3, r1 + 8007dc0: 330a adds r3, #10 + 8007dc2: 4602 mov r2, r0 + 8007dc4: 701a strb r2, [r3, #0] + memory_slot[slot].save_date[1] = point_buffer[MEMORY_POINT_DAY_POS + 1]; + 8007dc6: 79fa ldrb r2, [r7, #7] + 8007dc8: 4b24 ldr r3, [pc, #144] ; (8007e5c ) + 8007dca: 79d8 ldrb r0, [r3, #7] + 8007dcc: 4924 ldr r1, [pc, #144] ; (8007e60 ) + 8007dce: 4613 mov r3, r2 + 8007dd0: 011b lsls r3, r3, #4 + 8007dd2: 4413 add r3, r2 + 8007dd4: 440b add r3, r1 + 8007dd6: 330b adds r3, #11 + 8007dd8: 4602 mov r2, r0 + 8007dda: 701a strb r2, [r3, #0] + memory_slot[slot].save_date[2] = point_buffer[MEMORY_POINT_MONTH_POS]; + 8007ddc: 79fa ldrb r2, [r7, #7] + 8007dde: 4b1f ldr r3, [pc, #124] ; (8007e5c ) + 8007de0: 7a18 ldrb r0, [r3, #8] + 8007de2: 491f ldr r1, [pc, #124] ; (8007e60 ) + 8007de4: 4613 mov r3, r2 + 8007de6: 011b lsls r3, r3, #4 + 8007de8: 4413 add r3, r2 + 8007dea: 440b add r3, r1 + 8007dec: 330c adds r3, #12 + 8007dee: 4602 mov r2, r0 + 8007df0: 701a strb r2, [r3, #0] + memory_slot[slot].save_date[3] = point_buffer[MEMORY_POINT_MONTH_POS + 1]; + 8007df2: 79fa ldrb r2, [r7, #7] + 8007df4: 4b19 ldr r3, [pc, #100] ; (8007e5c ) + 8007df6: 7a58 ldrb r0, [r3, #9] + 8007df8: 4919 ldr r1, [pc, #100] ; (8007e60 ) + 8007dfa: 4613 mov r3, r2 + 8007dfc: 011b lsls r3, r3, #4 + 8007dfe: 4413 add r3, r2 + 8007e00: 440b add r3, r1 + 8007e02: 330d adds r3, #13 + 8007e04: 4602 mov r2, r0 + 8007e06: 701a strb r2, [r3, #0] + memory_slot[slot].save_date[4] = point_buffer[MEMORY_POINT_YEAR_POS]; + 8007e08: 79fa ldrb r2, [r7, #7] + 8007e0a: 4b14 ldr r3, [pc, #80] ; (8007e5c ) + 8007e0c: 7a98 ldrb r0, [r3, #10] + 8007e0e: 4914 ldr r1, [pc, #80] ; (8007e60 ) + 8007e10: 4613 mov r3, r2 + 8007e12: 011b lsls r3, r3, #4 + 8007e14: 4413 add r3, r2 + 8007e16: 440b add r3, r1 + 8007e18: 330e adds r3, #14 + 8007e1a: 4602 mov r2, r0 + 8007e1c: 701a strb r2, [r3, #0] + memory_slot[slot].save_date[5] = point_buffer[MEMORY_POINT_YEAR_POS + 1]; + 8007e1e: 79fa ldrb r2, [r7, #7] + 8007e20: 4b0e ldr r3, [pc, #56] ; (8007e5c ) + 8007e22: 7ad8 ldrb r0, [r3, #11] + 8007e24: 490e ldr r1, [pc, #56] ; (8007e60 ) + 8007e26: 4613 mov r3, r2 + 8007e28: 011b lsls r3, r3, #4 + 8007e2a: 4413 add r3, r2 + 8007e2c: 440b add r3, r1 + 8007e2e: 330f adds r3, #15 + 8007e30: 4602 mov r2, r0 + 8007e32: 701a strb r2, [r3, #0] + 8007e34: e007 b.n 8007e46 + } + else + { + memory_slot[slot].exist_flag = 0; + 8007e36: 79fa ldrb r2, [r7, #7] + 8007e38: 4909 ldr r1, [pc, #36] ; (8007e60 ) + 8007e3a: 4613 mov r3, r2 + 8007e3c: 011b lsls r3, r3, #4 + 8007e3e: 4413 add r3, r2 + 8007e40: 440b add r3, r1 + 8007e42: 2200 movs r2, #0 + 8007e44: 701a strb r2, [r3, #0] + for (uint8_t slot = 1; slot <= MEMORY_SLOTS_TOTAL; slot++) + 8007e46: 79fb ldrb r3, [r7, #7] + 8007e48: 3301 adds r3, #1 + 8007e4a: 71fb strb r3, [r7, #7] + 8007e4c: 79fb ldrb r3, [r7, #7] + 8007e4e: 2b05 cmp r3, #5 + 8007e50: f67f af5a bls.w 8007d08 + } + } +} + 8007e54: bf00 nop + 8007e56: 3708 adds r7, #8 + 8007e58: 46bd mov sp, r7 + 8007e5a: bd80 pop {r7, pc} + 8007e5c: 20000840 .word 0x20000840 + 8007e60: 20000878 .word 0x20000878 + +08007e64 : + + + +//Save selected device in a slot +void save_memory_point(uint8_t dev_num, char *point_name, uint8_t slot_num) +{ + 8007e64: b580 push {r7, lr} + 8007e66: b082 sub sp, #8 + 8007e68: af00 add r7, sp, #0 + 8007e6a: 4603 mov r3, r0 + 8007e6c: 6039 str r1, [r7, #0] + 8007e6e: 71fb strb r3, [r7, #7] + 8007e70: 4613 mov r3, r2 + 8007e72: 71bb strb r3, [r7, #6] + clear_point_buffer(); + 8007e74: f000 f994 bl 80081a0 + + point_buffer[MEMORY_POINT_EXIST_FLAG_POS] = POINT_EXIST_FLAG_DEFAULT; + 8007e78: 4b4d ldr r3, [pc, #308] ; (8007fb0 ) + 8007e7a: 22aa movs r2, #170 ; 0xaa + 8007e7c: 701a strb r2, [r3, #0] + + point_buffer[MEMORY_POINT_NAME_POS] = point_name[0]; + 8007e7e: 683b ldr r3, [r7, #0] + 8007e80: 781a ldrb r2, [r3, #0] + 8007e82: 4b4b ldr r3, [pc, #300] ; (8007fb0 ) + 8007e84: 705a strb r2, [r3, #1] + point_buffer[MEMORY_POINT_NAME_POS + 1] = point_name[1]; + 8007e86: 683b ldr r3, [r7, #0] + 8007e88: 3301 adds r3, #1 + 8007e8a: 781a ldrb r2, [r3, #0] + 8007e8c: 4b48 ldr r3, [pc, #288] ; (8007fb0 ) + 8007e8e: 709a strb r2, [r3, #2] + point_buffer[MEMORY_POINT_NAME_POS + 2] = point_name[2]; + 8007e90: 683b ldr r3, [r7, #0] + 8007e92: 3302 adds r3, #2 + 8007e94: 781a ldrb r2, [r3, #0] + 8007e96: 4b46 ldr r3, [pc, #280] ; (8007fb0 ) + 8007e98: 70da strb r2, [r3, #3] + point_buffer[MEMORY_POINT_NAME_POS + 3] = point_name[3]; + 8007e9a: 683b ldr r3, [r7, #0] + 8007e9c: 3303 adds r3, #3 + 8007e9e: 781a ldrb r2, [r3, #0] + 8007ea0: 4b43 ldr r3, [pc, #268] ; (8007fb0 ) + 8007ea2: 711a strb r2, [r3, #4] + point_buffer[MEMORY_POINT_NAME_POS + 4] = point_name[4]; + 8007ea4: 683b ldr r3, [r7, #0] + 8007ea6: 3304 adds r3, #4 + 8007ea8: 781a ldrb r2, [r3, #0] + 8007eaa: 4b41 ldr r3, [pc, #260] ; (8007fb0 ) + 8007eac: 715a strb r2, [r3, #5] + + point_buffer[MEMORY_POINT_DAY_POS] = p_gps_raw->date[0]; //save in char format for easy print in the menu + 8007eae: 4b41 ldr r3, [pc, #260] ; (8007fb4 ) + 8007eb0: 681b ldr r3, [r3, #0] + 8007eb2: 7b1a ldrb r2, [r3, #12] + 8007eb4: 4b3e ldr r3, [pc, #248] ; (8007fb0 ) + 8007eb6: 719a strb r2, [r3, #6] + point_buffer[MEMORY_POINT_DAY_POS + 1] = p_gps_raw->date[1]; + 8007eb8: 4b3e ldr r3, [pc, #248] ; (8007fb4 ) + 8007eba: 681b ldr r3, [r3, #0] + 8007ebc: 7b5a ldrb r2, [r3, #13] + 8007ebe: 4b3c ldr r3, [pc, #240] ; (8007fb0 ) + 8007ec0: 71da strb r2, [r3, #7] + + point_buffer[MEMORY_POINT_MONTH_POS] = p_gps_raw->date[2]; + 8007ec2: 4b3c ldr r3, [pc, #240] ; (8007fb4 ) + 8007ec4: 681b ldr r3, [r3, #0] + 8007ec6: 7b9a ldrb r2, [r3, #14] + 8007ec8: 4b39 ldr r3, [pc, #228] ; (8007fb0 ) + 8007eca: 721a strb r2, [r3, #8] + point_buffer[MEMORY_POINT_MONTH_POS + 1] = p_gps_raw->date[3]; + 8007ecc: 4b39 ldr r3, [pc, #228] ; (8007fb4 ) + 8007ece: 681b ldr r3, [r3, #0] + 8007ed0: 7bda ldrb r2, [r3, #15] + 8007ed2: 4b37 ldr r3, [pc, #220] ; (8007fb0 ) + 8007ed4: 725a strb r2, [r3, #9] + + point_buffer[MEMORY_POINT_YEAR_POS] = p_gps_raw->date[4]; + 8007ed6: 4b37 ldr r3, [pc, #220] ; (8007fb4 ) + 8007ed8: 681b ldr r3, [r3, #0] + 8007eda: 7c1a ldrb r2, [r3, #16] + 8007edc: 4b34 ldr r3, [pc, #208] ; (8007fb0 ) + 8007ede: 729a strb r2, [r3, #10] + point_buffer[MEMORY_POINT_YEAR_POS + 1] = p_gps_raw->date[5]; + 8007ee0: 4b34 ldr r3, [pc, #208] ; (8007fb4 ) + 8007ee2: 681b ldr r3, [r3, #0] + 8007ee4: 7c5a ldrb r2, [r3, #17] + 8007ee6: 4b32 ldr r3, [pc, #200] ; (8007fb0 ) + 8007ee8: 72da strb r2, [r3, #11] + + point_buffer[MEMORY_POINT_LATITUDE_POS] = pp_gps_air[dev_num]->latitude.as_array[0]; + 8007eea: 4b33 ldr r3, [pc, #204] ; (8007fb8 ) + 8007eec: 681a ldr r2, [r3, #0] + 8007eee: 79fb ldrb r3, [r7, #7] + 8007ef0: 009b lsls r3, r3, #2 + 8007ef2: 4413 add r3, r2 + 8007ef4: 681b ldr r3, [r3, #0] + 8007ef6: 791a ldrb r2, [r3, #4] + 8007ef8: 4b2d ldr r3, [pc, #180] ; (8007fb0 ) + 8007efa: 731a strb r2, [r3, #12] + point_buffer[MEMORY_POINT_LATITUDE_POS + 1] = pp_gps_air[dev_num]->latitude.as_array[1]; + 8007efc: 4b2e ldr r3, [pc, #184] ; (8007fb8 ) + 8007efe: 681a ldr r2, [r3, #0] + 8007f00: 79fb ldrb r3, [r7, #7] + 8007f02: 009b lsls r3, r3, #2 + 8007f04: 4413 add r3, r2 + 8007f06: 681b ldr r3, [r3, #0] + 8007f08: 795a ldrb r2, [r3, #5] + 8007f0a: 4b29 ldr r3, [pc, #164] ; (8007fb0 ) + 8007f0c: 735a strb r2, [r3, #13] + point_buffer[MEMORY_POINT_LATITUDE_POS + 2] = pp_gps_air[dev_num]->latitude.as_array[2]; + 8007f0e: 4b2a ldr r3, [pc, #168] ; (8007fb8 ) + 8007f10: 681a ldr r2, [r3, #0] + 8007f12: 79fb ldrb r3, [r7, #7] + 8007f14: 009b lsls r3, r3, #2 + 8007f16: 4413 add r3, r2 + 8007f18: 681b ldr r3, [r3, #0] + 8007f1a: 799a ldrb r2, [r3, #6] + 8007f1c: 4b24 ldr r3, [pc, #144] ; (8007fb0 ) + 8007f1e: 739a strb r2, [r3, #14] + point_buffer[MEMORY_POINT_LATITUDE_POS + 3] = pp_gps_air[dev_num]->latitude.as_array[3]; + 8007f20: 4b25 ldr r3, [pc, #148] ; (8007fb8 ) + 8007f22: 681a ldr r2, [r3, #0] + 8007f24: 79fb ldrb r3, [r7, #7] + 8007f26: 009b lsls r3, r3, #2 + 8007f28: 4413 add r3, r2 + 8007f2a: 681b ldr r3, [r3, #0] + 8007f2c: 79da ldrb r2, [r3, #7] + 8007f2e: 4b20 ldr r3, [pc, #128] ; (8007fb0 ) + 8007f30: 73da strb r2, [r3, #15] + + point_buffer[MEMORY_POINT_LONGITUDE_POS] = pp_gps_air[dev_num]->longitude.as_array[0]; + 8007f32: 4b21 ldr r3, [pc, #132] ; (8007fb8 ) + 8007f34: 681a ldr r2, [r3, #0] + 8007f36: 79fb ldrb r3, [r7, #7] + 8007f38: 009b lsls r3, r3, #2 + 8007f3a: 4413 add r3, r2 + 8007f3c: 681b ldr r3, [r3, #0] + 8007f3e: 7a1a ldrb r2, [r3, #8] + 8007f40: 4b1b ldr r3, [pc, #108] ; (8007fb0 ) + 8007f42: 741a strb r2, [r3, #16] + point_buffer[MEMORY_POINT_LONGITUDE_POS + 1] = pp_gps_air[dev_num]->longitude.as_array[1]; + 8007f44: 4b1c ldr r3, [pc, #112] ; (8007fb8 ) + 8007f46: 681a ldr r2, [r3, #0] + 8007f48: 79fb ldrb r3, [r7, #7] + 8007f4a: 009b lsls r3, r3, #2 + 8007f4c: 4413 add r3, r2 + 8007f4e: 681b ldr r3, [r3, #0] + 8007f50: 7a5a ldrb r2, [r3, #9] + 8007f52: 4b17 ldr r3, [pc, #92] ; (8007fb0 ) + 8007f54: 745a strb r2, [r3, #17] + point_buffer[MEMORY_POINT_LONGITUDE_POS + 2] = pp_gps_air[dev_num]->longitude.as_array[2]; + 8007f56: 4b18 ldr r3, [pc, #96] ; (8007fb8 ) + 8007f58: 681a ldr r2, [r3, #0] + 8007f5a: 79fb ldrb r3, [r7, #7] + 8007f5c: 009b lsls r3, r3, #2 + 8007f5e: 4413 add r3, r2 + 8007f60: 681b ldr r3, [r3, #0] + 8007f62: 7a9a ldrb r2, [r3, #10] + 8007f64: 4b12 ldr r3, [pc, #72] ; (8007fb0 ) + 8007f66: 749a strb r2, [r3, #18] + point_buffer[MEMORY_POINT_LONGITUDE_POS + 3] = pp_gps_air[dev_num]->longitude.as_array[3]; + 8007f68: 4b13 ldr r3, [pc, #76] ; (8007fb8 ) + 8007f6a: 681a ldr r2, [r3, #0] + 8007f6c: 79fb ldrb r3, [r7, #7] + 8007f6e: 009b lsls r3, r3, #2 + 8007f70: 4413 add r3, r2 + 8007f72: 681b ldr r3, [r3, #0] + 8007f74: 7ada ldrb r2, [r3, #11] + 8007f76: 4b0e ldr r3, [pc, #56] ; (8007fb0 ) + 8007f78: 74da strb r2, [r3, #19] + + point_buffer[MEMORY_POINT_ALTITUDE_POS] = pp_gps_air[dev_num]->altitude.as_array[0]; + 8007f7a: 4b0f ldr r3, [pc, #60] ; (8007fb8 ) + 8007f7c: 681a ldr r2, [r3, #0] + 8007f7e: 79fb ldrb r3, [r7, #7] + 8007f80: 009b lsls r3, r3, #2 + 8007f82: 4413 add r3, r2 + 8007f84: 681b ldr r3, [r3, #0] + 8007f86: 7b1a ldrb r2, [r3, #12] + 8007f88: 4b09 ldr r3, [pc, #36] ; (8007fb0 ) + 8007f8a: 751a strb r2, [r3, #20] + point_buffer[MEMORY_POINT_ALTITUDE_POS + 1] = pp_gps_air[dev_num]->altitude.as_array[1]; + 8007f8c: 4b0a ldr r3, [pc, #40] ; (8007fb8 ) + 8007f8e: 681a ldr r2, [r3, #0] + 8007f90: 79fb ldrb r3, [r7, #7] + 8007f92: 009b lsls r3, r3, #2 + 8007f94: 4413 add r3, r2 + 8007f96: 681b ldr r3, [r3, #0] + 8007f98: 7b5a ldrb r2, [r3, #13] + 8007f9a: 4b05 ldr r3, [pc, #20] ; (8007fb0 ) + 8007f9c: 755a strb r2, [r3, #21] + + m24c64_write_page(&point_buffer[0], slot_num); + 8007f9e: 79bb ldrb r3, [r7, #6] + 8007fa0: 4619 mov r1, r3 + 8007fa2: 4803 ldr r0, [pc, #12] ; (8007fb0 ) + 8007fa4: f7fb fca8 bl 80038f8 +} + 8007fa8: bf00 nop + 8007faa: 3708 adds r7, #8 + 8007fac: 46bd mov sp, r7 + 8007fae: bd80 pop {r7, pc} + 8007fb0: 20000840 .word 0x20000840 + 8007fb4: 20000808 .word 0x20000808 + 8007fb8: 20000804 .word 0x20000804 + +08007fbc : + + + +void load_memory_point(uint8_t dev_num, uint8_t slot_num) +{ + 8007fbc: b5b0 push {r4, r5, r7, lr} + 8007fbe: b084 sub sp, #16 + 8007fc0: af00 add r7, sp, #0 + 8007fc2: 4603 mov r3, r0 + 8007fc4: 460a mov r2, r1 + 8007fc6: 71fb strb r3, [r7, #7] + 8007fc8: 4613 mov r3, r2 + 8007fca: 71bb strb r3, [r7, #6] + clear_point_buffer(); + 8007fcc: f000 f8e8 bl 80081a0 + + m24c64_read_page(&point_buffer[0], slot_num); + 8007fd0: 79bb ldrb r3, [r7, #6] + 8007fd2: 4619 mov r1, r3 + 8007fd4: 4865 ldr r0, [pc, #404] ; (800816c ) + 8007fd6: f7fb fbcb bl 8003770 + + memset(pp_gps_air[dev_num], 0, sizeof(*(pp_gps_air[dev_num]))); + 8007fda: 4b65 ldr r3, [pc, #404] ; (8008170 ) + 8007fdc: 681a ldr r2, [r3, #0] + 8007fde: 79fb ldrb r3, [r7, #7] + 8007fe0: 009b lsls r3, r3, #2 + 8007fe2: 4413 add r3, r2 + 8007fe4: 681b ldr r3, [r3, #0] + 8007fe6: 2214 movs r2, #20 + 8007fe8: 2100 movs r1, #0 + 8007fea: 4618 mov r0, r3 + 8007fec: f001 fcbf bl 800996e + memset(pp_dev_aux[dev_num], 0, sizeof(*(pp_dev_aux[dev_num]))); + 8007ff0: 4b60 ldr r3, [pc, #384] ; (8008174 ) + 8007ff2: 681a ldr r2, [r3, #0] + 8007ff4: 79fb ldrb r3, [r7, #7] + 8007ff6: 009b lsls r3, r3, #2 + 8007ff8: 4413 add r3, r2 + 8007ffa: 681b ldr r3, [r3, #0] + 8007ffc: 2218 movs r2, #24 + 8007ffe: 2100 movs r1, #0 + 8008000: 4618 mov r0, r3 + 8008002: f001 fcb4 bl 800996e + + pp_dev_aux[dev_num]->exist_flag = 1; + 8008006: 4b5b ldr r3, [pc, #364] ; (8008174 ) + 8008008: 681a ldr r2, [r3, #0] + 800800a: 79fb ldrb r3, [r7, #7] + 800800c: 009b lsls r3, r3, #2 + 800800e: 4413 add r3, r2 + 8008010: 681b ldr r3, [r3, #0] + 8008012: 2201 movs r2, #1 + 8008014: 701a strb r2, [r3, #0] + pp_dev_aux[dev_num]->memory_point_flag = 1; + 8008016: 4b57 ldr r3, [pc, #348] ; (8008174 ) + 8008018: 681a ldr r2, [r3, #0] + 800801a: 79fb ldrb r3, [r7, #7] + 800801c: 009b lsls r3, r3, #2 + 800801e: 4413 add r3, r2 + 8008020: 681b ldr r3, [r3, #0] + 8008022: 2201 movs r2, #1 + 8008024: 739a strb r2, [r3, #14] + pp_dev_aux[dev_num]->timestamp = get_uptime(); + 8008026: 4b53 ldr r3, [pc, #332] ; (8008174 ) + 8008028: 681a ldr r2, [r3, #0] + 800802a: 79fb ldrb r3, [r7, #7] + 800802c: 009b lsls r3, r3, #2 + 800802e: 4413 add r3, r2 + 8008030: 681c ldr r4, [r3, #0] + 8008032: f7fb fedd bl 8003df0 + 8008036: 4603 mov r3, r0 + 8008038: 6063 str r3, [r4, #4] + + for (uint8_t c = 0; c < MEMORY_POINT_NAME_LENGTH; c++) + 800803a: 2300 movs r3, #0 + 800803c: 73fb strb r3, [r7, #15] + 800803e: e015 b.n 800806c + { + pp_dev_aux[dev_num]->point_name[c] = memory_slot[slot_num].point_name[c]; + 8008040: 79ba ldrb r2, [r7, #6] + 8008042: 7bfc ldrb r4, [r7, #15] + 8008044: 4b4b ldr r3, [pc, #300] ; (8008174 ) + 8008046: 6819 ldr r1, [r3, #0] + 8008048: 79fb ldrb r3, [r7, #7] + 800804a: 009b lsls r3, r3, #2 + 800804c: 440b add r3, r1 + 800804e: 6818 ldr r0, [r3, #0] + 8008050: 7bf9 ldrb r1, [r7, #15] + 8008052: 4d49 ldr r5, [pc, #292] ; (8008178 ) + 8008054: 4613 mov r3, r2 + 8008056: 011b lsls r3, r3, #4 + 8008058: 4413 add r3, r2 + 800805a: 442b add r3, r5 + 800805c: 4423 add r3, r4 + 800805e: 3304 adds r3, #4 + 8008060: 781a ldrb r2, [r3, #0] + 8008062: 1843 adds r3, r0, r1 + 8008064: 73da strb r2, [r3, #15] + for (uint8_t c = 0; c < MEMORY_POINT_NAME_LENGTH; c++) + 8008066: 7bfb ldrb r3, [r7, #15] + 8008068: 3301 adds r3, #1 + 800806a: 73fb strb r3, [r7, #15] + 800806c: 7bfb ldrb r3, [r7, #15] + 800806e: 2b04 cmp r3, #4 + 8008070: d9e6 bls.n 8008040 + } + + pp_gps_air[dev_num]->device_id[0] = memory_slot[slot_num].slot_name[0]; + 8008072: 79ba ldrb r2, [r7, #6] + 8008074: 4b3e ldr r3, [pc, #248] ; (8008170 ) + 8008076: 6819 ldr r1, [r3, #0] + 8008078: 79fb ldrb r3, [r7, #7] + 800807a: 009b lsls r3, r3, #2 + 800807c: 440b add r3, r1 + 800807e: 6819 ldr r1, [r3, #0] + 8008080: 483d ldr r0, [pc, #244] ; (8008178 ) + 8008082: 4613 mov r3, r2 + 8008084: 011b lsls r3, r3, #4 + 8008086: 4413 add r3, r2 + 8008088: 4403 add r3, r0 + 800808a: 3301 adds r3, #1 + 800808c: 781b ldrb r3, [r3, #0] + 800808e: 700b strb r3, [r1, #0] + pp_gps_air[dev_num]->device_id[1] = memory_slot[slot_num].slot_name[1]; + 8008090: 79ba ldrb r2, [r7, #6] + 8008092: 4b37 ldr r3, [pc, #220] ; (8008170 ) + 8008094: 6819 ldr r1, [r3, #0] + 8008096: 79fb ldrb r3, [r7, #7] + 8008098: 009b lsls r3, r3, #2 + 800809a: 440b add r3, r1 + 800809c: 6819 ldr r1, [r3, #0] + 800809e: 4836 ldr r0, [pc, #216] ; (8008178 ) + 80080a0: 4613 mov r3, r2 + 80080a2: 011b lsls r3, r3, #4 + 80080a4: 4413 add r3, r2 + 80080a6: 4403 add r3, r0 + 80080a8: 3302 adds r3, #2 + 80080aa: 781b ldrb r3, [r3, #0] + 80080ac: 704b strb r3, [r1, #1] + + pp_gps_air[dev_num]->latitude.as_array[0] = point_buffer[MEMORY_POINT_LATITUDE_POS]; + 80080ae: 4b30 ldr r3, [pc, #192] ; (8008170 ) + 80080b0: 681a ldr r2, [r3, #0] + 80080b2: 79fb ldrb r3, [r7, #7] + 80080b4: 009b lsls r3, r3, #2 + 80080b6: 4413 add r3, r2 + 80080b8: 681b ldr r3, [r3, #0] + 80080ba: 4a2c ldr r2, [pc, #176] ; (800816c ) + 80080bc: 7b12 ldrb r2, [r2, #12] + 80080be: 711a strb r2, [r3, #4] + pp_gps_air[dev_num]->latitude.as_array[1] = point_buffer[MEMORY_POINT_LATITUDE_POS + 1]; + 80080c0: 4b2b ldr r3, [pc, #172] ; (8008170 ) + 80080c2: 681a ldr r2, [r3, #0] + 80080c4: 79fb ldrb r3, [r7, #7] + 80080c6: 009b lsls r3, r3, #2 + 80080c8: 4413 add r3, r2 + 80080ca: 681b ldr r3, [r3, #0] + 80080cc: 4a27 ldr r2, [pc, #156] ; (800816c ) + 80080ce: 7b52 ldrb r2, [r2, #13] + 80080d0: 715a strb r2, [r3, #5] + pp_gps_air[dev_num]->latitude.as_array[2] = point_buffer[MEMORY_POINT_LATITUDE_POS + 2]; + 80080d2: 4b27 ldr r3, [pc, #156] ; (8008170 ) + 80080d4: 681a ldr r2, [r3, #0] + 80080d6: 79fb ldrb r3, [r7, #7] + 80080d8: 009b lsls r3, r3, #2 + 80080da: 4413 add r3, r2 + 80080dc: 681b ldr r3, [r3, #0] + 80080de: 4a23 ldr r2, [pc, #140] ; (800816c ) + 80080e0: 7b92 ldrb r2, [r2, #14] + 80080e2: 719a strb r2, [r3, #6] + pp_gps_air[dev_num]->latitude.as_array[3] = point_buffer[MEMORY_POINT_LATITUDE_POS + 3]; + 80080e4: 4b22 ldr r3, [pc, #136] ; (8008170 ) + 80080e6: 681a ldr r2, [r3, #0] + 80080e8: 79fb ldrb r3, [r7, #7] + 80080ea: 009b lsls r3, r3, #2 + 80080ec: 4413 add r3, r2 + 80080ee: 681b ldr r3, [r3, #0] + 80080f0: 4a1e ldr r2, [pc, #120] ; (800816c ) + 80080f2: 7bd2 ldrb r2, [r2, #15] + 80080f4: 71da strb r2, [r3, #7] + + pp_gps_air[dev_num]->longitude.as_array[0] = point_buffer[MEMORY_POINT_LONGITUDE_POS]; + 80080f6: 4b1e ldr r3, [pc, #120] ; (8008170 ) + 80080f8: 681a ldr r2, [r3, #0] + 80080fa: 79fb ldrb r3, [r7, #7] + 80080fc: 009b lsls r3, r3, #2 + 80080fe: 4413 add r3, r2 + 8008100: 681b ldr r3, [r3, #0] + 8008102: 4a1a ldr r2, [pc, #104] ; (800816c ) + 8008104: 7c12 ldrb r2, [r2, #16] + 8008106: 721a strb r2, [r3, #8] + pp_gps_air[dev_num]->longitude.as_array[1] = point_buffer[MEMORY_POINT_LONGITUDE_POS + 1]; + 8008108: 4b19 ldr r3, [pc, #100] ; (8008170 ) + 800810a: 681a ldr r2, [r3, #0] + 800810c: 79fb ldrb r3, [r7, #7] + 800810e: 009b lsls r3, r3, #2 + 8008110: 4413 add r3, r2 + 8008112: 681b ldr r3, [r3, #0] + 8008114: 4a15 ldr r2, [pc, #84] ; (800816c ) + 8008116: 7c52 ldrb r2, [r2, #17] + 8008118: 725a strb r2, [r3, #9] + pp_gps_air[dev_num]->longitude.as_array[2] = point_buffer[MEMORY_POINT_LONGITUDE_POS + 2]; + 800811a: 4b15 ldr r3, [pc, #84] ; (8008170 ) + 800811c: 681a ldr r2, [r3, #0] + 800811e: 79fb ldrb r3, [r7, #7] + 8008120: 009b lsls r3, r3, #2 + 8008122: 4413 add r3, r2 + 8008124: 681b ldr r3, [r3, #0] + 8008126: 4a11 ldr r2, [pc, #68] ; (800816c ) + 8008128: 7c92 ldrb r2, [r2, #18] + 800812a: 729a strb r2, [r3, #10] + pp_gps_air[dev_num]->longitude.as_array[3] = point_buffer[MEMORY_POINT_LONGITUDE_POS + 3]; + 800812c: 4b10 ldr r3, [pc, #64] ; (8008170 ) + 800812e: 681a ldr r2, [r3, #0] + 8008130: 79fb ldrb r3, [r7, #7] + 8008132: 009b lsls r3, r3, #2 + 8008134: 4413 add r3, r2 + 8008136: 681b ldr r3, [r3, #0] + 8008138: 4a0c ldr r2, [pc, #48] ; (800816c ) + 800813a: 7cd2 ldrb r2, [r2, #19] + 800813c: 72da strb r2, [r3, #11] + + pp_gps_air[dev_num]->altitude.as_array[0] = point_buffer[MEMORY_POINT_ALTITUDE_POS]; + 800813e: 4b0c ldr r3, [pc, #48] ; (8008170 ) + 8008140: 681a ldr r2, [r3, #0] + 8008142: 79fb ldrb r3, [r7, #7] + 8008144: 009b lsls r3, r3, #2 + 8008146: 4413 add r3, r2 + 8008148: 681b ldr r3, [r3, #0] + 800814a: 4a08 ldr r2, [pc, #32] ; (800816c ) + 800814c: 7d12 ldrb r2, [r2, #20] + 800814e: 731a strb r2, [r3, #12] + pp_gps_air[dev_num]->altitude.as_array[1] = point_buffer[MEMORY_POINT_ALTITUDE_POS + 1]; + 8008150: 4b07 ldr r3, [pc, #28] ; (8008170 ) + 8008152: 681a ldr r2, [r3, #0] + 8008154: 79fb ldrb r3, [r7, #7] + 8008156: 009b lsls r3, r3, #2 + 8008158: 4413 add r3, r2 + 800815a: 681b ldr r3, [r3, #0] + 800815c: 4a03 ldr r2, [pc, #12] ; (800816c ) + 800815e: 7d52 ldrb r2, [r2, #21] + 8008160: 735a strb r2, [r3, #13] +} + 8008162: bf00 nop + 8008164: 3710 adds r7, #16 + 8008166: 46bd mov sp, r7 + 8008168: bdb0 pop {r4, r5, r7, pc} + 800816a: bf00 nop + 800816c: 20000840 .word 0x20000840 + 8008170: 20000804 .word 0x20000804 + 8008174: 2000083c .word 0x2000083c + 8008178: 20000878 .word 0x20000878 + +0800817c : + + + +void delete_memory_point(uint8_t slot_num) +{ + 800817c: b580 push {r7, lr} + 800817e: b082 sub sp, #8 + 8008180: af00 add r7, sp, #0 + 8008182: 4603 mov r3, r0 + 8008184: 71fb strb r3, [r7, #7] + clear_point_buffer(); + 8008186: f000 f80b bl 80081a0 + m24c64_write_page(&point_buffer[0], slot_num); + 800818a: 79fb ldrb r3, [r7, #7] + 800818c: 4619 mov r1, r3 + 800818e: 4803 ldr r0, [pc, #12] ; (800819c ) + 8008190: f7fb fbb2 bl 80038f8 +} + 8008194: bf00 nop + 8008196: 3708 adds r7, #8 + 8008198: 46bd mov sp, r7 + 800819a: bd80 pop {r7, pc} + 800819c: 20000840 .word 0x20000840 + +080081a0 : + + + +void clear_point_buffer(void) +{ + 80081a0: b480 push {r7} + 80081a2: b083 sub sp, #12 + 80081a4: af00 add r7, sp, #0 + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 80081a6: 2300 movs r3, #0 + 80081a8: 71fb strb r3, [r7, #7] + 80081aa: e006 b.n 80081ba + { + point_buffer[i] = M24C64_EMPTY_CELL_VALUE; + 80081ac: 79fb ldrb r3, [r7, #7] + 80081ae: 4a07 ldr r2, [pc, #28] ; (80081cc ) + 80081b0: 21ff movs r1, #255 ; 0xff + 80081b2: 54d1 strb r1, [r2, r3] + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 80081b4: 79fb ldrb r3, [r7, #7] + 80081b6: 3301 adds r3, #1 + 80081b8: 71fb strb r3, [r7, #7] + 80081ba: 79fb ldrb r3, [r7, #7] + 80081bc: 2b1f cmp r3, #31 + 80081be: d9f5 bls.n 80081ac + } +} + 80081c0: bf00 nop + 80081c2: 370c adds r7, #12 + 80081c4: 46bd mov sp, r7 + 80081c6: bc80 pop {r7} + 80081c8: 4770 bx lr + 80081ca: bf00 nop + 80081cc: 20000840 .word 0x20000840 + +080081d0 : + + + +//Convert timeout in seconds to timeout in "XXdXXhXXmXXs" +void convert_timeout(uint32_t timeout_val, char *buffer) +{ + 80081d0: b580 push {r7, lr} + 80081d2: b088 sub sp, #32 + 80081d4: af00 add r7, sp, #0 + 80081d6: 6078 str r0, [r7, #4] + 80081d8: 6039 str r1, [r7, #0] + uint32_t sec = 0; + 80081da: 2300 movs r3, #0 + 80081dc: 61fb str r3, [r7, #28] + uint32_t min = 0; + 80081de: 2300 movs r3, #0 + 80081e0: 61bb str r3, [r7, #24] + uint32_t hour = 0; + 80081e2: 2300 movs r3, #0 + 80081e4: 617b str r3, [r7, #20] + uint32_t day = 0; + 80081e6: 2300 movs r3, #0 + 80081e8: 613b str r3, [r7, #16] + char buf[3]; + + + if (timeout_val >= 60) + 80081ea: 687b ldr r3, [r7, #4] + 80081ec: 2b3b cmp r3, #59 ; 0x3b + 80081ee: d939 bls.n 8008264 + { + min = timeout_val / 60; + 80081f0: 687b ldr r3, [r7, #4] + 80081f2: 4a8b ldr r2, [pc, #556] ; (8008420 ) + 80081f4: fba2 2303 umull r2, r3, r2, r3 + 80081f8: 095b lsrs r3, r3, #5 + 80081fa: 61bb str r3, [r7, #24] + sec = timeout_val % 60; + 80081fc: 687a ldr r2, [r7, #4] + 80081fe: 4b88 ldr r3, [pc, #544] ; (8008420 ) + 8008200: fba3 1302 umull r1, r3, r3, r2 + 8008204: 0959 lsrs r1, r3, #5 + 8008206: 460b mov r3, r1 + 8008208: 011b lsls r3, r3, #4 + 800820a: 1a5b subs r3, r3, r1 + 800820c: 009b lsls r3, r3, #2 + 800820e: 1ad3 subs r3, r2, r3 + 8008210: 61fb str r3, [r7, #28] + + if (min >= 60) + 8008212: 69bb ldr r3, [r7, #24] + 8008214: 2b3b cmp r3, #59 ; 0x3b + 8008216: d927 bls.n 8008268 + { + hour = min / 60; + 8008218: 69bb ldr r3, [r7, #24] + 800821a: 4a81 ldr r2, [pc, #516] ; (8008420 ) + 800821c: fba2 2303 umull r2, r3, r2, r3 + 8008220: 095b lsrs r3, r3, #5 + 8008222: 617b str r3, [r7, #20] + min = min % 60; + 8008224: 69ba ldr r2, [r7, #24] + 8008226: 4b7e ldr r3, [pc, #504] ; (8008420 ) + 8008228: fba3 1302 umull r1, r3, r3, r2 + 800822c: 0959 lsrs r1, r3, #5 + 800822e: 460b mov r3, r1 + 8008230: 011b lsls r3, r3, #4 + 8008232: 1a5b subs r3, r3, r1 + 8008234: 009b lsls r3, r3, #2 + 8008236: 1ad3 subs r3, r2, r3 + 8008238: 61bb str r3, [r7, #24] + + if (hour >= 24) + 800823a: 697b ldr r3, [r7, #20] + 800823c: 2b17 cmp r3, #23 + 800823e: d913 bls.n 8008268 + { + day = hour / 24; + 8008240: 697b ldr r3, [r7, #20] + 8008242: 4a78 ldr r2, [pc, #480] ; (8008424 ) + 8008244: fba2 2303 umull r2, r3, r2, r3 + 8008248: 091b lsrs r3, r3, #4 + 800824a: 613b str r3, [r7, #16] + hour = hour % 24; + 800824c: 697a ldr r2, [r7, #20] + 800824e: 4b75 ldr r3, [pc, #468] ; (8008424 ) + 8008250: fba3 1302 umull r1, r3, r3, r2 + 8008254: 0919 lsrs r1, r3, #4 + 8008256: 460b mov r3, r1 + 8008258: 005b lsls r3, r3, #1 + 800825a: 440b add r3, r1 + 800825c: 00db lsls r3, r3, #3 + 800825e: 1ad3 subs r3, r2, r3 + 8008260: 617b str r3, [r7, #20] + 8008262: e001 b.n 8008268 + } + } + } + else + { + sec = timeout_val; + 8008264: 687b ldr r3, [r7, #4] + 8008266: 61fb str r3, [r7, #28] + } + + if (day) + 8008268: 693b ldr r3, [r7, #16] + 800826a: 2b00 cmp r3, #0 + 800826c: d044 beq.n 80082f8 + { + //XXdXXh + itoa32(day, &buf[0]); + 800826e: 693b ldr r3, [r7, #16] + 8008270: f107 020c add.w r2, r7, #12 + 8008274: 4611 mov r1, r2 + 8008276: 4618 mov r0, r3 + 8008278: f000 face bl 8008818 + if (day > 9) + 800827c: 693b ldr r3, [r7, #16] + 800827e: 2b09 cmp r3, #9 + 8008280: d90b bls.n 800829a + { + buffer[0] = buf[0]; + 8008282: 7b3a ldrb r2, [r7, #12] + 8008284: 683b ldr r3, [r7, #0] + 8008286: 701a strb r2, [r3, #0] + buffer[1] = buf[1]; + 8008288: 683b ldr r3, [r7, #0] + 800828a: 3301 adds r3, #1 + 800828c: 7b7a ldrb r2, [r7, #13] + 800828e: 701a strb r2, [r3, #0] + buffer[2] = 'd'; + 8008290: 683b ldr r3, [r7, #0] + 8008292: 3302 adds r3, #2 + 8008294: 2264 movs r2, #100 ; 0x64 + 8008296: 701a strb r2, [r3, #0] + 8008298: e00a b.n 80082b0 + } + else + { + buffer[0] = '0'; + 800829a: 683b ldr r3, [r7, #0] + 800829c: 2230 movs r2, #48 ; 0x30 + 800829e: 701a strb r2, [r3, #0] + buffer[1] = buf[0]; + 80082a0: 683b ldr r3, [r7, #0] + 80082a2: 3301 adds r3, #1 + 80082a4: 7b3a ldrb r2, [r7, #12] + 80082a6: 701a strb r2, [r3, #0] + buffer[2] = 'd'; + 80082a8: 683b ldr r3, [r7, #0] + 80082aa: 3302 adds r3, #2 + 80082ac: 2264 movs r2, #100 ; 0x64 + 80082ae: 701a strb r2, [r3, #0] + } + + itoa32(hour, &buf[0]); + 80082b0: 697b ldr r3, [r7, #20] + 80082b2: f107 020c add.w r2, r7, #12 + 80082b6: 4611 mov r1, r2 + 80082b8: 4618 mov r0, r3 + 80082ba: f000 faad bl 8008818 + if (hour > 9) + 80082be: 697b ldr r3, [r7, #20] + 80082c0: 2b09 cmp r3, #9 + 80082c2: d90c bls.n 80082de + { + buffer[3] = buf[0]; + 80082c4: 683b ldr r3, [r7, #0] + 80082c6: 3303 adds r3, #3 + 80082c8: 7b3a ldrb r2, [r7, #12] + 80082ca: 701a strb r2, [r3, #0] + buffer[4] = buf[1]; + 80082cc: 683b ldr r3, [r7, #0] + 80082ce: 3304 adds r3, #4 + 80082d0: 7b7a ldrb r2, [r7, #13] + 80082d2: 701a strb r2, [r3, #0] + buffer[5] = 'h'; + 80082d4: 683b ldr r3, [r7, #0] + 80082d6: 3305 adds r3, #5 + 80082d8: 2268 movs r2, #104 ; 0x68 + 80082da: 701a strb r2, [r3, #0] + 80082dc: e098 b.n 8008410 + } + else + { + buffer[3] = '0'; + 80082de: 683b ldr r3, [r7, #0] + 80082e0: 3303 adds r3, #3 + 80082e2: 2230 movs r2, #48 ; 0x30 + 80082e4: 701a strb r2, [r3, #0] + buffer[4] = buf[0]; + 80082e6: 683b ldr r3, [r7, #0] + 80082e8: 3304 adds r3, #4 + 80082ea: 7b3a ldrb r2, [r7, #12] + 80082ec: 701a strb r2, [r3, #0] + buffer[5] = 'h'; + 80082ee: 683b ldr r3, [r7, #0] + 80082f0: 3305 adds r3, #5 + 80082f2: 2268 movs r2, #104 ; 0x68 + 80082f4: 701a strb r2, [r3, #0] + 80082f6: e08b b.n 8008410 + } + } + else if (hour) + 80082f8: 697b ldr r3, [r7, #20] + 80082fa: 2b00 cmp r3, #0 + 80082fc: d044 beq.n 8008388 + { + //XXhXXm + itoa32(hour, &buf[0]); + 80082fe: 697b ldr r3, [r7, #20] + 8008300: f107 020c add.w r2, r7, #12 + 8008304: 4611 mov r1, r2 + 8008306: 4618 mov r0, r3 + 8008308: f000 fa86 bl 8008818 + if (hour > 9) + 800830c: 697b ldr r3, [r7, #20] + 800830e: 2b09 cmp r3, #9 + 8008310: d90b bls.n 800832a + { + buffer[0] = buf[0]; + 8008312: 7b3a ldrb r2, [r7, #12] + 8008314: 683b ldr r3, [r7, #0] + 8008316: 701a strb r2, [r3, #0] + buffer[1] = buf[1]; + 8008318: 683b ldr r3, [r7, #0] + 800831a: 3301 adds r3, #1 + 800831c: 7b7a ldrb r2, [r7, #13] + 800831e: 701a strb r2, [r3, #0] + buffer[2] = 'h'; + 8008320: 683b ldr r3, [r7, #0] + 8008322: 3302 adds r3, #2 + 8008324: 2268 movs r2, #104 ; 0x68 + 8008326: 701a strb r2, [r3, #0] + 8008328: e00a b.n 8008340 + } + else + { + buffer[0] = '0'; + 800832a: 683b ldr r3, [r7, #0] + 800832c: 2230 movs r2, #48 ; 0x30 + 800832e: 701a strb r2, [r3, #0] + buffer[1] = buf[0]; + 8008330: 683b ldr r3, [r7, #0] + 8008332: 3301 adds r3, #1 + 8008334: 7b3a ldrb r2, [r7, #12] + 8008336: 701a strb r2, [r3, #0] + buffer[2] = 'h'; + 8008338: 683b ldr r3, [r7, #0] + 800833a: 3302 adds r3, #2 + 800833c: 2268 movs r2, #104 ; 0x68 + 800833e: 701a strb r2, [r3, #0] + } + + itoa32(min, &buf[0]); + 8008340: 69bb ldr r3, [r7, #24] + 8008342: f107 020c add.w r2, r7, #12 + 8008346: 4611 mov r1, r2 + 8008348: 4618 mov r0, r3 + 800834a: f000 fa65 bl 8008818 + if (min > 9) + 800834e: 69bb ldr r3, [r7, #24] + 8008350: 2b09 cmp r3, #9 + 8008352: d90c bls.n 800836e + { + buffer[3] = buf[0]; + 8008354: 683b ldr r3, [r7, #0] + 8008356: 3303 adds r3, #3 + 8008358: 7b3a ldrb r2, [r7, #12] + 800835a: 701a strb r2, [r3, #0] + buffer[4] = buf[1]; + 800835c: 683b ldr r3, [r7, #0] + 800835e: 3304 adds r3, #4 + 8008360: 7b7a ldrb r2, [r7, #13] + 8008362: 701a strb r2, [r3, #0] + buffer[5] = 'm'; + 8008364: 683b ldr r3, [r7, #0] + 8008366: 3305 adds r3, #5 + 8008368: 226d movs r2, #109 ; 0x6d + 800836a: 701a strb r2, [r3, #0] + 800836c: e050 b.n 8008410 + } + else + { + buffer[3] = '0'; + 800836e: 683b ldr r3, [r7, #0] + 8008370: 3303 adds r3, #3 + 8008372: 2230 movs r2, #48 ; 0x30 + 8008374: 701a strb r2, [r3, #0] + buffer[4] = buf[0]; + 8008376: 683b ldr r3, [r7, #0] + 8008378: 3304 adds r3, #4 + 800837a: 7b3a ldrb r2, [r7, #12] + 800837c: 701a strb r2, [r3, #0] + buffer[5] = 'm'; + 800837e: 683b ldr r3, [r7, #0] + 8008380: 3305 adds r3, #5 + 8008382: 226d movs r2, #109 ; 0x6d + 8008384: 701a strb r2, [r3, #0] + 8008386: e043 b.n 8008410 + } + } + else + { + //XXmXXs + itoa32(min, &buf[0]); + 8008388: 69bb ldr r3, [r7, #24] + 800838a: f107 020c add.w r2, r7, #12 + 800838e: 4611 mov r1, r2 + 8008390: 4618 mov r0, r3 + 8008392: f000 fa41 bl 8008818 + if (min > 9) + 8008396: 69bb ldr r3, [r7, #24] + 8008398: 2b09 cmp r3, #9 + 800839a: d90b bls.n 80083b4 + { + buffer[0] = buf[0]; + 800839c: 7b3a ldrb r2, [r7, #12] + 800839e: 683b ldr r3, [r7, #0] + 80083a0: 701a strb r2, [r3, #0] + buffer[1] = buf[1]; + 80083a2: 683b ldr r3, [r7, #0] + 80083a4: 3301 adds r3, #1 + 80083a6: 7b7a ldrb r2, [r7, #13] + 80083a8: 701a strb r2, [r3, #0] + buffer[2] = 'm'; + 80083aa: 683b ldr r3, [r7, #0] + 80083ac: 3302 adds r3, #2 + 80083ae: 226d movs r2, #109 ; 0x6d + 80083b0: 701a strb r2, [r3, #0] + 80083b2: e00a b.n 80083ca + } + else + { + buffer[0] = '0'; + 80083b4: 683b ldr r3, [r7, #0] + 80083b6: 2230 movs r2, #48 ; 0x30 + 80083b8: 701a strb r2, [r3, #0] + buffer[1] = buf[0]; + 80083ba: 683b ldr r3, [r7, #0] + 80083bc: 3301 adds r3, #1 + 80083be: 7b3a ldrb r2, [r7, #12] + 80083c0: 701a strb r2, [r3, #0] + buffer[2] = 'm'; + 80083c2: 683b ldr r3, [r7, #0] + 80083c4: 3302 adds r3, #2 + 80083c6: 226d movs r2, #109 ; 0x6d + 80083c8: 701a strb r2, [r3, #0] + } + + itoa32(sec, &buf[0]); + 80083ca: 69fb ldr r3, [r7, #28] + 80083cc: f107 020c add.w r2, r7, #12 + 80083d0: 4611 mov r1, r2 + 80083d2: 4618 mov r0, r3 + 80083d4: f000 fa20 bl 8008818 + if (sec > 9) + 80083d8: 69fb ldr r3, [r7, #28] + 80083da: 2b09 cmp r3, #9 + 80083dc: d90c bls.n 80083f8 + { + buffer[3] = buf[0]; + 80083de: 683b ldr r3, [r7, #0] + 80083e0: 3303 adds r3, #3 + 80083e2: 7b3a ldrb r2, [r7, #12] + 80083e4: 701a strb r2, [r3, #0] + buffer[4] = buf[1]; + 80083e6: 683b ldr r3, [r7, #0] + 80083e8: 3304 adds r3, #4 + 80083ea: 7b7a ldrb r2, [r7, #13] + 80083ec: 701a strb r2, [r3, #0] + buffer[5] = 's'; + 80083ee: 683b ldr r3, [r7, #0] + 80083f0: 3305 adds r3, #5 + 80083f2: 2273 movs r2, #115 ; 0x73 + 80083f4: 701a strb r2, [r3, #0] + 80083f6: e00b b.n 8008410 + } + else + { + buffer[3] = '0'; + 80083f8: 683b ldr r3, [r7, #0] + 80083fa: 3303 adds r3, #3 + 80083fc: 2230 movs r2, #48 ; 0x30 + 80083fe: 701a strb r2, [r3, #0] + buffer[4] = buf[0]; + 8008400: 683b ldr r3, [r7, #0] + 8008402: 3304 adds r3, #4 + 8008404: 7b3a ldrb r2, [r7, #12] + 8008406: 701a strb r2, [r3, #0] + buffer[5] = 's'; + 8008408: 683b ldr r3, [r7, #0] + 800840a: 3305 adds r3, #5 + 800840c: 2273 movs r2, #115 ; 0x73 + 800840e: 701a strb r2, [r3, #0] + } + } + + buffer[6] = 0; //string end + 8008410: 683b ldr r3, [r7, #0] + 8008412: 3306 adds r3, #6 + 8008414: 2200 movs r2, #0 + 8008416: 701a strb r2, [r3, #0] +} + 8008418: bf00 nop + 800841a: 3720 adds r7, #32 + 800841c: 46bd mov sp, r7 + 800841e: bd80 pop {r7, pc} + 8008420: 88888889 .word 0x88888889 + 8008424: aaaaaaab .word 0xaaaaaaab + +08008428 : + + + +//Simple delay in cycles +void delay_cyc(uint32_t cycles) +{ + 8008428: b480 push {r7} + 800842a: b083 sub sp, #12 + 800842c: af00 add r7, sp, #0 + 800842e: 6078 str r0, [r7, #4] + while (cycles) + 8008430: e002 b.n 8008438 + { + cycles--; + 8008432: 687b ldr r3, [r7, #4] + 8008434: 3b01 subs r3, #1 + 8008436: 607b str r3, [r7, #4] + while (cycles) + 8008438: 687b ldr r3, [r7, #4] + 800843a: 2b00 cmp r3, #0 + 800843c: d1f9 bne.n 8008432 + } +} + 800843e: bf00 nop + 8008440: 370c adds r7, #12 + 8008442: 46bd mov sp, r7 + 8008444: bc80 pop {r7} + 8008446: 4770 bx lr + +08008448 : + + + +//Converts string to float +float atof32(char *input) +{ + 8008448: b5b0 push {r4, r5, r7, lr} + 800844a: b086 sub sp, #24 + 800844c: af00 add r7, sp, #0 + 800844e: 6078 str r0, [r7, #4] + uint8_t i = 0; + 8008450: 2300 movs r3, #0 + 8008452: 75fb strb r3, [r7, #23] + int32_t sign = 1; + 8008454: 2301 movs r3, #1 + 8008456: 613b str r3, [r7, #16] + float power = 1.0; + 8008458: f04f 537e mov.w r3, #1065353216 ; 0x3f800000 + 800845c: 60fb str r3, [r7, #12] + float result = 0.0; + 800845e: f04f 0300 mov.w r3, #0 + 8008462: 60bb str r3, [r7, #8] + + if(input[0] == 0) + 8008464: 687b ldr r3, [r7, #4] + 8008466: 781b ldrb r3, [r3, #0] + 8008468: 2b00 cmp r3, #0 + 800846a: d102 bne.n 8008472 + { + return 0.0; + 800846c: f04f 0300 mov.w r3, #0 + 8008470: e07a b.n 8008568 + } + + if(input[i] == '-') + 8008472: 7dfb ldrb r3, [r7, #23] + 8008474: 687a ldr r2, [r7, #4] + 8008476: 4413 add r3, r2 + 8008478: 781b ldrb r3, [r3, #0] + 800847a: 2b2d cmp r3, #45 ; 0x2d + 800847c: d12b bne.n 80084d6 + { + sign = -1; + 800847e: f04f 33ff mov.w r3, #4294967295 + 8008482: 613b str r3, [r7, #16] + i++; + 8008484: 7dfb ldrb r3, [r7, #23] + 8008486: 3301 adds r3, #1 + 8008488: 75fb strb r3, [r7, #23] + } + + while(input[i] != '.') + 800848a: e024 b.n 80084d6 + { + result = result * 10.0 + (input[i] - '0'); + 800848c: 68b8 ldr r0, [r7, #8] + 800848e: f7f7 ffd3 bl 8000438 <__aeabi_f2d> + 8008492: f04f 0200 mov.w r2, #0 + 8008496: 4b36 ldr r3, [pc, #216] ; (8008570 ) + 8008498: f7f8 f826 bl 80004e8 <__aeabi_dmul> + 800849c: 4603 mov r3, r0 + 800849e: 460c mov r4, r1 + 80084a0: 4625 mov r5, r4 + 80084a2: 461c mov r4, r3 + 80084a4: 7dfb ldrb r3, [r7, #23] + 80084a6: 687a ldr r2, [r7, #4] + 80084a8: 4413 add r3, r2 + 80084aa: 781b ldrb r3, [r3, #0] + 80084ac: 3b30 subs r3, #48 ; 0x30 + 80084ae: 4618 mov r0, r3 + 80084b0: f7f7 ffb0 bl 8000414 <__aeabi_i2d> + 80084b4: 4602 mov r2, r0 + 80084b6: 460b mov r3, r1 + 80084b8: 4620 mov r0, r4 + 80084ba: 4629 mov r1, r5 + 80084bc: f7f7 fe5e bl 800017c <__adddf3> + 80084c0: 4603 mov r3, r0 + 80084c2: 460c mov r4, r1 + 80084c4: 4618 mov r0, r3 + 80084c6: 4621 mov r1, r4 + 80084c8: f7f8 fb06 bl 8000ad8 <__aeabi_d2f> + 80084cc: 4603 mov r3, r0 + 80084ce: 60bb str r3, [r7, #8] + i++; + 80084d0: 7dfb ldrb r3, [r7, #23] + 80084d2: 3301 adds r3, #1 + 80084d4: 75fb strb r3, [r7, #23] + while(input[i] != '.') + 80084d6: 7dfb ldrb r3, [r7, #23] + 80084d8: 687a ldr r2, [r7, #4] + 80084da: 4413 add r3, r2 + 80084dc: 781b ldrb r3, [r3, #0] + 80084de: 2b2e cmp r3, #46 ; 0x2e + 80084e0: d1d4 bne.n 800848c + } + + i++; + 80084e2: 7dfb ldrb r3, [r7, #23] + 80084e4: 3301 adds r3, #1 + 80084e6: 75fb strb r3, [r7, #23] + + while(input[i] != 0) + 80084e8: e02a b.n 8008540 + { + result = result * 10.0 + (input[i] - '0'); + 80084ea: 68b8 ldr r0, [r7, #8] + 80084ec: f7f7 ffa4 bl 8000438 <__aeabi_f2d> + 80084f0: f04f 0200 mov.w r2, #0 + 80084f4: 4b1e ldr r3, [pc, #120] ; (8008570 ) + 80084f6: f7f7 fff7 bl 80004e8 <__aeabi_dmul> + 80084fa: 4603 mov r3, r0 + 80084fc: 460c mov r4, r1 + 80084fe: 4625 mov r5, r4 + 8008500: 461c mov r4, r3 + 8008502: 7dfb ldrb r3, [r7, #23] + 8008504: 687a ldr r2, [r7, #4] + 8008506: 4413 add r3, r2 + 8008508: 781b ldrb r3, [r3, #0] + 800850a: 3b30 subs r3, #48 ; 0x30 + 800850c: 4618 mov r0, r3 + 800850e: f7f7 ff81 bl 8000414 <__aeabi_i2d> + 8008512: 4602 mov r2, r0 + 8008514: 460b mov r3, r1 + 8008516: 4620 mov r0, r4 + 8008518: 4629 mov r1, r5 + 800851a: f7f7 fe2f bl 800017c <__adddf3> + 800851e: 4603 mov r3, r0 + 8008520: 460c mov r4, r1 + 8008522: 4618 mov r0, r3 + 8008524: 4621 mov r1, r4 + 8008526: f7f8 fad7 bl 8000ad8 <__aeabi_d2f> + 800852a: 4603 mov r3, r0 + 800852c: 60bb str r3, [r7, #8] + power *= 10.0; + 800852e: 4911 ldr r1, [pc, #68] ; (8008574 ) + 8008530: 68f8 ldr r0, [r7, #12] + 8008532: f7f8 fc2f bl 8000d94 <__aeabi_fmul> + 8008536: 4603 mov r3, r0 + 8008538: 60fb str r3, [r7, #12] + i++; + 800853a: 7dfb ldrb r3, [r7, #23] + 800853c: 3301 adds r3, #1 + 800853e: 75fb strb r3, [r7, #23] + while(input[i] != 0) + 8008540: 7dfb ldrb r3, [r7, #23] + 8008542: 687a ldr r2, [r7, #4] + 8008544: 4413 add r3, r2 + 8008546: 781b ldrb r3, [r3, #0] + 8008548: 2b00 cmp r3, #0 + 800854a: d1ce bne.n 80084ea + } + + return (sign * result / power); + 800854c: 6938 ldr r0, [r7, #16] + 800854e: f7f8 fbcd bl 8000cec <__aeabi_i2f> + 8008552: 4603 mov r3, r0 + 8008554: 68b9 ldr r1, [r7, #8] + 8008556: 4618 mov r0, r3 + 8008558: f7f8 fc1c bl 8000d94 <__aeabi_fmul> + 800855c: 4603 mov r3, r0 + 800855e: 68f9 ldr r1, [r7, #12] + 8008560: 4618 mov r0, r3 + 8008562: f7f8 fccb bl 8000efc <__aeabi_fdiv> + 8008566: 4603 mov r3, r0 +} + 8008568: 4618 mov r0, r3 + 800856a: 3718 adds r7, #24 + 800856c: 46bd mov sp, r7 + 800856e: bdb0 pop {r4, r5, r7, pc} + 8008570: 40240000 .word 0x40240000 + 8008574: 41200000 .word 0x41200000 + +08008578 : + + + +//Converts float to string +void ftoa32(float value, uint8_t precision, char *buffer) +{ + 8008578: b590 push {r4, r7, lr} + 800857a: b08d sub sp, #52 ; 0x34 + 800857c: af00 add r7, sp, #0 + 800857e: 60f8 str r0, [r7, #12] + 8008580: 460b mov r3, r1 + 8008582: 607a str r2, [r7, #4] + 8008584: 72fb strb r3, [r7, #11] + uint8_t i = 0; + 8008586: 2300 movs r3, #0 + 8008588: f887 302f strb.w r3, [r7, #47] ; 0x2f + uint32_t mod = 0; + 800858c: 2300 movs r3, #0 + 800858e: 61bb str r3, [r7, #24] + float pow = 1.0; + 8008590: f04f 537e mov.w r3, #1065353216 ; 0x3f800000 + 8008594: 62bb str r3, [r7, #40] ; 0x28 + char sgn = 0; + 8008596: 2300 movs r3, #0 + 8008598: f887 3027 strb.w r3, [r7, #39] ; 0x27 + float value_copy; + + if((value == 0.0) || (value == -0.0)) + 800859c: f04f 0100 mov.w r1, #0 + 80085a0: 68f8 ldr r0, [r7, #12] + 80085a2: f7f8 fd8b bl 80010bc <__aeabi_fcmpeq> + 80085a6: 4603 mov r3, r0 + 80085a8: 2b00 cmp r3, #0 + 80085aa: d107 bne.n 80085bc + 80085ac: f04f 0100 mov.w r1, #0 + 80085b0: 68f8 ldr r0, [r7, #12] + 80085b2: f7f8 fd83 bl 80010bc <__aeabi_fcmpeq> + 80085b6: 4603 mov r3, r0 + 80085b8: 2b00 cmp r3, #0 + 80085ba: d007 beq.n 80085cc + { + buffer[0] = '0'; + 80085bc: 687b ldr r3, [r7, #4] + 80085be: 2230 movs r2, #48 ; 0x30 + 80085c0: 701a strb r2, [r3, #0] + buffer[1] = 0; + 80085c2: 687b ldr r3, [r7, #4] + 80085c4: 3301 adds r3, #1 + 80085c6: 2200 movs r2, #0 + 80085c8: 701a strb r2, [r3, #0] + return; + 80085ca: e0d6 b.n 800877a + } + + if(value < 0) + 80085cc: f04f 0100 mov.w r1, #0 + 80085d0: 68f8 ldr r0, [r7, #12] + 80085d2: f7f8 fd7d bl 80010d0 <__aeabi_fcmplt> + 80085d6: 4603 mov r3, r0 + 80085d8: 2b00 cmp r3, #0 + 80085da: d00f beq.n 80085fc + { + sgn = '-'; + 80085dc: 232d movs r3, #45 ; 0x2d + 80085de: f887 3027 strb.w r3, [r7, #39] ; 0x27 + value *= -1.0; + 80085e2: 68f8 ldr r0, [r7, #12] + 80085e4: f7f7 ff28 bl 8000438 <__aeabi_f2d> + 80085e8: 4603 mov r3, r0 + 80085ea: 460c mov r4, r1 + 80085ec: 4618 mov r0, r3 + 80085ee: 4621 mov r1, r4 + 80085f0: f7f8 fa72 bl 8000ad8 <__aeabi_d2f> + 80085f4: 4603 mov r3, r0 + 80085f6: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 + 80085fa: 60fb str r3, [r7, #12] + } + + value_copy = value; + 80085fc: 68fb ldr r3, [r7, #12] + 80085fe: 617b str r3, [r7, #20] + + for(uint8_t p = 0; p < precision; p++) + 8008600: 2300 movs r3, #0 + 8008602: f887 3026 strb.w r3, [r7, #38] ; 0x26 + 8008606: e00a b.n 800861e + { + pow = pow * 10.0; + 8008608: 495d ldr r1, [pc, #372] ; (8008780 ) + 800860a: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800860c: f7f8 fbc2 bl 8000d94 <__aeabi_fmul> + 8008610: 4603 mov r3, r0 + 8008612: 62bb str r3, [r7, #40] ; 0x28 + for(uint8_t p = 0; p < precision; p++) + 8008614: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 8008618: 3301 adds r3, #1 + 800861a: f887 3026 strb.w r3, [r7, #38] ; 0x26 + 800861e: f897 2026 ldrb.w r2, [r7, #38] ; 0x26 + 8008622: 7afb ldrb r3, [r7, #11] + 8008624: 429a cmp r2, r3 + 8008626: d3ef bcc.n 8008608 + } + + value = value * pow; + 8008628: 6ab9 ldr r1, [r7, #40] ; 0x28 + 800862a: 68f8 ldr r0, [r7, #12] + 800862c: f7f8 fbb2 bl 8000d94 <__aeabi_fmul> + 8008630: 4603 mov r3, r0 + 8008632: 60fb str r3, [r7, #12] + uint32_t ipart = value; + 8008634: 68f8 ldr r0, [r7, #12] + 8008636: f7f8 fd99 bl 800116c <__aeabi_f2uiz> + 800863a: 4603 mov r3, r0 + 800863c: 623b str r3, [r7, #32] + + buffer[i++] = 0; + 800863e: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8008642: 1c5a adds r2, r3, #1 + 8008644: f887 202f strb.w r2, [r7, #47] ; 0x2f + 8008648: 461a mov r2, r3 + 800864a: 687b ldr r3, [r7, #4] + 800864c: 4413 add r3, r2 + 800864e: 2200 movs r2, #0 + 8008650: 701a strb r2, [r3, #0] + + do + { + mod = ipart % 10; + 8008652: 6a3a ldr r2, [r7, #32] + 8008654: 4b4b ldr r3, [pc, #300] ; (8008784 ) + 8008656: fba3 1302 umull r1, r3, r3, r2 + 800865a: 08d9 lsrs r1, r3, #3 + 800865c: 460b mov r3, r1 + 800865e: 009b lsls r3, r3, #2 + 8008660: 440b add r3, r1 + 8008662: 005b lsls r3, r3, #1 + 8008664: 1ad3 subs r3, r2, r3 + 8008666: 61bb str r3, [r7, #24] + ipart /= 10; + 8008668: 6a3b ldr r3, [r7, #32] + 800866a: 4a46 ldr r2, [pc, #280] ; (8008784 ) + 800866c: fba2 2303 umull r2, r3, r2, r3 + 8008670: 08db lsrs r3, r3, #3 + 8008672: 623b str r3, [r7, #32] + buffer[i++] = mod + '0'; + 8008674: 69bb ldr r3, [r7, #24] + 8008676: b2da uxtb r2, r3 + 8008678: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 800867c: 1c59 adds r1, r3, #1 + 800867e: f887 102f strb.w r1, [r7, #47] ; 0x2f + 8008682: 4619 mov r1, r3 + 8008684: 687b ldr r3, [r7, #4] + 8008686: 440b add r3, r1 + 8008688: 3230 adds r2, #48 ; 0x30 + 800868a: b2d2 uxtb r2, r2 + 800868c: 701a strb r2, [r3, #0] + } + while(ipart > 0); + 800868e: 6a3b ldr r3, [r7, #32] + 8008690: 2b00 cmp r3, #0 + 8008692: d1de bne.n 8008652 + + if (value_copy < 1.0) + 8008694: f04f 517e mov.w r1, #1065353216 ; 0x3f800000 + 8008698: 6978 ldr r0, [r7, #20] + 800869a: f7f8 fd19 bl 80010d0 <__aeabi_fcmplt> + 800869e: 4603 mov r3, r0 + 80086a0: 2b00 cmp r3, #0 + 80086a2: d014 beq.n 80086ce + { + for(uint8_t p = 0; p < precision; p++) + 80086a4: 2300 movs r3, #0 + 80086a6: 77fb strb r3, [r7, #31] + 80086a8: e00d b.n 80086c6 + { + buffer[i] = '0'; + 80086aa: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 80086ae: 687a ldr r2, [r7, #4] + 80086b0: 4413 add r3, r2 + 80086b2: 2230 movs r2, #48 ; 0x30 + 80086b4: 701a strb r2, [r3, #0] + i++; + 80086b6: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 80086ba: 3301 adds r3, #1 + 80086bc: f887 302f strb.w r3, [r7, #47] ; 0x2f + for(uint8_t p = 0; p < precision; p++) + 80086c0: 7ffb ldrb r3, [r7, #31] + 80086c2: 3301 adds r3, #1 + 80086c4: 77fb strb r3, [r7, #31] + 80086c6: 7ffa ldrb r2, [r7, #31] + 80086c8: 7afb ldrb r3, [r7, #11] + 80086ca: 429a cmp r2, r3 + 80086cc: d3ed bcc.n 80086aa + } + } + + if(sgn == '-') + 80086ce: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80086d2: 2b2d cmp r3, #45 ; 0x2d + 80086d4: d107 bne.n 80086e6 + { + buffer[i] = sgn; + 80086d6: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 80086da: 687a ldr r2, [r7, #4] + 80086dc: 4413 add r3, r2 + 80086de: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 80086e2: 701a strb r2, [r3, #0] + 80086e4: e004 b.n 80086f0 + } + else + { + i--; + 80086e6: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 80086ea: 3b01 subs r3, #1 + 80086ec: f887 302f strb.w r3, [r7, #47] ; 0x2f + } + + for(uint8_t n = i + 1; n > precision + 1; n--) + 80086f0: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 80086f4: 3301 adds r3, #1 + 80086f6: 77bb strb r3, [r7, #30] + 80086f8: e00b b.n 8008712 + { + buffer[n] = buffer[n - 1]; + 80086fa: 7fbb ldrb r3, [r7, #30] + 80086fc: 3b01 subs r3, #1 + 80086fe: 687a ldr r2, [r7, #4] + 8008700: 441a add r2, r3 + 8008702: 7fbb ldrb r3, [r7, #30] + 8008704: 6879 ldr r1, [r7, #4] + 8008706: 440b add r3, r1 + 8008708: 7812 ldrb r2, [r2, #0] + 800870a: 701a strb r2, [r3, #0] + for(uint8_t n = i + 1; n > precision + 1; n--) + 800870c: 7fbb ldrb r3, [r7, #30] + 800870e: 3b01 subs r3, #1 + 8008710: 77bb strb r3, [r7, #30] + 8008712: 7fba ldrb r2, [r7, #30] + 8008714: 7afb ldrb r3, [r7, #11] + 8008716: 3301 adds r3, #1 + 8008718: 429a cmp r2, r3 + 800871a: dcee bgt.n 80086fa + } + buffer[precision + 1] = '.'; + 800871c: 7afb ldrb r3, [r7, #11] + 800871e: 3301 adds r3, #1 + 8008720: 687a ldr r2, [r7, #4] + 8008722: 4413 add r3, r2 + 8008724: 222e movs r2, #46 ; 0x2e + 8008726: 701a strb r2, [r3, #0] + i++; + 8008728: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 800872c: 3301 adds r3, #1 + 800872e: f887 302f strb.w r3, [r7, #47] ; 0x2f + + char c; + for(uint8_t j = 0; j < i; j++, i--) + 8008732: 2300 movs r3, #0 + 8008734: 777b strb r3, [r7, #29] + 8008736: e01b b.n 8008770 + { + c = buffer[j]; + 8008738: 7f7b ldrb r3, [r7, #29] + 800873a: 687a ldr r2, [r7, #4] + 800873c: 4413 add r3, r2 + 800873e: 781b ldrb r3, [r3, #0] + 8008740: 74fb strb r3, [r7, #19] + buffer[j] = buffer[i]; + 8008742: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8008746: 687a ldr r2, [r7, #4] + 8008748: 441a add r2, r3 + 800874a: 7f7b ldrb r3, [r7, #29] + 800874c: 6879 ldr r1, [r7, #4] + 800874e: 440b add r3, r1 + 8008750: 7812 ldrb r2, [r2, #0] + 8008752: 701a strb r2, [r3, #0] + buffer[i] = c; + 8008754: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8008758: 687a ldr r2, [r7, #4] + 800875a: 4413 add r3, r2 + 800875c: 7cfa ldrb r2, [r7, #19] + 800875e: 701a strb r2, [r3, #0] + for(uint8_t j = 0; j < i; j++, i--) + 8008760: 7f7b ldrb r3, [r7, #29] + 8008762: 3301 adds r3, #1 + 8008764: 777b strb r3, [r7, #29] + 8008766: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 800876a: 3b01 subs r3, #1 + 800876c: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8008770: 7f7a ldrb r2, [r7, #29] + 8008772: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8008776: 429a cmp r2, r3 + 8008778: d3de bcc.n 8008738 + } +} + 800877a: 3734 adds r7, #52 ; 0x34 + 800877c: 46bd mov sp, r7 + 800877e: bd90 pop {r4, r7, pc} + 8008780: 41200000 .word 0x41200000 + 8008784: cccccccd .word 0xcccccccd + +08008788 : + + + +//Converts string to integer +int32_t atoi32(char *input) +{ + 8008788: b480 push {r7} + 800878a: b087 sub sp, #28 + 800878c: af00 add r7, sp, #0 + 800878e: 6078 str r0, [r7, #4] + uint8_t i = 0; + 8008790: 2300 movs r3, #0 + 8008792: 75fb strb r3, [r7, #23] + int32_t sign = 1; + 8008794: 2301 movs r3, #1 + 8008796: 613b str r3, [r7, #16] + int32_t result = 0; + 8008798: 2300 movs r3, #0 + 800879a: 60fb str r3, [r7, #12] + + if(input[0] == 0) + 800879c: 687b ldr r3, [r7, #4] + 800879e: 781b ldrb r3, [r3, #0] + 80087a0: 2b00 cmp r3, #0 + 80087a2: d101 bne.n 80087a8 + { + return 0; + 80087a4: 2300 movs r3, #0 + 80087a6: e031 b.n 800880c + } + + if((input[0] == '0') && (input[1] == 0)) + 80087a8: 687b ldr r3, [r7, #4] + 80087aa: 781b ldrb r3, [r3, #0] + 80087ac: 2b30 cmp r3, #48 ; 0x30 + 80087ae: d106 bne.n 80087be + 80087b0: 687b ldr r3, [r7, #4] + 80087b2: 3301 adds r3, #1 + 80087b4: 781b ldrb r3, [r3, #0] + 80087b6: 2b00 cmp r3, #0 + 80087b8: d101 bne.n 80087be + { + return 0; + 80087ba: 2300 movs r3, #0 + 80087bc: e026 b.n 800880c + } + + if(input[i] == '-') + 80087be: 7dfb ldrb r3, [r7, #23] + 80087c0: 687a ldr r2, [r7, #4] + 80087c2: 4413 add r3, r2 + 80087c4: 781b ldrb r3, [r3, #0] + 80087c6: 2b2d cmp r3, #45 ; 0x2d + 80087c8: d116 bne.n 80087f8 + { + sign = -1; + 80087ca: f04f 33ff mov.w r3, #4294967295 + 80087ce: 613b str r3, [r7, #16] + i++; + 80087d0: 7dfb ldrb r3, [r7, #23] + 80087d2: 3301 adds r3, #1 + 80087d4: 75fb strb r3, [r7, #23] + } + + while(input[i] != 0) + 80087d6: e00f b.n 80087f8 + { + result = result * 10 + (input[i] - '0'); + 80087d8: 68fa ldr r2, [r7, #12] + 80087da: 4613 mov r3, r2 + 80087dc: 009b lsls r3, r3, #2 + 80087de: 4413 add r3, r2 + 80087e0: 005b lsls r3, r3, #1 + 80087e2: 4619 mov r1, r3 + 80087e4: 7dfb ldrb r3, [r7, #23] + 80087e6: 687a ldr r2, [r7, #4] + 80087e8: 4413 add r3, r2 + 80087ea: 781b ldrb r3, [r3, #0] + 80087ec: 3b30 subs r3, #48 ; 0x30 + 80087ee: 440b add r3, r1 + 80087f0: 60fb str r3, [r7, #12] + i++; + 80087f2: 7dfb ldrb r3, [r7, #23] + 80087f4: 3301 adds r3, #1 + 80087f6: 75fb strb r3, [r7, #23] + while(input[i] != 0) + 80087f8: 7dfb ldrb r3, [r7, #23] + 80087fa: 687a ldr r2, [r7, #4] + 80087fc: 4413 add r3, r2 + 80087fe: 781b ldrb r3, [r3, #0] + 8008800: 2b00 cmp r3, #0 + 8008802: d1e9 bne.n 80087d8 + } + + return result * sign; + 8008804: 68fb ldr r3, [r7, #12] + 8008806: 693a ldr r2, [r7, #16] + 8008808: fb02 f303 mul.w r3, r2, r3 +} + 800880c: 4618 mov r0, r3 + 800880e: 371c adds r7, #28 + 8008810: 46bd mov sp, r7 + 8008812: bc80 pop {r7} + 8008814: 4770 bx lr + ... + +08008818 : + + + +//Converts integer to string +void itoa32(int32_t value, char *buffer) +{ + 8008818: b480 push {r7} + 800881a: b085 sub sp, #20 + 800881c: af00 add r7, sp, #0 + 800881e: 6078 str r0, [r7, #4] + 8008820: 6039 str r1, [r7, #0] + uint8_t i = 0; + 8008822: 2300 movs r3, #0 + 8008824: 73fb strb r3, [r7, #15] + uint8_t mod = 0; + 8008826: 2300 movs r3, #0 + 8008828: 733b strb r3, [r7, #12] + char sgn = 0; + 800882a: 2300 movs r3, #0 + 800882c: 73bb strb r3, [r7, #14] + + if(value == 0) + 800882e: 687b ldr r3, [r7, #4] + 8008830: 2b00 cmp r3, #0 + 8008832: d107 bne.n 8008844 + { + buffer[0] = '0'; + 8008834: 683b ldr r3, [r7, #0] + 8008836: 2230 movs r2, #48 ; 0x30 + 8008838: 701a strb r2, [r3, #0] + buffer[1] = 0; + 800883a: 683b ldr r3, [r7, #0] + 800883c: 3301 adds r3, #1 + 800883e: 2200 movs r2, #0 + 8008840: 701a strb r2, [r3, #0] + return; + 8008842: e05e b.n 8008902 + } + + if(value < 0) + 8008844: 687b ldr r3, [r7, #4] + 8008846: 2b00 cmp r3, #0 + 8008848: da04 bge.n 8008854 + { + sgn = '-'; + 800884a: 232d movs r3, #45 ; 0x2d + 800884c: 73bb strb r3, [r7, #14] + value *= -1; + 800884e: 687b ldr r3, [r7, #4] + 8008850: 425b negs r3, r3 + 8008852: 607b str r3, [r7, #4] + } + + buffer[i++] = 0; + 8008854: 7bfb ldrb r3, [r7, #15] + 8008856: 1c5a adds r2, r3, #1 + 8008858: 73fa strb r2, [r7, #15] + 800885a: 461a mov r2, r3 + 800885c: 683b ldr r3, [r7, #0] + 800885e: 4413 add r3, r2 + 8008860: 2200 movs r2, #0 + 8008862: 701a strb r2, [r3, #0] + + while(value > 0) + 8008864: e01f b.n 80088a6 + { + mod = value % 10; + 8008866: 687a ldr r2, [r7, #4] + 8008868: 4b28 ldr r3, [pc, #160] ; (800890c ) + 800886a: fb83 1302 smull r1, r3, r3, r2 + 800886e: 1099 asrs r1, r3, #2 + 8008870: 17d3 asrs r3, r2, #31 + 8008872: 1ac9 subs r1, r1, r3 + 8008874: 460b mov r3, r1 + 8008876: 009b lsls r3, r3, #2 + 8008878: 440b add r3, r1 + 800887a: 005b lsls r3, r3, #1 + 800887c: 1ad1 subs r1, r2, r3 + 800887e: 460b mov r3, r1 + 8008880: 733b strb r3, [r7, #12] + value /= 10; + 8008882: 687b ldr r3, [r7, #4] + 8008884: 4a21 ldr r2, [pc, #132] ; (800890c ) + 8008886: fb82 1203 smull r1, r2, r2, r3 + 800888a: 1092 asrs r2, r2, #2 + 800888c: 17db asrs r3, r3, #31 + 800888e: 1ad3 subs r3, r2, r3 + 8008890: 607b str r3, [r7, #4] + buffer[i++] = mod + '0'; + 8008892: 7bfb ldrb r3, [r7, #15] + 8008894: 1c5a adds r2, r3, #1 + 8008896: 73fa strb r2, [r7, #15] + 8008898: 461a mov r2, r3 + 800889a: 683b ldr r3, [r7, #0] + 800889c: 4413 add r3, r2 + 800889e: 7b3a ldrb r2, [r7, #12] + 80088a0: 3230 adds r2, #48 ; 0x30 + 80088a2: b2d2 uxtb r2, r2 + 80088a4: 701a strb r2, [r3, #0] + while(value > 0) + 80088a6: 687b ldr r3, [r7, #4] + 80088a8: 2b00 cmp r3, #0 + 80088aa: dcdc bgt.n 8008866 + } + + if(sgn == '-') + 80088ac: 7bbb ldrb r3, [r7, #14] + 80088ae: 2b2d cmp r3, #45 ; 0x2d + 80088b0: d105 bne.n 80088be + { + buffer[i] = sgn; + 80088b2: 7bfb ldrb r3, [r7, #15] + 80088b4: 683a ldr r2, [r7, #0] + 80088b6: 4413 add r3, r2 + 80088b8: 7bba ldrb r2, [r7, #14] + 80088ba: 701a strb r2, [r3, #0] + 80088bc: e002 b.n 80088c4 + } + else + { + i--; + 80088be: 7bfb ldrb r3, [r7, #15] + 80088c0: 3b01 subs r3, #1 + 80088c2: 73fb strb r3, [r7, #15] + } + + char c; + for(uint8_t j = 0; j < i; j++, i--) + 80088c4: 2300 movs r3, #0 + 80088c6: 737b strb r3, [r7, #13] + 80088c8: e017 b.n 80088fa + { + c = buffer[j]; + 80088ca: 7b7b ldrb r3, [r7, #13] + 80088cc: 683a ldr r2, [r7, #0] + 80088ce: 4413 add r3, r2 + 80088d0: 781b ldrb r3, [r3, #0] + 80088d2: 72fb strb r3, [r7, #11] + buffer[j] = buffer[i]; + 80088d4: 7bfb ldrb r3, [r7, #15] + 80088d6: 683a ldr r2, [r7, #0] + 80088d8: 441a add r2, r3 + 80088da: 7b7b ldrb r3, [r7, #13] + 80088dc: 6839 ldr r1, [r7, #0] + 80088de: 440b add r3, r1 + 80088e0: 7812 ldrb r2, [r2, #0] + 80088e2: 701a strb r2, [r3, #0] + buffer[i] = c; + 80088e4: 7bfb ldrb r3, [r7, #15] + 80088e6: 683a ldr r2, [r7, #0] + 80088e8: 4413 add r3, r2 + 80088ea: 7afa ldrb r2, [r7, #11] + 80088ec: 701a strb r2, [r3, #0] + for(uint8_t j = 0; j < i; j++, i--) + 80088ee: 7b7b ldrb r3, [r7, #13] + 80088f0: 3301 adds r3, #1 + 80088f2: 737b strb r3, [r7, #13] + 80088f4: 7bfb ldrb r3, [r7, #15] + 80088f6: 3b01 subs r3, #1 + 80088f8: 73fb strb r3, [r7, #15] + 80088fa: 7b7a ldrb r2, [r7, #13] + 80088fc: 7bfb ldrb r3, [r7, #15] + 80088fe: 429a cmp r2, r3 + 8008900: d3e3 bcc.n 80088ca + } +} + 8008902: 3714 adds r7, #20 + 8008904: 46bd mov sp, r7 + 8008906: bc80 pop {r7} + 8008908: 4770 bx lr + 800890a: bf00 nop + 800890c: 66666667 .word 0x66666667 + +08008910 : +uint8_t tx_power_values[] = TX_POWER_VALUES_ARRAY; + + + +uint8_t *get_send_interval_values(void) +{ + 8008910: b480 push {r7} + 8008912: af00 add r7, sp, #0 + return &send_interval_values[0]; + 8008914: 4b02 ldr r3, [pc, #8] ; (8008920 ) +} + 8008916: 4618 mov r0, r3 + 8008918: 46bd mov sp, r7 + 800891a: bc80 pop {r7} + 800891c: 4770 bx lr + 800891e: bf00 nop + 8008920: 20000050 .word 0x20000050 + +08008924 : + + + +uint8_t *get_tx_power_values(void) +{ + 8008924: b480 push {r7} + 8008926: af00 add r7, sp, #0 + return &tx_power_values[0]; + 8008928: 4b02 ldr r3, [pc, #8] ; (8008934 ) +} + 800892a: 4618 mov r0, r3 + 800892c: 46bd mov sp, r7 + 800892e: bc80 pop {r7} + 8008930: 4770 bx lr + 8008932: bf00 nop + 8008934: 20000058 .word 0x20000058 + +08008938 : + + + +struct settings_struct *get_settings(void) +{ + 8008938: b480 push {r7} + 800893a: af00 add r7, sp, #0 + return &settings; + 800893c: 4b02 ldr r3, [pc, #8] ; (8008948 ) +} + 800893e: 4618 mov r0, r3 + 8008940: 46bd mov sp, r7 + 8008942: bc80 pop {r7} + 8008944: 4770 bx lr + 8008946: bf00 nop + 8008948: 200008e0 .word 0x200008e0 + +0800894c : + + + +void settings_load(void) +{ + 800894c: b580 push {r7, lr} + 800894e: b082 sub sp, #8 + 8008950: af00 add r7, sp, #0 + uint16_t init_flag_addr = EEPROM_SETTINGS_PAGE_ADDRESS * M24C64_PAGE_SIZE + SETTINGS_INIT_FLAG_POS; + 8008952: 2300 movs r3, #0 + 8008954: 80fb strh r3, [r7, #6] + + if (m24c64_read_byte(init_flag_addr) != SETTINGS_INIT_FLAG_DEFAULT) //if first power-up or EEPROM had been erased + 8008956: 88fb ldrh r3, [r7, #6] + 8008958: 4618 mov r0, r3 + 800895a: f7fa fe6f bl 800363c + 800895e: 4603 mov r3, r0 + 8008960: 2baa cmp r3, #170 ; 0xaa + 8008962: d001 beq.n 8008968 + { + settings_save_default(); + 8008964: f000 f834 bl 80089d0 + } + + //read from EEPROM + m24c64_read_page(&settings_array[0], EEPROM_SETTINGS_PAGE_ADDRESS); + 8008968: 2100 movs r1, #0 + 800896a: 4817 ldr r0, [pc, #92] ; (80089c8 ) + 800896c: f7fa ff00 bl 8003770 + + //load settings to struct + settings.device_number = settings_array[SETTINGS_DEVICE_NUMBER_POS]; + 8008970: 4b15 ldr r3, [pc, #84] ; (80089c8 ) + 8008972: 785a ldrb r2, [r3, #1] + 8008974: 4b15 ldr r3, [pc, #84] ; (80089cc ) + 8008976: 701a strb r2, [r3, #0] + settings.device_id[0] = settings_array[SETTINGS_DEVICE_ID_POS]; + 8008978: 4b13 ldr r3, [pc, #76] ; (80089c8 ) + 800897a: 789a ldrb r2, [r3, #2] + 800897c: 4b13 ldr r3, [pc, #76] ; (80089cc ) + 800897e: 705a strb r2, [r3, #1] + settings.device_id[1] = settings_array[SETTINGS_DEVICE_ID_POS + 1]; + 8008980: 4b11 ldr r3, [pc, #68] ; (80089c8 ) + 8008982: 78da ldrb r2, [r3, #3] + 8008984: 4b11 ldr r3, [pc, #68] ; (80089cc ) + 8008986: 709a strb r2, [r3, #2] + settings.freq_channel = settings_array[SETTINGS_FREQ_CHANNEL_POS]; + 8008988: 4b0f ldr r3, [pc, #60] ; (80089c8 ) + 800898a: 791a ldrb r2, [r3, #4] + 800898c: 4b0f ldr r3, [pc, #60] ; (80089cc ) + 800898e: 70da strb r2, [r3, #3] + settings.tx_power_opt = settings_array[SETTINGS_TX_POWER_POS]; + 8008990: 4b0d ldr r3, [pc, #52] ; (80089c8 ) + 8008992: 795a ldrb r2, [r3, #5] + 8008994: 4b0d ldr r3, [pc, #52] ; (80089cc ) + 8008996: 711a strb r2, [r3, #4] + settings.send_interval_opt = settings_array[SETTINGS_SEND_INTERVAL_POS]; + 8008998: 4b0b ldr r3, [pc, #44] ; (80089c8 ) + 800899a: 799a ldrb r2, [r3, #6] + 800899c: 4b0b ldr r3, [pc, #44] ; (80089cc ) + 800899e: 715a strb r2, [r3, #5] + settings.timeout_threshold.as_array[0] = settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS]; + 80089a0: 4b09 ldr r3, [pc, #36] ; (80089c8 ) + 80089a2: 79da ldrb r2, [r3, #7] + 80089a4: 4b09 ldr r3, [pc, #36] ; (80089cc ) + 80089a6: 719a strb r2, [r3, #6] + settings.timeout_threshold.as_array[1] = settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS + 1]; + 80089a8: 4b07 ldr r3, [pc, #28] ; (80089c8 ) + 80089aa: 7a1a ldrb r2, [r3, #8] + 80089ac: 4b07 ldr r3, [pc, #28] ; (80089cc ) + 80089ae: 71da strb r2, [r3, #7] + settings.fence_threshold.as_array[0] = settings_array[SETTINGS_FENCE_THRESHOLD_POS]; + 80089b0: 4b05 ldr r3, [pc, #20] ; (80089c8 ) + 80089b2: 7a5a ldrb r2, [r3, #9] + 80089b4: 4b05 ldr r3, [pc, #20] ; (80089cc ) + 80089b6: 721a strb r2, [r3, #8] + settings.fence_threshold.as_array[1] = settings_array[SETTINGS_FENCE_THRESHOLD_POS + 1]; + 80089b8: 4b03 ldr r3, [pc, #12] ; (80089c8 ) + 80089ba: 7a9a ldrb r2, [r3, #10] + 80089bc: 4b03 ldr r3, [pc, #12] ; (80089cc ) + 80089be: 725a strb r2, [r3, #9] +} + 80089c0: bf00 nop + 80089c2: 3708 adds r7, #8 + 80089c4: 46bd mov sp, r7 + 80089c6: bd80 pop {r7, pc} + 80089c8: 200008ec .word 0x200008ec + 80089cc: 200008e0 .word 0x200008e0 + +080089d0 : + + + +void settings_save_default(void) +{ + 80089d0: b580 push {r7, lr} + 80089d2: b082 sub sp, #8 + 80089d4: af00 add r7, sp, #0 + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 80089d6: 2300 movs r3, #0 + 80089d8: 71fb strb r3, [r7, #7] + 80089da: e006 b.n 80089ea + { + settings_array[i] = M24C64_EMPTY_CELL_VALUE; //clear array + 80089dc: 79fb ldrb r3, [r7, #7] + 80089de: 4a19 ldr r2, [pc, #100] ; (8008a44 ) + 80089e0: 21ff movs r1, #255 ; 0xff + 80089e2: 54d1 strb r1, [r2, r3] + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 80089e4: 79fb ldrb r3, [r7, #7] + 80089e6: 3301 adds r3, #1 + 80089e8: 71fb strb r3, [r7, #7] + 80089ea: 79fb ldrb r3, [r7, #7] + 80089ec: 2b1f cmp r3, #31 + 80089ee: d9f5 bls.n 80089dc + } + + //assign default values + settings_array[SETTINGS_INIT_FLAG_POS] = SETTINGS_INIT_FLAG_DEFAULT; + 80089f0: 4b14 ldr r3, [pc, #80] ; (8008a44 ) + 80089f2: 22aa movs r2, #170 ; 0xaa + 80089f4: 701a strb r2, [r3, #0] + settings_array[SETTINGS_DEVICE_NUMBER_POS] = SETTINGS_DEVICE_NUMBER_DEFAULT; + 80089f6: 4b13 ldr r3, [pc, #76] ; (8008a44 ) + 80089f8: 2201 movs r2, #1 + 80089fa: 705a strb r2, [r3, #1] + settings_array[SETTINGS_DEVICE_ID_POS] = SETTINGS_DEVICE_ID_0_DEFAULT; + 80089fc: 4b11 ldr r3, [pc, #68] ; (8008a44 ) + 80089fe: 2249 movs r2, #73 ; 0x49 + 8008a00: 709a strb r2, [r3, #2] + settings_array[SETTINGS_DEVICE_ID_POS + 1] = SETTINGS_DEVICE_ID_1_DEFAULT; + 8008a02: 4b10 ldr r3, [pc, #64] ; (8008a44 ) + 8008a04: 2244 movs r2, #68 ; 0x44 + 8008a06: 70da strb r2, [r3, #3] + settings_array[SETTINGS_FREQ_CHANNEL_POS] = SETTINGS_FREQ_CHANNEL_DEFAULT; + 8008a08: 4b0e ldr r3, [pc, #56] ; (8008a44 ) + 8008a0a: 2201 movs r2, #1 + 8008a0c: 711a strb r2, [r3, #4] + settings_array[SETTINGS_TX_POWER_POS] = SETTINGS_TX_POWER_DEFAULT; + 8008a0e: 4b0d ldr r3, [pc, #52] ; (8008a44 ) + 8008a10: 2200 movs r2, #0 + 8008a12: 715a strb r2, [r3, #5] + settings_array[SETTINGS_SEND_INTERVAL_POS] = SETTINGS_SEND_INTERVAL_DEFAULT; + 8008a14: 4b0b ldr r3, [pc, #44] ; (8008a44 ) + 8008a16: 2200 movs r2, #0 + 8008a18: 719a strb r2, [r3, #6] + settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS] = (uint8_t)((uint8_t)0xFF & (uint16_t)SETTINGS_TIMEOUT_THRESHOLD_DEFAULT); //note: little-endian assumed + 8008a1a: 4b0a ldr r3, [pc, #40] ; (8008a44 ) + 8008a1c: 223c movs r2, #60 ; 0x3c + 8008a1e: 71da strb r2, [r3, #7] + settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS + 1]= (uint8_t)((uint8_t)0xFF & ((uint16_t)SETTINGS_TIMEOUT_THRESHOLD_DEFAULT >> 8)); + 8008a20: 4b08 ldr r3, [pc, #32] ; (8008a44 ) + 8008a22: 2200 movs r2, #0 + 8008a24: 721a strb r2, [r3, #8] + settings_array[SETTINGS_FENCE_THRESHOLD_POS] = (uint8_t)((uint8_t)0xFF & (uint16_t)SETTINGS_FENCE_THRESHOLD_DEFAULT); //note: little-endian assumed + 8008a26: 4b07 ldr r3, [pc, #28] ; (8008a44 ) + 8008a28: 2264 movs r2, #100 ; 0x64 + 8008a2a: 725a strb r2, [r3, #9] + settings_array[SETTINGS_FENCE_THRESHOLD_POS + 1] = (uint8_t)((uint8_t)0xFF & ((uint16_t)SETTINGS_FENCE_THRESHOLD_DEFAULT >> 8)); + 8008a2c: 4b05 ldr r3, [pc, #20] ; (8008a44 ) + 8008a2e: 2200 movs r2, #0 + 8008a30: 729a strb r2, [r3, #10] + + //write to EEPROM + m24c64_write_page(&settings_array[0], EEPROM_SETTINGS_PAGE_ADDRESS); + 8008a32: 2100 movs r1, #0 + 8008a34: 4803 ldr r0, [pc, #12] ; (8008a44 ) + 8008a36: f7fa ff5f bl 80038f8 +} + 8008a3a: bf00 nop + 8008a3c: 3708 adds r7, #8 + 8008a3e: 46bd mov sp, r7 + 8008a40: bd80 pop {r7, pc} + 8008a42: bf00 nop + 8008a44: 200008ec .word 0x200008ec + +08008a48 : + + + +void settings_save(struct settings_struct *p_settings) +{ + 8008a48: b580 push {r7, lr} + 8008a4a: b084 sub sp, #16 + 8008a4c: af00 add r7, sp, #0 + 8008a4e: 6078 str r0, [r7, #4] + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 8008a50: 2300 movs r3, #0 + 8008a52: 73fb strb r3, [r7, #15] + 8008a54: e006 b.n 8008a64 + { + settings_array[i] = M24C64_EMPTY_CELL_VALUE; //clear array + 8008a56: 7bfb ldrb r3, [r7, #15] + 8008a58: 4a1d ldr r2, [pc, #116] ; (8008ad0 ) + 8008a5a: 21ff movs r1, #255 ; 0xff + 8008a5c: 54d1 strb r1, [r2, r3] + for (uint8_t i = 0; i < M24C64_PAGE_SIZE; i++) + 8008a5e: 7bfb ldrb r3, [r7, #15] + 8008a60: 3301 adds r3, #1 + 8008a62: 73fb strb r3, [r7, #15] + 8008a64: 7bfb ldrb r3, [r7, #15] + 8008a66: 2b1f cmp r3, #31 + 8008a68: d9f5 bls.n 8008a56 + } + + //assign values + settings_array[SETTINGS_INIT_FLAG_POS] = SETTINGS_INIT_FLAG_DEFAULT; + 8008a6a: 4b19 ldr r3, [pc, #100] ; (8008ad0 ) + 8008a6c: 22aa movs r2, #170 ; 0xaa + 8008a6e: 701a strb r2, [r3, #0] + settings_array[SETTINGS_DEVICE_NUMBER_POS] = p_settings->device_number; + 8008a70: 687b ldr r3, [r7, #4] + 8008a72: 781a ldrb r2, [r3, #0] + 8008a74: 4b16 ldr r3, [pc, #88] ; (8008ad0 ) + 8008a76: 705a strb r2, [r3, #1] + settings_array[SETTINGS_DEVICE_ID_POS] = p_settings->device_id[0]; + 8008a78: 687b ldr r3, [r7, #4] + 8008a7a: 785a ldrb r2, [r3, #1] + 8008a7c: 4b14 ldr r3, [pc, #80] ; (8008ad0 ) + 8008a7e: 709a strb r2, [r3, #2] + settings_array[SETTINGS_DEVICE_ID_POS + 1] = p_settings->device_id[1]; + 8008a80: 687b ldr r3, [r7, #4] + 8008a82: 789a ldrb r2, [r3, #2] + 8008a84: 4b12 ldr r3, [pc, #72] ; (8008ad0 ) + 8008a86: 70da strb r2, [r3, #3] + settings_array[SETTINGS_FREQ_CHANNEL_POS] = p_settings->freq_channel; + 8008a88: 687b ldr r3, [r7, #4] + 8008a8a: 78da ldrb r2, [r3, #3] + 8008a8c: 4b10 ldr r3, [pc, #64] ; (8008ad0 ) + 8008a8e: 711a strb r2, [r3, #4] + settings_array[SETTINGS_TX_POWER_POS] = p_settings->tx_power_opt; + 8008a90: 687b ldr r3, [r7, #4] + 8008a92: 791a ldrb r2, [r3, #4] + 8008a94: 4b0e ldr r3, [pc, #56] ; (8008ad0 ) + 8008a96: 715a strb r2, [r3, #5] + settings_array[SETTINGS_SEND_INTERVAL_POS] = p_settings->send_interval_opt; + 8008a98: 687b ldr r3, [r7, #4] + 8008a9a: 795a ldrb r2, [r3, #5] + 8008a9c: 4b0c ldr r3, [pc, #48] ; (8008ad0 ) + 8008a9e: 719a strb r2, [r3, #6] + settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS] = p_settings->timeout_threshold.as_array[0]; + 8008aa0: 687b ldr r3, [r7, #4] + 8008aa2: 799a ldrb r2, [r3, #6] + 8008aa4: 4b0a ldr r3, [pc, #40] ; (8008ad0 ) + 8008aa6: 71da strb r2, [r3, #7] + settings_array[SETTINGS_TIMEOUT_THRESHOLD_POS + 1]= p_settings->timeout_threshold.as_array[1]; + 8008aa8: 687b ldr r3, [r7, #4] + 8008aaa: 79da ldrb r2, [r3, #7] + 8008aac: 4b08 ldr r3, [pc, #32] ; (8008ad0 ) + 8008aae: 721a strb r2, [r3, #8] + settings_array[SETTINGS_FENCE_THRESHOLD_POS] = p_settings->fence_threshold.as_array[0]; + 8008ab0: 687b ldr r3, [r7, #4] + 8008ab2: 7a1a ldrb r2, [r3, #8] + 8008ab4: 4b06 ldr r3, [pc, #24] ; (8008ad0 ) + 8008ab6: 725a strb r2, [r3, #9] + settings_array[SETTINGS_FENCE_THRESHOLD_POS + 1] = p_settings->fence_threshold.as_array[1]; + 8008ab8: 687b ldr r3, [r7, #4] + 8008aba: 7a5a ldrb r2, [r3, #9] + 8008abc: 4b04 ldr r3, [pc, #16] ; (8008ad0 ) + 8008abe: 729a strb r2, [r3, #10] + + //write to EEPROM + m24c64_write_page(&settings_array[0], EEPROM_SETTINGS_PAGE_ADDRESS); + 8008ac0: 2100 movs r1, #0 + 8008ac2: 4803 ldr r0, [pc, #12] ; (8008ad0 ) + 8008ac4: f7fa ff18 bl 80038f8 +} + 8008ac8: bf00 nop + 8008aca: 3710 adds r7, #16 + 8008acc: 46bd mov sp, r7 + 8008ace: bd80 pop {r7, pc} + 8008ad0: 200008ec .word 0x200008ec + +08008ad4 : + + + +//SI4463 Init +void si4463_init(void) +{ + 8008ad4: b580 push {r7, lr} + 8008ad6: b0de sub sp, #376 ; 0x178 + 8008ad8: af00 add r7, sp, #0 + cs_si4463_inactive(); //set pins initial state + 8008ada: f7f9 f8d3 bl 8001c84 + sdn_si4463_inactive(); + 8008ade: f7f9 f8b9 bl 8001c54 + delay_cyc(1000000); + 8008ae2: 482e ldr r0, [pc, #184] ; (8008b9c ) + 8008ae4: f7ff fca0 bl 8008428 + + sdn_si4463_active(); //reset the chip + 8008ae8: f7f9 f8a8 bl 8001c3c + delay_cyc(1000000); + 8008aec: 482b ldr r0, [pc, #172] ; (8008b9c ) + 8008aee: f7ff fc9b bl 8008428 + sdn_si4463_inactive(); + 8008af2: f7f9 f8af bl 8001c54 + + uint8_t init_arr[] = RADIO_CONFIGURATION_DATA_ARRAY; //array with init data, generated by WDS software + 8008af6: 1d3b adds r3, r7, #4 + 8008af8: 4a29 ldr r2, [pc, #164] ; (8008ba0 ) + 8008afa: 4618 mov r0, r3 + 8008afc: 4611 mov r1, r2 + 8008afe: f44f 73b6 mov.w r3, #364 ; 0x16c + 8008b02: 461a mov r2, r3 + 8008b04: f000 ff28 bl 8009958 + uint8_t *p_init_arr = &init_arr[0]; //pointer to the array + 8008b08: 1d3b adds r3, r7, #4 + 8008b0a: f8c7 3174 str.w r3, [r7, #372] ; 0x174 + + //Send all commands while pointer not equal 0x00 (0x00 presented in the end of the configuration array) + while(*p_init_arr != 0x00) + 8008b0e: e029 b.n 8008b64 + { + uint8_t len = *p_init_arr; //command len (first byte of the each line in configuration array) + 8008b10: f8d7 3174 ldr.w r3, [r7, #372] ; 0x174 + 8008b14: 781b ldrb r3, [r3, #0] + 8008b16: f887 3172 strb.w r3, [r7, #370] ; 0x172 + p_init_arr++; //move pointer to the first data byte (which is next after the command len) + 8008b1a: f8d7 3174 ldr.w r3, [r7, #372] ; 0x174 + 8008b1e: 3301 adds r3, #1 + 8008b20: f8c7 3174 str.w r3, [r7, #372] ; 0x174 + + si4463_wait_cts(); //check cts before any command + 8008b24: f000 f842 bl 8008bac + cs_si4463_active(); + 8008b28: f7f9 f8a0 bl 8001c6c + for(uint8_t i = 0; i < len; i++) + 8008b2c: 2300 movs r3, #0 + 8008b2e: f887 3173 strb.w r3, [r7, #371] ; 0x173 + 8008b32: e00f b.n 8008b54 + { + spi1_trx(*p_init_arr); //send command byte + 8008b34: f8d7 3174 ldr.w r3, [r7, #372] ; 0x174 + 8008b38: 781b ldrb r3, [r3, #0] + 8008b3a: 4618 mov r0, r3 + 8008b3c: f000 fa1a bl 8008f74 + p_init_arr++; //move pointer to the next byte in command + 8008b40: f8d7 3174 ldr.w r3, [r7, #372] ; 0x174 + 8008b44: 3301 adds r3, #1 + 8008b46: f8c7 3174 str.w r3, [r7, #372] ; 0x174 + for(uint8_t i = 0; i < len; i++) + 8008b4a: f897 3173 ldrb.w r3, [r7, #371] ; 0x173 + 8008b4e: 3301 adds r3, #1 + 8008b50: f887 3173 strb.w r3, [r7, #371] ; 0x173 + 8008b54: f897 2173 ldrb.w r2, [r7, #371] ; 0x173 + 8008b58: f897 3172 ldrb.w r3, [r7, #370] ; 0x172 + 8008b5c: 429a cmp r2, r3 + 8008b5e: d3e9 bcc.n 8008b34 + } + cs_si4463_inactive(); + 8008b60: f7f9 f890 bl 8001c84 + while(*p_init_arr != 0x00) + 8008b64: f8d7 3174 ldr.w r3, [r7, #372] ; 0x174 + 8008b68: 781b ldrb r3, [r3, #0] + 8008b6a: 2b00 cmp r3, #0 + 8008b6c: d1d0 bne.n 8008b10 + } + + //Set len of the packet + si4463_set_packet_len(AIR_PACKET_LEN); + 8008b6e: 2011 movs r0, #17 + 8008b70: f000 f82c bl 8008bcc + + //Get current settings + p_settings = get_settings(); + 8008b74: f7ff fee0 bl 8008938 + 8008b78: 4602 mov r2, r0 + 8008b7a: 4b0a ldr r3, [pc, #40] ; (8008ba4 ) + 8008b7c: 601a str r2, [r3, #0] + + //Set TX power + si4463_set_tx_power(tx_power_register_values[p_settings->tx_power_opt]); + 8008b7e: 4b09 ldr r3, [pc, #36] ; (8008ba4 ) + 8008b80: 681b ldr r3, [r3, #0] + 8008b82: 791b ldrb r3, [r3, #4] + 8008b84: 461a mov r2, r3 + 8008b86: 4b08 ldr r3, [pc, #32] ; (8008ba8 ) + 8008b88: 5c9b ldrb r3, [r3, r2] + 8008b8a: 4618 mov r0, r3 + 8008b8c: f000 f840 bl 8008c10 +} + 8008b90: bf00 nop + 8008b92: f507 77bc add.w r7, r7, #376 ; 0x178 + 8008b96: 46bd mov sp, r7 + 8008b98: bd80 pop {r7, pc} + 8008b9a: bf00 nop + 8008b9c: 000f4240 .word 0x000f4240 + 8008ba0: 0800cdd4 .word 0x0800cdd4 + 8008ba4: 2000061c .word 0x2000061c + 8008ba8: 2000005c .word 0x2000005c + +08008bac : + + + +//Wait for hardware CTS pin +void si4463_wait_cts(void) +{ + 8008bac: b480 push {r7} + 8008bae: af00 add r7, sp, #0 + while(!(GPIOA->IDR & GPIO_IDR_IDR12)){} //while GPIO1 = 0 + 8008bb0: bf00 nop + 8008bb2: 4b05 ldr r3, [pc, #20] ; (8008bc8 ) + 8008bb4: 689b ldr r3, [r3, #8] + 8008bb6: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8008bba: 2b00 cmp r3, #0 + 8008bbc: d0f9 beq.n 8008bb2 +} + 8008bbe: bf00 nop + 8008bc0: 46bd mov sp, r7 + 8008bc2: bc80 pop {r7} + 8008bc4: 4770 bx lr + 8008bc6: bf00 nop + 8008bc8: 40010800 .word 0x40010800 + +08008bcc : + + + +//Set air packet length +void si4463_set_packet_len(uint8_t packet_len) +{ + 8008bcc: b580 push {r7, lr} + 8008bce: b082 sub sp, #8 + 8008bd0: af00 add r7, sp, #0 + 8008bd2: 4603 mov r3, r0 + 8008bd4: 71fb strb r3, [r7, #7] + si4463_wait_cts(); + 8008bd6: f7ff ffe9 bl 8008bac + cs_si4463_active(); + 8008bda: f7f9 f847 bl 8001c6c + spi1_trx(SI4463_CMD_SET_PROPERTY); + 8008bde: 2011 movs r0, #17 + 8008be0: f000 f9c8 bl 8008f74 + spi1_trx(SI4463_PKT_FIELD_1_LENGTH_GROUP_ID); + 8008be4: 2012 movs r0, #18 + 8008be6: f000 f9c5 bl 8008f74 + spi1_trx(SI4463_PKT_FIELD_1_LENGTH_NUM_PROPS); + 8008bea: 2002 movs r0, #2 + 8008bec: f000 f9c2 bl 8008f74 + spi1_trx(SI4463_PKT_FIELD_1_LENGTH_START_PROP); + 8008bf0: 200d movs r0, #13 + 8008bf2: f000 f9bf bl 8008f74 + spi1_trx(0x00); //packet len high byte + 8008bf6: 2000 movs r0, #0 + 8008bf8: f000 f9bc bl 8008f74 + spi1_trx(packet_len); //packet len low byte + 8008bfc: 79fb ldrb r3, [r7, #7] + 8008bfe: 4618 mov r0, r3 + 8008c00: f000 f9b8 bl 8008f74 + cs_si4463_inactive(); + 8008c04: f7f9 f83e bl 8001c84 +} + 8008c08: bf00 nop + 8008c0a: 3708 adds r7, #8 + 8008c0c: 46bd mov sp, r7 + 8008c0e: bd80 pop {r7, pc} + +08008c10 : + + + +void si4463_set_tx_power(uint8_t tx_pow_reg_val) +{ + 8008c10: b580 push {r7, lr} + 8008c12: b082 sub sp, #8 + 8008c14: af00 add r7, sp, #0 + 8008c16: 4603 mov r3, r0 + 8008c18: 71fb strb r3, [r7, #7] + si4463_wait_cts(); + 8008c1a: f7ff ffc7 bl 8008bac + cs_si4463_active(); + 8008c1e: f7f9 f825 bl 8001c6c + spi1_trx(SI4463_CMD_SET_PROPERTY); + 8008c22: 2011 movs r0, #17 + 8008c24: f000 f9a6 bl 8008f74 + spi1_trx(SI4463_PA_PWR_LVL_GROUP_ID); + 8008c28: 2022 movs r0, #34 ; 0x22 + 8008c2a: f000 f9a3 bl 8008f74 + spi1_trx(SI4463_PA_PWR_LVL_NUM_PROPS); + 8008c2e: 2001 movs r0, #1 + 8008c30: f000 f9a0 bl 8008f74 + spi1_trx(SI4463_PA_PWR_LVL_START_PROP); + 8008c34: 2001 movs r0, #1 + 8008c36: f000 f99d bl 8008f74 + spi1_trx(tx_pow_reg_val); + 8008c3a: 79fb ldrb r3, [r7, #7] + 8008c3c: 4618 mov r0, r3 + 8008c3e: f000 f999 bl 8008f74 + cs_si4463_inactive(); + 8008c42: f7f9 f81f bl 8001c84 +} + 8008c46: bf00 nop + 8008c48: 3708 adds r7, #8 + 8008c4a: 46bd mov sp, r7 + 8008c4c: bd80 pop {r7, pc} + ... + +08008c50 : + + + +//SI4463 TX packet +void si4463_tx_packet(void) +{ + 8008c50: b580 push {r7, lr} + 8008c52: b082 sub sp, #8 + 8008c54: af00 add r7, sp, #0 + //reset TX FIFO + si4463_wait_cts(); + 8008c56: f7ff ffa9 bl 8008bac + cs_si4463_active(); + 8008c5a: f7f9 f807 bl 8001c6c + spi1_trx(SI4463_CMD_FIFO_INFO); + 8008c5e: 2015 movs r0, #21 + 8008c60: f000 f988 bl 8008f74 + spi1_trx(SI4463_FIFO_INFO_TX_BIT); + 8008c64: 2001 movs r0, #1 + 8008c66: f000 f985 bl 8008f74 + cs_si4463_inactive(); + 8008c6a: f7f9 f80b bl 8001c84 + + //fill TX FIFO buffer + si4463_wait_cts(); + 8008c6e: f7ff ff9d bl 8008bac + cs_si4463_active(); + 8008c72: f7f8 fffb bl 8001c6c + spi1_trx(SI4463_CMD_WRITE_TX_FIFO); + 8008c76: 2066 movs r0, #102 ; 0x66 + 8008c78: f000 f97c bl 8008f74 + for (uint8_t i = 0; i < AIR_PACKET_LEN; i++) + 8008c7c: 2300 movs r3, #0 + 8008c7e: 71fb strb r3, [r7, #7] + 8008c80: e008 b.n 8008c94 + { + spi1_trx(air_packet_tx[i]); + 8008c82: 79fb ldrb r3, [r7, #7] + 8008c84: 4a14 ldr r2, [pc, #80] ; (8008cd8 ) + 8008c86: 5cd3 ldrb r3, [r2, r3] + 8008c88: 4618 mov r0, r3 + 8008c8a: f000 f973 bl 8008f74 + for (uint8_t i = 0; i < AIR_PACKET_LEN; i++) + 8008c8e: 79fb ldrb r3, [r7, #7] + 8008c90: 3301 adds r3, #1 + 8008c92: 71fb strb r3, [r7, #7] + 8008c94: 79fb ldrb r3, [r7, #7] + 8008c96: 2b10 cmp r3, #16 + 8008c98: d9f3 bls.n 8008c82 + } + cs_si4463_inactive(); + 8008c9a: f7f8 fff3 bl 8001c84 + + //start TX + si4463_wait_cts(); + 8008c9e: f7ff ff85 bl 8008bac + cs_si4463_active(); + 8008ca2: f7f8 ffe3 bl 8001c6c + spi1_trx(SI4463_CMD_START_TX); + 8008ca6: 2031 movs r0, #49 ; 0x31 + 8008ca8: f000 f964 bl 8008f74 + spi1_trx(p_settings->freq_channel); //frequency channel + 8008cac: 4b0b ldr r3, [pc, #44] ; (8008cdc ) + 8008cae: 681b ldr r3, [r3, #0] + 8008cb0: 78db ldrb r3, [r3, #3] + 8008cb2: 4618 mov r0, r3 + 8008cb4: f000 f95e bl 8008f74 + spi1_trx(SI4463_SLEEP_STATE << 4); //return to sleep state, send FIFO content, start TX immediately + 8008cb8: 2010 movs r0, #16 + 8008cba: f000 f95b bl 8008f74 + spi1_trx(0x00); //the number of data bytes to be transmitted + 8008cbe: 2000 movs r0, #0 + 8008cc0: f000 f958 bl 8008f74 + spi1_trx(0x00); //is specified by the value(s) of the PKT_FIELD_X_LENGTH properties + 8008cc4: 2000 movs r0, #0 + 8008cc6: f000 f955 bl 8008f74 + cs_si4463_inactive(); + 8008cca: f7f8 ffdb bl 8001c84 +} + 8008cce: bf00 nop + 8008cd0: 3708 adds r7, #8 + 8008cd2: 46bd mov sp, r7 + 8008cd4: bd80 pop {r7, pc} + 8008cd6: bf00 nop + 8008cd8: 20000920 .word 0x20000920 + 8008cdc: 2000061c .word 0x2000061c + +08008ce0 : + + + +//SI4463 start packet RX +void si4463_start_rx(void) +{ + 8008ce0: b580 push {r7, lr} + 8008ce2: af00 add r7, sp, #0 + si4463_wait_cts(); + 8008ce4: f7ff ff62 bl 8008bac + cs_si4463_active(); + 8008ce8: f7f8 ffc0 bl 8001c6c + spi1_trx(SI4463_CMD_START_RX); + 8008cec: 2032 movs r0, #50 ; 0x32 + 8008cee: f000 f941 bl 8008f74 + spi1_trx(p_settings->freq_channel); //frequency channel + 8008cf2: 4b0e ldr r3, [pc, #56] ; (8008d2c ) + 8008cf4: 681b ldr r3, [r3, #0] + 8008cf6: 78db ldrb r3, [r3, #3] + 8008cf8: 4618 mov r0, r3 + 8008cfa: f000 f93b bl 8008f74 + spi1_trx(0x00); //start RX immediately + 8008cfe: 2000 movs r0, #0 + 8008d00: f000 f938 bl 8008f74 + spi1_trx(0x00); //RX packet len is specified + 8008d04: 2000 movs r0, #0 + 8008d06: f000 f935 bl 8008f74 + spi1_trx(0x00); //in packet handler configuration + 8008d0a: 2000 movs r0, #0 + 8008d0c: f000 f932 bl 8008f74 + spi1_trx(SI4463_SLEEP_STATE); //if RX timeout then go to sleep (after RX_PREAMBLE_TIMEOUT) + 8008d10: 2001 movs r0, #1 + 8008d12: f000 f92f bl 8008f74 + spi1_trx(SI4463_SLEEP_STATE); //if RX valid then go to sleep + 8008d16: 2001 movs r0, #1 + 8008d18: f000 f92c bl 8008f74 + spi1_trx(SI4463_SLEEP_STATE); //if RX invalid then go to sleep + 8008d1c: 2001 movs r0, #1 + 8008d1e: f000 f929 bl 8008f74 + cs_si4463_inactive(); + 8008d22: f7f8 ffaf bl 8001c84 +} + 8008d26: bf00 nop + 8008d28: bd80 pop {r7, pc} + 8008d2a: bf00 nop + 8008d2c: 2000061c .word 0x2000061c + +08008d30 : + + + +//SI4463 get received packet +uint8_t si4463_get_rx_packet(void) +{ + 8008d30: b590 push {r4, r7, lr} + 8008d32: b083 sub sp, #12 + 8008d34: af00 add r7, sp, #0 + uint8_t ph_pending = 0; + 8008d36: 2300 movs r3, #0 + 8008d38: 71bb strb r3, [r7, #6] + + //send get PH status command + si4463_wait_cts(); + 8008d3a: f7ff ff37 bl 8008bac + cs_si4463_active(); + 8008d3e: f7f8 ff95 bl 8001c6c + spi1_trx(SI4463_CMD_GET_PH_STATUS); + 8008d42: 2021 movs r0, #33 ; 0x21 + 8008d44: f000 f916 bl 8008f74 + spi1_trx(SI4463_BYTE_DUMMY); //also clear all pending interrupts + 8008d48: 2000 movs r0, #0 + 8008d4a: f000 f913 bl 8008f74 + cs_si4463_inactive(); + 8008d4e: f7f8 ff99 bl 8001c84 + + //retrieve response + si4463_wait_cts(); + 8008d52: f7ff ff2b bl 8008bac + cs_si4463_active(); + 8008d56: f7f8 ff89 bl 8001c6c + spi1_trx(SI4463_CMD_READ_CMD_BUF); + 8008d5a: 2044 movs r0, #68 ; 0x44 + 8008d5c: f000 f90a bl 8008f74 + spi1_trx(SI4463_BYTE_DUMMY); //skip CTS byte + 8008d60: 2000 movs r0, #0 + 8008d62: f000 f907 bl 8008f74 + ph_pending = spi1_trx(SI4463_BYTE_DUMMY); + 8008d66: 2000 movs r0, #0 + 8008d68: f000 f904 bl 8008f74 + 8008d6c: 4603 mov r3, r0 + 8008d6e: 71bb strb r3, [r7, #6] + cs_si4463_inactive(); + 8008d70: f7f8 ff88 bl 8001c84 + + if (ph_pending & SI4463_PH_PEND_CRC_ERROR_BIT) + 8008d74: 79bb ldrb r3, [r7, #6] + 8008d76: f003 0308 and.w r3, r3, #8 + 8008d7a: 2b00 cmp r3, #0 + 8008d7c: d019 beq.n 8008db2 + { + si4463_wait_cts(); //clear RX FIFO content + 8008d7e: f7ff ff15 bl 8008bac + cs_si4463_active(); + 8008d82: f7f8 ff73 bl 8001c6c + spi1_trx(SI4463_CMD_FIFO_INFO); + 8008d86: 2015 movs r0, #21 + 8008d88: f000 f8f4 bl 8008f74 + spi1_trx(SI4463_FIFO_INFO_RX_BIT); + 8008d8c: 2002 movs r0, #2 + 8008d8e: f000 f8f1 bl 8008f74 + cs_si4463_inactive(); + 8008d92: f7f8 ff77 bl 8001c84 + + si4463_wait_cts(); //workaround if received packet has CRC error (see si4463 revB1 errata) + 8008d96: f7ff ff09 bl 8008bac + cs_si4463_active(); + 8008d9a: f7f8 ff67 bl 8001c6c + spi1_trx(SI4463_CMD_CHANGE_STATE); + 8008d9e: 2034 movs r0, #52 ; 0x34 + 8008da0: f000 f8e8 bl 8008f74 + spi1_trx(SI4463_SLEEP_STATE); + 8008da4: 2001 movs r0, #1 + 8008da6: f000 f8e5 bl 8008f74 + cs_si4463_inactive(); + 8008daa: f7f8 ff6b bl 8001c84 + + return 0; + 8008dae: 2300 movs r3, #0 + 8008db0: e021 b.n 8008df6 + } + else if (ph_pending & SI4463_PH_PEND_PACKET_RX_BIT) + 8008db2: 79bb ldrb r3, [r7, #6] + 8008db4: f003 0310 and.w r3, r3, #16 + 8008db8: 2b00 cmp r3, #0 + 8008dba: d01b beq.n 8008df4 + { + //read RX FIFO buffer + si4463_wait_cts(); + 8008dbc: f7ff fef6 bl 8008bac + cs_si4463_active(); + 8008dc0: f7f8 ff54 bl 8001c6c + spi1_trx(SI4463_CMD_READ_RX_FIFO); + 8008dc4: 2077 movs r0, #119 ; 0x77 + 8008dc6: f000 f8d5 bl 8008f74 + for (uint8_t i = 0; i < AIR_PACKET_LEN; i++) + 8008dca: 2300 movs r3, #0 + 8008dcc: 71fb strb r3, [r7, #7] + 8008dce: e00a b.n 8008de6 + { + air_packet_rx[i] = spi1_trx(SI4463_BYTE_DUMMY); + 8008dd0: 79fc ldrb r4, [r7, #7] + 8008dd2: 2000 movs r0, #0 + 8008dd4: f000 f8ce bl 8008f74 + 8008dd8: 4603 mov r3, r0 + 8008dda: 461a mov r2, r3 + 8008ddc: 4b08 ldr r3, [pc, #32] ; (8008e00 ) + 8008dde: 551a strb r2, [r3, r4] + for (uint8_t i = 0; i < AIR_PACKET_LEN; i++) + 8008de0: 79fb ldrb r3, [r7, #7] + 8008de2: 3301 adds r3, #1 + 8008de4: 71fb strb r3, [r7, #7] + 8008de6: 79fb ldrb r3, [r7, #7] + 8008de8: 2b10 cmp r3, #16 + 8008dea: d9f1 bls.n 8008dd0 + } + cs_si4463_inactive(); + 8008dec: f7f8 ff4a bl 8001c84 + + return 1; + 8008df0: 2301 movs r3, #1 + 8008df2: e000 b.n 8008df6 + } + else + { + return 0; + 8008df4: 2300 movs r3, #0 + } +} + 8008df6: 4618 mov r0, r3 + 8008df8: 370c adds r7, #12 + 8008dfa: 46bd mov sp, r7 + 8008dfc: bd90 pop {r4, r7, pc} + 8008dfe: bf00 nop + 8008e00: 2000090c .word 0x2000090c + +08008e04 : + + + +uint8_t *get_air_packet_tx(void) +{ + 8008e04: b480 push {r7} + 8008e06: af00 add r7, sp, #0 + return &air_packet_tx[0]; + 8008e08: 4b02 ldr r3, [pc, #8] ; (8008e14 ) +} + 8008e0a: 4618 mov r0, r3 + 8008e0c: 46bd mov sp, r7 + 8008e0e: bc80 pop {r7} + 8008e10: 4770 bx lr + 8008e12: bf00 nop + 8008e14: 20000920 .word 0x20000920 + +08008e18 : + + + +uint8_t *get_air_packet_rx(void) +{ + 8008e18: b480 push {r7} + 8008e1a: af00 add r7, sp, #0 + return &air_packet_rx[0]; + 8008e1c: 4b02 ldr r3, [pc, #8] ; (8008e28 ) +} + 8008e1e: 4618 mov r0, r3 + 8008e20: 46bd mov sp, r7 + 8008e22: bc80 pop {r7} + 8008e24: 4770 bx lr + 8008e26: bf00 nop + 8008e28: 2000090c .word 0x2000090c + +08008e2c : + + + +//Init SPI1 +void spi1_init(void) +{ + 8008e2c: b480 push {r7} + 8008e2e: af00 add r7, sp, #0 + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; //enable clock spi1 + 8008e30: 4b29 ldr r3, [pc, #164] ; (8008ed8 ) + 8008e32: 699b ldr r3, [r3, #24] + 8008e34: 4a28 ldr r2, [pc, #160] ; (8008ed8 ) + 8008e36: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 8008e3a: 6193 str r3, [r2, #24] + RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; //enable alternate function clock + 8008e3c: 4b26 ldr r3, [pc, #152] ; (8008ed8 ) + 8008e3e: 699b ldr r3, [r3, #24] + 8008e40: 4a25 ldr r2, [pc, #148] ; (8008ed8 ) + 8008e42: f043 0301 orr.w r3, r3, #1 + 8008e46: 6193 str r3, [r2, #24] + AFIO->MAPR |= AFIO_MAPR_SPI1_REMAP; //remap spi + 8008e48: 4b24 ldr r3, [pc, #144] ; (8008edc ) + 8008e4a: 685b ldr r3, [r3, #4] + 8008e4c: 4a23 ldr r2, [pc, #140] ; (8008edc ) + 8008e4e: f043 0301 orr.w r3, r3, #1 + 8008e52: 6053 str r3, [r2, #4] + AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_JTAGDISABLE; //disable JTAG + 8008e54: 4b21 ldr r3, [pc, #132] ; (8008edc ) + 8008e56: 685b ldr r3, [r3, #4] + 8008e58: 4a20 ldr r2, [pc, #128] ; (8008edc ) + 8008e5a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 + 8008e5e: 6053 str r3, [r2, #4] + SPI1->CR1 &= ~SPI_CR1_BR; //clock/2 + 8008e60: 4b1f ldr r3, [pc, #124] ; (8008ee0 ) + 8008e62: 881b ldrh r3, [r3, #0] + 8008e64: b29b uxth r3, r3 + 8008e66: 4a1e ldr r2, [pc, #120] ; (8008ee0 ) + 8008e68: f023 0338 bic.w r3, r3, #56 ; 0x38 + 8008e6c: b29b uxth r3, r3 + 8008e6e: 8013 strh r3, [r2, #0] + SPI1->CR1 |= SPI_CR1_SSM; + 8008e70: 4b1b ldr r3, [pc, #108] ; (8008ee0 ) + 8008e72: 881b ldrh r3, [r3, #0] + 8008e74: b29b uxth r3, r3 + 8008e76: 4a1a ldr r2, [pc, #104] ; (8008ee0 ) + 8008e78: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8008e7c: b29b uxth r3, r3 + 8008e7e: 8013 strh r3, [r2, #0] + SPI1->CR1 |= SPI_CR1_SSI; + 8008e80: 4b17 ldr r3, [pc, #92] ; (8008ee0 ) + 8008e82: 881b ldrh r3, [r3, #0] + 8008e84: b29b uxth r3, r3 + 8008e86: 4a16 ldr r2, [pc, #88] ; (8008ee0 ) + 8008e88: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8008e8c: b29b uxth r3, r3 + 8008e8e: 8013 strh r3, [r2, #0] + SPI1->CR1 |= SPI_CR1_MSTR; //master mode + 8008e90: 4b13 ldr r3, [pc, #76] ; (8008ee0 ) + 8008e92: 881b ldrh r3, [r3, #0] + 8008e94: b29b uxth r3, r3 + 8008e96: 4a12 ldr r2, [pc, #72] ; (8008ee0 ) + 8008e98: f043 0304 orr.w r3, r3, #4 + 8008e9c: b29b uxth r3, r3 + 8008e9e: 8013 strh r3, [r2, #0] + SPI1->CR1 &= ~SPI_CR1_CPOL; //SCK = 0 in IDLE + 8008ea0: 4b0f ldr r3, [pc, #60] ; (8008ee0 ) + 8008ea2: 881b ldrh r3, [r3, #0] + 8008ea4: b29b uxth r3, r3 + 8008ea6: 4a0e ldr r2, [pc, #56] ; (8008ee0 ) + 8008ea8: f023 0302 bic.w r3, r3, #2 + 8008eac: b29b uxth r3, r3 + 8008eae: 8013 strh r3, [r2, #0] + SPI1->CR1 &= ~SPI_CR1_CPHA; //first rising edge capture + 8008eb0: 4b0b ldr r3, [pc, #44] ; (8008ee0 ) + 8008eb2: 881b ldrh r3, [r3, #0] + 8008eb4: b29b uxth r3, r3 + 8008eb6: 4a0a ldr r2, [pc, #40] ; (8008ee0 ) + 8008eb8: f023 0301 bic.w r3, r3, #1 + 8008ebc: b29b uxth r3, r3 + 8008ebe: 8013 strh r3, [r2, #0] + SPI1->CR1 |= SPI_CR1_SPE; //enable spi + 8008ec0: 4b07 ldr r3, [pc, #28] ; (8008ee0 ) + 8008ec2: 881b ldrh r3, [r3, #0] + 8008ec4: b29b uxth r3, r3 + 8008ec6: 4a06 ldr r2, [pc, #24] ; (8008ee0 ) + 8008ec8: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8008ecc: b29b uxth r3, r3 + 8008ece: 8013 strh r3, [r2, #0] +} + 8008ed0: bf00 nop + 8008ed2: 46bd mov sp, r7 + 8008ed4: bc80 pop {r7} + 8008ed6: 4770 bx lr + 8008ed8: 40021000 .word 0x40021000 + 8008edc: 40010000 .word 0x40010000 + 8008ee0: 40013000 .word 0x40013000 + +08008ee4 : + + + +//Init SPI2 +void spi2_init(void) +{ + 8008ee4: b480 push {r7} + 8008ee6: af00 add r7, sp, #0 + RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; //enable clock spi2 + 8008ee8: 4b20 ldr r3, [pc, #128] ; (8008f6c ) + 8008eea: 69db ldr r3, [r3, #28] + 8008eec: 4a1f ldr r2, [pc, #124] ; (8008f6c ) + 8008eee: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8008ef2: 61d3 str r3, [r2, #28] + SPI2->CR1 &= ~SPI_CR1_BR; //clock/2 + 8008ef4: 4b1e ldr r3, [pc, #120] ; (8008f70 ) + 8008ef6: 881b ldrh r3, [r3, #0] + 8008ef8: b29b uxth r3, r3 + 8008efa: 4a1d ldr r2, [pc, #116] ; (8008f70 ) + 8008efc: f023 0338 bic.w r3, r3, #56 ; 0x38 + 8008f00: b29b uxth r3, r3 + 8008f02: 8013 strh r3, [r2, #0] + SPI2->CR1 |= SPI_CR1_SSM; + 8008f04: 4b1a ldr r3, [pc, #104] ; (8008f70 ) + 8008f06: 881b ldrh r3, [r3, #0] + 8008f08: b29b uxth r3, r3 + 8008f0a: 4a19 ldr r2, [pc, #100] ; (8008f70 ) + 8008f0c: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8008f10: b29b uxth r3, r3 + 8008f12: 8013 strh r3, [r2, #0] + SPI2->CR1 |= SPI_CR1_SSI; + 8008f14: 4b16 ldr r3, [pc, #88] ; (8008f70 ) + 8008f16: 881b ldrh r3, [r3, #0] + 8008f18: b29b uxth r3, r3 + 8008f1a: 4a15 ldr r2, [pc, #84] ; (8008f70 ) + 8008f1c: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8008f20: b29b uxth r3, r3 + 8008f22: 8013 strh r3, [r2, #0] + SPI2->CR1 |= SPI_CR1_MSTR; //master mode + 8008f24: 4b12 ldr r3, [pc, #72] ; (8008f70 ) + 8008f26: 881b ldrh r3, [r3, #0] + 8008f28: b29b uxth r3, r3 + 8008f2a: 4a11 ldr r2, [pc, #68] ; (8008f70 ) + 8008f2c: f043 0304 orr.w r3, r3, #4 + 8008f30: b29b uxth r3, r3 + 8008f32: 8013 strh r3, [r2, #0] + SPI2->CR1 &= ~SPI_CR1_CPOL; //SCK = 0 in IDLE + 8008f34: 4b0e ldr r3, [pc, #56] ; (8008f70 ) + 8008f36: 881b ldrh r3, [r3, #0] + 8008f38: b29b uxth r3, r3 + 8008f3a: 4a0d ldr r2, [pc, #52] ; (8008f70 ) + 8008f3c: f023 0302 bic.w r3, r3, #2 + 8008f40: b29b uxth r3, r3 + 8008f42: 8013 strh r3, [r2, #0] + SPI2->CR1 &= ~SPI_CR1_CPHA; //first rising edge capture + 8008f44: 4b0a ldr r3, [pc, #40] ; (8008f70 ) + 8008f46: 881b ldrh r3, [r3, #0] + 8008f48: b29b uxth r3, r3 + 8008f4a: 4a09 ldr r2, [pc, #36] ; (8008f70 ) + 8008f4c: f023 0301 bic.w r3, r3, #1 + 8008f50: b29b uxth r3, r3 + 8008f52: 8013 strh r3, [r2, #0] + SPI2->CR1 |= SPI_CR1_SPE; //enable spi + 8008f54: 4b06 ldr r3, [pc, #24] ; (8008f70 ) + 8008f56: 881b ldrh r3, [r3, #0] + 8008f58: b29b uxth r3, r3 + 8008f5a: 4a05 ldr r2, [pc, #20] ; (8008f70 ) + 8008f5c: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8008f60: b29b uxth r3, r3 + 8008f62: 8013 strh r3, [r2, #0] +} + 8008f64: bf00 nop + 8008f66: 46bd mov sp, r7 + 8008f68: bc80 pop {r7} + 8008f6a: 4770 bx lr + 8008f6c: 40021000 .word 0x40021000 + 8008f70: 40003800 .word 0x40003800 + +08008f74 : + + + +//TRX one byte via SPI1 +uint8_t spi1_trx(uint8_t send_data) +{ + 8008f74: b480 push {r7} + 8008f76: b083 sub sp, #12 + 8008f78: af00 add r7, sp, #0 + 8008f7a: 4603 mov r3, r0 + 8008f7c: 71fb strb r3, [r7, #7] + while(!(SPI1->SR & SPI_SR_TXE)){} //while TXE bit = 0 + 8008f7e: bf00 nop + 8008f80: 4b0d ldr r3, [pc, #52] ; (8008fb8 ) + 8008f82: 891b ldrh r3, [r3, #8] + 8008f84: b29b uxth r3, r3 + 8008f86: f003 0302 and.w r3, r3, #2 + 8008f8a: 2b00 cmp r3, #0 + 8008f8c: d0f8 beq.n 8008f80 + SPI1->DR = send_data; + 8008f8e: 4b0a ldr r3, [pc, #40] ; (8008fb8 ) + 8008f90: 79fa ldrb r2, [r7, #7] + 8008f92: b292 uxth r2, r2 + 8008f94: 819a strh r2, [r3, #12] + + while(!(SPI1->SR & SPI_SR_RXNE)){} //while RXNE = 0 + 8008f96: bf00 nop + 8008f98: 4b07 ldr r3, [pc, #28] ; (8008fb8 ) + 8008f9a: 891b ldrh r3, [r3, #8] + 8008f9c: b29b uxth r3, r3 + 8008f9e: f003 0301 and.w r3, r3, #1 + 8008fa2: 2b00 cmp r3, #0 + 8008fa4: d0f8 beq.n 8008f98 + return SPI1->DR; + 8008fa6: 4b04 ldr r3, [pc, #16] ; (8008fb8 ) + 8008fa8: 899b ldrh r3, [r3, #12] + 8008faa: b29b uxth r3, r3 + 8008fac: b2db uxtb r3, r3 +} + 8008fae: 4618 mov r0, r3 + 8008fb0: 370c adds r7, #12 + 8008fb2: 46bd mov sp, r7 + 8008fb4: bc80 pop {r7} + 8008fb6: 4770 bx lr + 8008fb8: 40013000 .word 0x40013000 + +08008fbc : + + + +//TRX one byte via SPI2 +uint8_t spi2_trx(uint8_t send_data) +{ + 8008fbc: b480 push {r7} + 8008fbe: b083 sub sp, #12 + 8008fc0: af00 add r7, sp, #0 + 8008fc2: 4603 mov r3, r0 + 8008fc4: 71fb strb r3, [r7, #7] + while (!(SPI2->SR & SPI_SR_TXE)){} //while TXE bit = 0 + 8008fc6: bf00 nop + 8008fc8: 4b0d ldr r3, [pc, #52] ; (8009000 ) + 8008fca: 891b ldrh r3, [r3, #8] + 8008fcc: b29b uxth r3, r3 + 8008fce: f003 0302 and.w r3, r3, #2 + 8008fd2: 2b00 cmp r3, #0 + 8008fd4: d0f8 beq.n 8008fc8 + SPI2->DR = send_data; + 8008fd6: 4b0a ldr r3, [pc, #40] ; (8009000 ) + 8008fd8: 79fa ldrb r2, [r7, #7] + 8008fda: b292 uxth r2, r2 + 8008fdc: 819a strh r2, [r3, #12] + + while (!(SPI2->SR & SPI_SR_RXNE)){} //while RXNE = 0 + 8008fde: bf00 nop + 8008fe0: 4b07 ldr r3, [pc, #28] ; (8009000 ) + 8008fe2: 891b ldrh r3, [r3, #8] + 8008fe4: b29b uxth r3, r3 + 8008fe6: f003 0301 and.w r3, r3, #1 + 8008fea: 2b00 cmp r3, #0 + 8008fec: d0f8 beq.n 8008fe0 + return SPI2->DR; + 8008fee: 4b04 ldr r3, [pc, #16] ; (8009000 ) + 8008ff0: 899b ldrh r3, [r3, #12] + 8008ff2: b29b uxth r3, r3 + 8008ff4: b2db uxtb r3, r3 +} + 8008ff6: 4618 mov r0, r3 + 8008ff8: 370c adds r7, #12 + 8008ffa: 46bd mov sp, r7 + 8008ffc: bc80 pop {r7} + 8008ffe: 4770 bx lr + 8009000: 40003800 .word 0x40003800 + +08009004 : + + + +//SSD1306 Init +void ssd1306_init(void) +{ + 8009004: b580 push {r7, lr} + 8009006: b082 sub sp, #8 + 8009008: af00 add r7, sp, #0 + cs_ssd1306_inactive(); //ports init state + 800900a: f7f8 fe83 bl 8001d14 + res_ssd1306_inactive(); + 800900e: f7f8 fe51 bl 8001cb4 + ssd1306_command_mode(); + 8009012: f7f8 fe67 bl 8001ce4 + delay_cyc(100000); + 8009016: 481c ldr r0, [pc, #112] ; (8009088 ) + 8009018: f7ff fa06 bl 8008428 + + res_ssd1306_active(); //reset ssd1306 + 800901c: f7f8 fe3e bl 8001c9c + delay_cyc(100000); + 8009020: 4819 ldr r0, [pc, #100] ; (8009088 ) + 8009022: f7ff fa01 bl 8008428 + res_ssd1306_inactive(); + 8009026: f7f8 fe45 bl 8001cb4 + delay_cyc(100000); + 800902a: 4817 ldr r0, [pc, #92] ; (8009088 ) + 800902c: f7ff f9fc bl 8008428 + + uint8_t i = 0; + 8009030: 2300 movs r3, #0 + 8009032: 71fb strb r3, [r7, #7] + uint8_t len = 0; + 8009034: 2300 movs r3, #0 + 8009036: 71bb strb r3, [r7, #6] + while (ssd1306_conf[i] != 0x00) + 8009038: e019 b.n 800906e + { + len = ssd1306_conf[i++]; + 800903a: 79fb ldrb r3, [r7, #7] + 800903c: 1c5a adds r2, r3, #1 + 800903e: 71fa strb r2, [r7, #7] + 8009040: 461a mov r2, r3 + 8009042: 4b12 ldr r3, [pc, #72] ; (800908c ) + 8009044: 5c9b ldrb r3, [r3, r2] + 8009046: 71bb strb r3, [r7, #6] + + cs_ssd1306_active(); + 8009048: f7f8 fe58 bl 8001cfc + while (len--) + 800904c: e008 b.n 8009060 + { + spi2_trx(ssd1306_conf[i++]); + 800904e: 79fb ldrb r3, [r7, #7] + 8009050: 1c5a adds r2, r3, #1 + 8009052: 71fa strb r2, [r7, #7] + 8009054: 461a mov r2, r3 + 8009056: 4b0d ldr r3, [pc, #52] ; (800908c ) + 8009058: 5c9b ldrb r3, [r3, r2] + 800905a: 4618 mov r0, r3 + 800905c: f7ff ffae bl 8008fbc + while (len--) + 8009060: 79bb ldrb r3, [r7, #6] + 8009062: 1e5a subs r2, r3, #1 + 8009064: 71ba strb r2, [r7, #6] + 8009066: 2b00 cmp r3, #0 + 8009068: d1f1 bne.n 800904e + } + cs_ssd1306_inactive(); + 800906a: f7f8 fe53 bl 8001d14 + while (ssd1306_conf[i] != 0x00) + 800906e: 79fb ldrb r3, [r7, #7] + 8009070: 4a06 ldr r2, [pc, #24] ; (800908c ) + 8009072: 5cd3 ldrb r3, [r2, r3] + 8009074: 2b00 cmp r3, #0 + 8009076: d1e0 bne.n 800903a + } + + ssd1306_clear(); + 8009078: f000 f82a bl 80090d0 + ssd1306_update(); + 800907c: f000 f808 bl 8009090 +} + 8009080: bf00 nop + 8009082: 3708 adds r7, #8 + 8009084: 46bd mov sp, r7 + 8009086: bd80 pop {r7, pc} + 8009088: 000186a0 .word 0x000186a0 + 800908c: 0800d538 .word 0x0800d538 + +08009090 : + + + +//Update screen with buffer content +void ssd1306_update(void) +{ + 8009090: b580 push {r7, lr} + 8009092: b082 sub sp, #8 + 8009094: af00 add r7, sp, #0 + ssd1306_data_mode(); + 8009096: f7f8 fe19 bl 8001ccc + cs_ssd1306_active(); + 800909a: f7f8 fe2f bl 8001cfc + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + 800909e: 2300 movs r3, #0 + 80090a0: 80fb strh r3, [r7, #6] + 80090a2: e008 b.n 80090b6 + { + spi2_trx(screen_buf[i]); + 80090a4: 88fb ldrh r3, [r7, #6] + 80090a6: 4a09 ldr r2, [pc, #36] ; (80090cc ) + 80090a8: 5cd3 ldrb r3, [r2, r3] + 80090aa: 4618 mov r0, r3 + 80090ac: f7ff ff86 bl 8008fbc + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + 80090b0: 88fb ldrh r3, [r7, #6] + 80090b2: 3301 adds r3, #1 + 80090b4: 80fb strh r3, [r7, #6] + 80090b6: 88fb ldrh r3, [r7, #6] + 80090b8: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80090bc: d3f2 bcc.n 80090a4 + } + cs_ssd1306_inactive(); + 80090be: f7f8 fe29 bl 8001d14 +} + 80090c2: bf00 nop + 80090c4: 3708 adds r7, #8 + 80090c6: 46bd mov sp, r7 + 80090c8: bd80 pop {r7, pc} + 80090ca: bf00 nop + 80090cc: 20000934 .word 0x20000934 + +080090d0 : + + + +//Clear all screen pixels +void ssd1306_clear(void) +{ + 80090d0: b480 push {r7} + 80090d2: b083 sub sp, #12 + 80090d4: af00 add r7, sp, #0 + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + 80090d6: 2300 movs r3, #0 + 80090d8: 80fb strh r3, [r7, #6] + 80090da: e006 b.n 80090ea + { + screen_buf[i] = 0x00; + 80090dc: 88fb ldrh r3, [r7, #6] + 80090de: 4a07 ldr r2, [pc, #28] ; (80090fc ) + 80090e0: 2100 movs r1, #0 + 80090e2: 54d1 strb r1, [r2, r3] + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + 80090e4: 88fb ldrh r3, [r7, #6] + 80090e6: 3301 adds r3, #1 + 80090e8: 80fb strh r3, [r7, #6] + 80090ea: 88fb ldrh r3, [r7, #6] + 80090ec: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80090f0: d3f4 bcc.n 80090dc + } +} + 80090f2: bf00 nop + 80090f4: 370c adds r7, #12 + 80090f6: 46bd mov sp, r7 + 80090f8: bc80 pop {r7} + 80090fa: 4770 bx lr + 80090fc: 20000934 .word 0x20000934 + +08009100 : + + + +//Clear, Set or Reset any pixel on the screen (x 0-127, y 0-63) +void ssd1306_pixel(uint8_t x, uint8_t y, int8_t action) +{ + 8009100: b480 push {r7} + 8009102: b083 sub sp, #12 + 8009104: af00 add r7, sp, #0 + 8009106: 4603 mov r3, r0 + 8009108: 71fb strb r3, [r7, #7] + 800910a: 460b mov r3, r1 + 800910c: 71bb strb r3, [r7, #6] + 800910e: 4613 mov r3, r2 + 8009110: 717b strb r3, [r7, #5] + switch (action) + 8009112: f997 3005 ldrsb.w r3, [r7, #5] + 8009116: 2b00 cmp r3, #0 + 8009118: d002 beq.n 8009120 + 800911a: 2b01 cmp r3, #1 + 800911c: d01d beq.n 800915a + 800911e: e037 b.n 8009190 + { + case 0: //clear pixel + screen_buf[x + (y / 8) * LCD_SIZE_X] &= ~(1 << (y % 8)); + 8009120: 79fa ldrb r2, [r7, #7] + 8009122: 79bb ldrb r3, [r7, #6] + 8009124: 08db lsrs r3, r3, #3 + 8009126: b2d8 uxtb r0, r3 + 8009128: 4603 mov r3, r0 + 800912a: 01db lsls r3, r3, #7 + 800912c: 4413 add r3, r2 + 800912e: 4a28 ldr r2, [pc, #160] ; (80091d0 ) + 8009130: 5cd3 ldrb r3, [r2, r3] + 8009132: b25a sxtb r2, r3 + 8009134: 79bb ldrb r3, [r7, #6] + 8009136: f003 0307 and.w r3, r3, #7 + 800913a: 2101 movs r1, #1 + 800913c: fa01 f303 lsl.w r3, r1, r3 + 8009140: b25b sxtb r3, r3 + 8009142: 43db mvns r3, r3 + 8009144: b25b sxtb r3, r3 + 8009146: 4013 ands r3, r2 + 8009148: b259 sxtb r1, r3 + 800914a: 79fa ldrb r2, [r7, #7] + 800914c: 4603 mov r3, r0 + 800914e: 01db lsls r3, r3, #7 + 8009150: 4413 add r3, r2 + 8009152: b2c9 uxtb r1, r1 + 8009154: 4a1e ldr r2, [pc, #120] ; (80091d0 ) + 8009156: 54d1 strb r1, [r2, r3] + break; + 8009158: e035 b.n 80091c6 + case 1: //set pixel + screen_buf[x + (y / 8) * LCD_SIZE_X] |= 1 << (y % 8); + 800915a: 79fa ldrb r2, [r7, #7] + 800915c: 79bb ldrb r3, [r7, #6] + 800915e: 08db lsrs r3, r3, #3 + 8009160: b2d8 uxtb r0, r3 + 8009162: 4603 mov r3, r0 + 8009164: 01db lsls r3, r3, #7 + 8009166: 4413 add r3, r2 + 8009168: 4a19 ldr r2, [pc, #100] ; (80091d0 ) + 800916a: 5cd3 ldrb r3, [r2, r3] + 800916c: b25a sxtb r2, r3 + 800916e: 79bb ldrb r3, [r7, #6] + 8009170: f003 0307 and.w r3, r3, #7 + 8009174: 2101 movs r1, #1 + 8009176: fa01 f303 lsl.w r3, r1, r3 + 800917a: b25b sxtb r3, r3 + 800917c: 4313 orrs r3, r2 + 800917e: b259 sxtb r1, r3 + 8009180: 79fa ldrb r2, [r7, #7] + 8009182: 4603 mov r3, r0 + 8009184: 01db lsls r3, r3, #7 + 8009186: 4413 add r3, r2 + 8009188: b2c9 uxtb r1, r1 + 800918a: 4a11 ldr r2, [pc, #68] ; (80091d0 ) + 800918c: 54d1 strb r1, [r2, r3] + break; + 800918e: e01a b.n 80091c6 + default: //invert pixel + screen_buf[x + (y / 8) * LCD_SIZE_X] ^= 1 << (y % 8); + 8009190: 79fa ldrb r2, [r7, #7] + 8009192: 79bb ldrb r3, [r7, #6] + 8009194: 08db lsrs r3, r3, #3 + 8009196: b2d8 uxtb r0, r3 + 8009198: 4603 mov r3, r0 + 800919a: 01db lsls r3, r3, #7 + 800919c: 4413 add r3, r2 + 800919e: 4a0c ldr r2, [pc, #48] ; (80091d0 ) + 80091a0: 5cd3 ldrb r3, [r2, r3] + 80091a2: b25a sxtb r2, r3 + 80091a4: 79bb ldrb r3, [r7, #6] + 80091a6: f003 0307 and.w r3, r3, #7 + 80091aa: 2101 movs r1, #1 + 80091ac: fa01 f303 lsl.w r3, r1, r3 + 80091b0: b25b sxtb r3, r3 + 80091b2: 4053 eors r3, r2 + 80091b4: b259 sxtb r1, r3 + 80091b6: 79fa ldrb r2, [r7, #7] + 80091b8: 4603 mov r3, r0 + 80091ba: 01db lsls r3, r3, #7 + 80091bc: 4413 add r3, r2 + 80091be: b2c9 uxtb r1, r1 + 80091c0: 4a03 ldr r2, [pc, #12] ; (80091d0 ) + 80091c2: 54d1 strb r1, [r2, r3] + break; + 80091c4: bf00 nop + } +} + 80091c6: bf00 nop + 80091c8: 370c adds r7, #12 + 80091ca: 46bd mov sp, r7 + 80091cc: bc80 pop {r7} + 80091ce: 4770 bx lr + 80091d0: 20000934 .word 0x20000934 + +080091d4 : + + + +//Set character position on screen (rows 0-7, cols 0-20) +void ssd1306_pos(uint8_t row, uint8_t col) +{ + 80091d4: b480 push {r7} + 80091d6: b083 sub sp, #12 + 80091d8: af00 add r7, sp, #0 + 80091da: 4603 mov r3, r0 + 80091dc: 460a mov r2, r1 + 80091de: 71fb strb r3, [r7, #7] + 80091e0: 4613 mov r3, r2 + 80091e2: 71bb strb r3, [r7, #6] + buf_pos = (row * 21 + col) * FONT_SIZE_X + 2 * row; //+2 bytes, because 128 - 21 * 6 = 2 + 80091e4: 79fa ldrb r2, [r7, #7] + 80091e6: 4613 mov r3, r2 + 80091e8: 005b lsls r3, r3, #1 + 80091ea: 4413 add r3, r2 + 80091ec: 00da lsls r2, r3, #3 + 80091ee: 1ad2 subs r2, r2, r3 + 80091f0: 79bb ldrb r3, [r7, #6] + 80091f2: 441a add r2, r3 + 80091f4: 4613 mov r3, r2 + 80091f6: 005b lsls r3, r3, #1 + 80091f8: 441a add r2, r3 + 80091fa: 79fb ldrb r3, [r7, #7] + 80091fc: 4413 add r3, r2 + 80091fe: b29b uxth r3, r3 + 8009200: 005b lsls r3, r3, #1 + 8009202: b29a uxth r2, r3 + 8009204: 4b03 ldr r3, [pc, #12] ; (8009214 ) + 8009206: 801a strh r2, [r3, #0] +} + 8009208: bf00 nop + 800920a: 370c adds r7, #12 + 800920c: 46bd mov sp, r7 + 800920e: bc80 pop {r7} + 8009210: 4770 bx lr + 8009212: bf00 nop + 8009214: 20000124 .word 0x20000124 + +08009218 : + + + +//Put one char in buffer in position, defined previously via ssd1306_pos() +void ssd1306_char(char chr, uint8_t inv) +{ + 8009218: b480 push {r7} + 800921a: b085 sub sp, #20 + 800921c: af00 add r7, sp, #0 + 800921e: 4603 mov r3, r0 + 8009220: 460a mov r2, r1 + 8009222: 71fb strb r3, [r7, #7] + 8009224: 4613 mov r3, r2 + 8009226: 71bb strb r3, [r7, #6] + if (inv) + 8009228: 79bb ldrb r3, [r7, #6] + 800922a: 2b00 cmp r3, #0 + 800922c: d002 beq.n 8009234 + { + inv = 0xFF; + 800922e: 23ff movs r3, #255 ; 0xff + 8009230: 71bb strb r3, [r7, #6] + 8009232: e001 b.n 8009238 + } + else + { + inv = 0x00; + 8009234: 2300 movs r3, #0 + 8009236: 71bb strb r3, [r7, #6] + } + + for (uint8_t i = 0; i < FONT_SIZE_X - 1; i++) + 8009238: 2300 movs r3, #0 + 800923a: 73fb strb r3, [r7, #15] + 800923c: e017 b.n 800926e + { + screen_buf[buf_pos++] = font[(uint8_t)chr][i] ^ inv; + 800923e: 79fa ldrb r2, [r7, #7] + 8009240: 7bf9 ldrb r1, [r7, #15] + 8009242: 4814 ldr r0, [pc, #80] ; (8009294 ) + 8009244: 4613 mov r3, r2 + 8009246: 009b lsls r3, r3, #2 + 8009248: 4413 add r3, r2 + 800924a: 4403 add r3, r0 + 800924c: 440b add r3, r1 + 800924e: 781a ldrb r2, [r3, #0] + 8009250: 4b11 ldr r3, [pc, #68] ; (8009298 ) + 8009252: 881b ldrh r3, [r3, #0] + 8009254: 1c59 adds r1, r3, #1 + 8009256: b288 uxth r0, r1 + 8009258: 490f ldr r1, [pc, #60] ; (8009298 ) + 800925a: 8008 strh r0, [r1, #0] + 800925c: 4619 mov r1, r3 + 800925e: 79bb ldrb r3, [r7, #6] + 8009260: 4053 eors r3, r2 + 8009262: b2da uxtb r2, r3 + 8009264: 4b0d ldr r3, [pc, #52] ; (800929c ) + 8009266: 545a strb r2, [r3, r1] + for (uint8_t i = 0; i < FONT_SIZE_X - 1; i++) + 8009268: 7bfb ldrb r3, [r7, #15] + 800926a: 3301 adds r3, #1 + 800926c: 73fb strb r3, [r7, #15] + 800926e: 7bfb ldrb r3, [r7, #15] + 8009270: 2b04 cmp r3, #4 + 8009272: d9e4 bls.n 800923e + } + screen_buf[buf_pos++] = 0x00 ^ inv; //intercharacter space + 8009274: 4b08 ldr r3, [pc, #32] ; (8009298 ) + 8009276: 881b ldrh r3, [r3, #0] + 8009278: 1c5a adds r2, r3, #1 + 800927a: b291 uxth r1, r2 + 800927c: 4a06 ldr r2, [pc, #24] ; (8009298 ) + 800927e: 8011 strh r1, [r2, #0] + 8009280: 4619 mov r1, r3 + 8009282: 4a06 ldr r2, [pc, #24] ; (800929c ) + 8009284: 79bb ldrb r3, [r7, #6] + 8009286: 5453 strb r3, [r2, r1] +} + 8009288: bf00 nop + 800928a: 3714 adds r7, #20 + 800928c: 46bd mov sp, r7 + 800928e: bc80 pop {r7} + 8009290: 4770 bx lr + 8009292: bf00 nop + 8009294: 0800d268 .word 0x0800d268 + 8009298: 20000124 .word 0x20000124 + 800929c: 20000934 .word 0x20000934 + +080092a0 : + + + +//Put one char in defined pos +void ssd1306_char_pos(uint8_t row, uint8_t col, char chr, uint8_t inv) +{ + 80092a0: b590 push {r4, r7, lr} + 80092a2: b083 sub sp, #12 + 80092a4: af00 add r7, sp, #0 + 80092a6: 4604 mov r4, r0 + 80092a8: 4608 mov r0, r1 + 80092aa: 4611 mov r1, r2 + 80092ac: 461a mov r2, r3 + 80092ae: 4623 mov r3, r4 + 80092b0: 71fb strb r3, [r7, #7] + 80092b2: 4603 mov r3, r0 + 80092b4: 71bb strb r3, [r7, #6] + 80092b6: 460b mov r3, r1 + 80092b8: 717b strb r3, [r7, #5] + 80092ba: 4613 mov r3, r2 + 80092bc: 713b strb r3, [r7, #4] + ssd1306_pos(row, col); + 80092be: 79ba ldrb r2, [r7, #6] + 80092c0: 79fb ldrb r3, [r7, #7] + 80092c2: 4611 mov r1, r2 + 80092c4: 4618 mov r0, r3 + 80092c6: f7ff ff85 bl 80091d4 + ssd1306_char(chr, inv); + 80092ca: 793a ldrb r2, [r7, #4] + 80092cc: 797b ldrb r3, [r7, #5] + 80092ce: 4611 mov r1, r2 + 80092d0: 4618 mov r0, r3 + 80092d2: f7ff ffa1 bl 8009218 +} + 80092d6: bf00 nop + 80092d8: 370c adds r7, #12 + 80092da: 46bd mov sp, r7 + 80092dc: bd90 pop {r4, r7, pc} + +080092de : + + + +//Print string on screen (with position) +void ssd1306_print(uint8_t row, uint8_t col, char *p_str, uint8_t inv) +{ + 80092de: b580 push {r7, lr} + 80092e0: b082 sub sp, #8 + 80092e2: af00 add r7, sp, #0 + 80092e4: 603a str r2, [r7, #0] + 80092e6: 461a mov r2, r3 + 80092e8: 4603 mov r3, r0 + 80092ea: 71fb strb r3, [r7, #7] + 80092ec: 460b mov r3, r1 + 80092ee: 71bb strb r3, [r7, #6] + 80092f0: 4613 mov r3, r2 + 80092f2: 717b strb r3, [r7, #5] + ssd1306_pos(row, col); + 80092f4: 79ba ldrb r2, [r7, #6] + 80092f6: 79fb ldrb r3, [r7, #7] + 80092f8: 4611 mov r1, r2 + 80092fa: 4618 mov r0, r3 + 80092fc: f7ff ff6a bl 80091d4 + + while (*p_str) + 8009300: e008 b.n 8009314 + { + ssd1306_char(*p_str++, inv); + 8009302: 683b ldr r3, [r7, #0] + 8009304: 1c5a adds r2, r3, #1 + 8009306: 603a str r2, [r7, #0] + 8009308: 781b ldrb r3, [r3, #0] + 800930a: 797a ldrb r2, [r7, #5] + 800930c: 4611 mov r1, r2 + 800930e: 4618 mov r0, r3 + 8009310: f7ff ff82 bl 8009218 + while (*p_str) + 8009314: 683b ldr r3, [r7, #0] + 8009316: 781b ldrb r3, [r3, #0] + 8009318: 2b00 cmp r3, #0 + 800931a: d1f2 bne.n 8009302 + } +} + 800931c: bf00 nop + 800931e: 3708 adds r7, #8 + 8009320: 46bd mov sp, r7 + 8009322: bd80 pop {r7, pc} + +08009324 : + + + +//Print string on screen (with position) in viceversa direction (decrease collumn) +void ssd1306_print_viceversa(uint8_t row, uint8_t col, char *p_str, uint8_t inv) +{ + 8009324: b580 push {r7, lr} + 8009326: b084 sub sp, #16 + 8009328: af00 add r7, sp, #0 + 800932a: 603a str r2, [r7, #0] + 800932c: 461a mov r2, r3 + 800932e: 4603 mov r3, r0 + 8009330: 71fb strb r3, [r7, #7] + 8009332: 460b mov r3, r1 + 8009334: 71bb strb r3, [r7, #6] + 8009336: 4613 mov r3, r2 + 8009338: 717b strb r3, [r7, #5] + uint8_t symb_cntr = 0; + 800933a: 2300 movs r3, #0 + 800933c: 73fb strb r3, [r7, #15] + + ssd1306_pos(row, col); + 800933e: 79ba ldrb r2, [r7, #6] + 8009340: 79fb ldrb r3, [r7, #7] + 8009342: 4611 mov r1, r2 + 8009344: 4618 mov r0, r3 + 8009346: f7ff ff45 bl 80091d4 + + while (*p_str) + 800934a: e005 b.n 8009358 + { + p_str++; + 800934c: 683b ldr r3, [r7, #0] + 800934e: 3301 adds r3, #1 + 8009350: 603b str r3, [r7, #0] + symb_cntr++; + 8009352: 7bfb ldrb r3, [r7, #15] + 8009354: 3301 adds r3, #1 + 8009356: 73fb strb r3, [r7, #15] + while (*p_str) + 8009358: 683b ldr r3, [r7, #0] + 800935a: 781b ldrb r3, [r3, #0] + 800935c: 2b00 cmp r3, #0 + 800935e: d1f5 bne.n 800934c + } + + while (symb_cntr) + 8009360: e012 b.n 8009388 + { + symb_cntr--; + 8009362: 7bfb ldrb r3, [r7, #15] + 8009364: 3b01 subs r3, #1 + 8009366: 73fb strb r3, [r7, #15] + ssd1306_char(*--p_str, inv); + 8009368: 683b ldr r3, [r7, #0] + 800936a: 3b01 subs r3, #1 + 800936c: 603b str r3, [r7, #0] + 800936e: 683b ldr r3, [r7, #0] + 8009370: 781b ldrb r3, [r3, #0] + 8009372: 797a ldrb r2, [r7, #5] + 8009374: 4611 mov r1, r2 + 8009376: 4618 mov r0, r3 + 8009378: f7ff ff4e bl 8009218 + buf_pos -= 2 * FONT_SIZE_X; //minus two characters position + 800937c: 4b06 ldr r3, [pc, #24] ; (8009398 ) + 800937e: 881b ldrh r3, [r3, #0] + 8009380: 3b0c subs r3, #12 + 8009382: b29a uxth r2, r3 + 8009384: 4b04 ldr r3, [pc, #16] ; (8009398 ) + 8009386: 801a strh r2, [r3, #0] + while (symb_cntr) + 8009388: 7bfb ldrb r3, [r7, #15] + 800938a: 2b00 cmp r3, #0 + 800938c: d1e9 bne.n 8009362 + } +} + 800938e: bf00 nop + 8009390: 3710 adds r7, #16 + 8009392: 46bd mov sp, r7 + 8009394: bd80 pop {r7, pc} + 8009396: bf00 nop + 8009398: 20000124 .word 0x20000124 + +0800939c : + + + +//Print string on screen +void ssd1306_print_next(char *p_str, uint8_t inv) +{ + 800939c: b580 push {r7, lr} + 800939e: b082 sub sp, #8 + 80093a0: af00 add r7, sp, #0 + 80093a2: 6078 str r0, [r7, #4] + 80093a4: 460b mov r3, r1 + 80093a6: 70fb strb r3, [r7, #3] + while (*p_str) + 80093a8: e008 b.n 80093bc + { + ssd1306_char(*p_str++, inv); + 80093aa: 687b ldr r3, [r7, #4] + 80093ac: 1c5a adds r2, r3, #1 + 80093ae: 607a str r2, [r7, #4] + 80093b0: 781b ldrb r3, [r3, #0] + 80093b2: 78fa ldrb r2, [r7, #3] + 80093b4: 4611 mov r1, r2 + 80093b6: 4618 mov r0, r3 + 80093b8: f7ff ff2e bl 8009218 + while (*p_str) + 80093bc: 687b ldr r3, [r7, #4] + 80093be: 781b ldrb r3, [r3, #0] + 80093c0: 2b00 cmp r3, #0 + 80093c2: d1f2 bne.n 80093aa + } +} + 80093c4: bf00 nop + 80093c6: 3708 adds r7, #8 + 80093c8: 46bd mov sp, r7 + 80093ca: bd80 pop {r7, pc} + +080093cc : + + + +//Show bitmap +void ssd1306_bitmap(const uint8_t arr[]) +{ + 80093cc: b480 push {r7} + 80093ce: b085 sub sp, #20 + 80093d0: af00 add r7, sp, #0 + 80093d2: 6078 str r0, [r7, #4] + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + 80093d4: 2300 movs r3, #0 + 80093d6: 81fb strh r3, [r7, #14] + 80093d8: e009 b.n 80093ee + { + screen_buf[i] = arr[i]; + 80093da: 89fb ldrh r3, [r7, #14] + 80093dc: 687a ldr r2, [r7, #4] + 80093de: 441a add r2, r3 + 80093e0: 89fb ldrh r3, [r7, #14] + 80093e2: 7811 ldrb r1, [r2, #0] + 80093e4: 4a06 ldr r2, [pc, #24] ; (8009400 ) + 80093e6: 54d1 strb r1, [r2, r3] + for (uint16_t i = 0; i < LCD_SIZE_BYTES; i++) + 80093e8: 89fb ldrh r3, [r7, #14] + 80093ea: 3301 adds r3, #1 + 80093ec: 81fb strh r3, [r7, #14] + 80093ee: 89fb ldrh r3, [r7, #14] + 80093f0: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80093f4: d3f1 bcc.n 80093da + } +} + 80093f6: bf00 nop + 80093f8: 3714 adds r7, #20 + 80093fa: 46bd mov sp, r7 + 80093fc: bc80 pop {r7} + 80093fe: 4770 bx lr + 8009400: 20000934 .word 0x20000934 + +08009404 : + + + +//Print byte on screen (debug function) +void ssd1306_print_byte(uint8_t row, uint8_t col, uint8_t *p_byte, uint8_t amount) +{ + 8009404: b580 push {r7, lr} + 8009406: b082 sub sp, #8 + 8009408: af00 add r7, sp, #0 + 800940a: 603a str r2, [r7, #0] + 800940c: 461a mov r2, r3 + 800940e: 4603 mov r3, r0 + 8009410: 71fb strb r3, [r7, #7] + 8009412: 460b mov r3, r1 + 8009414: 71bb strb r3, [r7, #6] + 8009416: 4613 mov r3, r2 + 8009418: 717b strb r3, [r7, #5] + ssd1306_pos(row, col); + 800941a: 79ba ldrb r2, [r7, #6] + 800941c: 79fb ldrb r3, [r7, #7] + 800941e: 4611 mov r1, r2 + 8009420: 4618 mov r0, r3 + 8009422: f7ff fed7 bl 80091d4 + + while (amount--) + 8009426: e00b b.n 8009440 + { + screen_buf[buf_pos++] = *p_byte++; + 8009428: 683b ldr r3, [r7, #0] + 800942a: 1c5a adds r2, r3, #1 + 800942c: 603a str r2, [r7, #0] + 800942e: 4a09 ldr r2, [pc, #36] ; (8009454 ) + 8009430: 8812 ldrh r2, [r2, #0] + 8009432: 1c51 adds r1, r2, #1 + 8009434: b288 uxth r0, r1 + 8009436: 4907 ldr r1, [pc, #28] ; (8009454 ) + 8009438: 8008 strh r0, [r1, #0] + 800943a: 7819 ldrb r1, [r3, #0] + 800943c: 4b06 ldr r3, [pc, #24] ; (8009458 ) + 800943e: 5499 strb r1, [r3, r2] + while (amount--) + 8009440: 797b ldrb r3, [r7, #5] + 8009442: 1e5a subs r2, r3, #1 + 8009444: 717a strb r2, [r7, #5] + 8009446: 2b00 cmp r3, #0 + 8009448: d1ee bne.n 8009428 + } +} + 800944a: bf00 nop + 800944c: 3708 adds r7, #8 + 800944e: 46bd mov sp, r7 + 8009450: bd80 pop {r7, pc} + 8009452: bf00 nop + 8009454: 20000124 .word 0x20000124 + 8009458: 20000934 .word 0x20000934 + +0800945c : +{ + 800945c: b480 push {r7} + 800945e: b083 sub sp, #12 + 8009460: af00 add r7, sp, #0 + 8009462: 4603 mov r3, r0 + 8009464: 71fb strb r3, [r7, #7] + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ + 8009466: 79fb ldrb r3, [r7, #7] + 8009468: f003 031f and.w r3, r3, #31 + 800946c: 2201 movs r2, #1 + 800946e: fa02 f103 lsl.w r1, r2, r3 + 8009472: 4a05 ldr r2, [pc, #20] ; (8009488 ) + 8009474: f997 3007 ldrsb.w r3, [r7, #7] + 8009478: 095b lsrs r3, r3, #5 + 800947a: f842 1023 str.w r1, [r2, r3, lsl #2] +} + 800947e: bf00 nop + 8009480: 370c adds r7, #12 + 8009482: 46bd mov sp, r7 + 8009484: bc80 pop {r7} + 8009486: 4770 bx lr + 8009488: e000e100 .word 0xe000e100 + +0800948c : + + + +//Init all timers together +void timers_init(void) +{ + 800948c: b580 push {r7, lr} + 800948e: af00 add r7, sp, #0 + systick_init(); + 8009490: f000 f832 bl 80094f8 + timer1_init(); + 8009494: f000 f852 bl 800953c + timer2_init(); + 8009498: f000 f8a8 bl 80095ec + timer3_init(); + 800949c: f000 f8ec bl 8009678 +} + 80094a0: bf00 nop + 80094a2: bd80 pop {r7, pc} + +080094a4 : + + + +void make_a_beep(void) +{ + 80094a4: b580 push {r7, lr} + 80094a6: af00 add r7, sp, #0 + led_board_on(); + 80094a8: f7f8 fbb0 bl 8001c0c + timer2_start(); //in order to switch off led_board + 80094ac: f000 f8d4 bl 8009658 + + if (beep_mute == 0) + 80094b0: 4b03 ldr r3, [pc, #12] ; (80094c0 ) + 80094b2: 781b ldrb r3, [r3, #0] + 80094b4: 2b00 cmp r3, #0 + 80094b6: d101 bne.n 80094bc + { + timer3_start(); + 80094b8: f000 f92c bl 8009714 + } +} + 80094bc: bf00 nop + 80094be: bd80 pop {r7, pc} + 80094c0: 20000126 .word 0x20000126 + +080094c4 : + + + +void toggle_mute(void) +{ + 80094c4: b480 push {r7} + 80094c6: af00 add r7, sp, #0 + beep_mute ^= (uint8_t)1; + 80094c8: 4b05 ldr r3, [pc, #20] ; (80094e0 ) + 80094ca: 781b ldrb r3, [r3, #0] + 80094cc: f083 0301 eor.w r3, r3, #1 + 80094d0: b2da uxtb r2, r3 + 80094d2: 4b03 ldr r3, [pc, #12] ; (80094e0 ) + 80094d4: 701a strb r2, [r3, #0] +} + 80094d6: bf00 nop + 80094d8: 46bd mov sp, r7 + 80094da: bc80 pop {r7} + 80094dc: 4770 bx lr + 80094de: bf00 nop + 80094e0: 20000126 .word 0x20000126 + +080094e4 : + + + +uint8_t get_mute_flag(void) +{ + 80094e4: b480 push {r7} + 80094e6: af00 add r7, sp, #0 + return beep_mute; + 80094e8: 4b02 ldr r3, [pc, #8] ; (80094f4 ) + 80094ea: 781b ldrb r3, [r3, #0] +} + 80094ec: 4618 mov r0, r3 + 80094ee: 46bd mov sp, r7 + 80094f0: bc80 pop {r7} + 80094f2: 4770 bx lr + 80094f4: 20000126 .word 0x20000126 + +080094f8 : + + + +//SysTick timer init (tick every 1s to count uptime) +void systick_init(void) +{ + 80094f8: b480 push {r7} + 80094fa: af00 add r7, sp, #0 + SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk; //clock source = AHB/8 = 72MHz/8 = 9MHz + 80094fc: 4b0d ldr r3, [pc, #52] ; (8009534 ) + 80094fe: 681b ldr r3, [r3, #0] + 8009500: 4a0c ldr r2, [pc, #48] ; (8009534 ) + 8009502: f023 0304 bic.w r3, r3, #4 + 8009506: 6013 str r3, [r2, #0] + SysTick->LOAD = (uint32_t)8999999; //9000000Hz-1 + 8009508: 4b0a ldr r3, [pc, #40] ; (8009534 ) + 800950a: 4a0b ldr r2, [pc, #44] ; (8009538 ) + 800950c: 605a str r2, [r3, #4] + SysTick->VAL = 0; //reset counter value + 800950e: 4b09 ldr r3, [pc, #36] ; (8009534 ) + 8009510: 2200 movs r2, #0 + 8009512: 609a str r2, [r3, #8] + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; //enable interrupt + 8009514: 4b07 ldr r3, [pc, #28] ; (8009534 ) + 8009516: 681b ldr r3, [r3, #0] + 8009518: 4a06 ldr r2, [pc, #24] ; (8009534 ) + 800951a: f043 0302 orr.w r3, r3, #2 + 800951e: 6013 str r3, [r2, #0] + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; //enable counter + 8009520: 4b04 ldr r3, [pc, #16] ; (8009534 ) + 8009522: 681b ldr r3, [r3, #0] + 8009524: 4a03 ldr r2, [pc, #12] ; (8009534 ) + 8009526: f043 0301 orr.w r3, r3, #1 + 800952a: 6013 str r3, [r2, #0] +} + 800952c: bf00 nop + 800952e: 46bd mov sp, r7 + 8009530: bc80 pop {r7} + 8009532: 4770 bx lr + 8009534: e000e010 .word 0xe000e010 + 8009538: 0089543f .word 0x0089543f + +0800953c : + + + +//Timer1 init (time slot counter) +void timer1_init(void) +{ + 800953c: b580 push {r7, lr} + 800953e: af00 add r7, sp, #0 + RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; //enable timer 1 clock + 8009540: 4b16 ldr r3, [pc, #88] ; (800959c ) + 8009542: 699b ldr r3, [r3, #24] + 8009544: 4a15 ldr r2, [pc, #84] ; (800959c ) + 8009546: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 800954a: 6193 str r3, [r2, #24] + TIM1->PSC = (uint16_t)35999; // 72MHz/(35999+1)=2kHz + 800954c: 4b14 ldr r3, [pc, #80] ; (80095a0 ) + 800954e: f648 429f movw r2, #35999 ; 0x8c9f + 8009552: 851a strh r2, [r3, #40] ; 0x28 + TIM1->ARR = (uint16_t)199; // 2kHz/(199+1)=10Hz(100ms) + 8009554: 4b12 ldr r3, [pc, #72] ; (80095a0 ) + 8009556: 22c7 movs r2, #199 ; 0xc7 + 8009558: 859a strh r2, [r3, #44] ; 0x2c + TIM1->CR1 |= TIM_CR1_URS; //only overflow generates interrupt + 800955a: 4b11 ldr r3, [pc, #68] ; (80095a0 ) + 800955c: 881b ldrh r3, [r3, #0] + 800955e: b29b uxth r3, r3 + 8009560: 4a0f ldr r2, [pc, #60] ; (80095a0 ) + 8009562: f043 0304 orr.w r3, r3, #4 + 8009566: b29b uxth r3, r3 + 8009568: 8013 strh r3, [r2, #0] + TIM1->EGR = TIM_EGR_UG; //software update generation + 800956a: 4b0d ldr r3, [pc, #52] ; (80095a0 ) + 800956c: 2201 movs r2, #1 + 800956e: 829a strh r2, [r3, #20] + TIM1->SR &= ~TIM_SR_UIF; //clear update interrupt + 8009570: 4b0b ldr r3, [pc, #44] ; (80095a0 ) + 8009572: 8a1b ldrh r3, [r3, #16] + 8009574: b29b uxth r3, r3 + 8009576: 4a0a ldr r2, [pc, #40] ; (80095a0 ) + 8009578: f023 0301 bic.w r3, r3, #1 + 800957c: b29b uxth r3, r3 + 800957e: 8213 strh r3, [r2, #16] + TIM1->DIER |= TIM_DIER_UIE; //update interrupt enable + 8009580: 4b07 ldr r3, [pc, #28] ; (80095a0 ) + 8009582: 899b ldrh r3, [r3, #12] + 8009584: b29b uxth r3, r3 + 8009586: 4a06 ldr r2, [pc, #24] ; (80095a0 ) + 8009588: f043 0301 orr.w r3, r3, #1 + 800958c: b29b uxth r3, r3 + 800958e: 8193 strh r3, [r2, #12] + + NVIC_EnableIRQ(TIM1_UP_IRQn); //enable interrupt + 8009590: 2019 movs r0, #25 + 8009592: f7ff ff63 bl 800945c +} + 8009596: bf00 nop + 8009598: bd80 pop {r7, pc} + 800959a: bf00 nop + 800959c: 40021000 .word 0x40021000 + 80095a0: 40012c00 .word 0x40012c00 + +080095a4 : + + + +//Timer1 start +void timer1_start(void) +{ + 80095a4: b480 push {r7} + 80095a6: af00 add r7, sp, #0 + TIM1->CR1 |= TIM_CR1_CEN; //enable counter + 80095a8: 4b05 ldr r3, [pc, #20] ; (80095c0 ) + 80095aa: 881b ldrh r3, [r3, #0] + 80095ac: b29b uxth r3, r3 + 80095ae: 4a04 ldr r2, [pc, #16] ; (80095c0 ) + 80095b0: f043 0301 orr.w r3, r3, #1 + 80095b4: b29b uxth r3, r3 + 80095b6: 8013 strh r3, [r2, #0] +} + 80095b8: bf00 nop + 80095ba: 46bd mov sp, r7 + 80095bc: bc80 pop {r7} + 80095be: 4770 bx lr + 80095c0: 40012c00 .word 0x40012c00 + +080095c4 : + + + +//Timer1 stop and reload +void timer1_stop_reload(void) +{ + 80095c4: b480 push {r7} + 80095c6: af00 add r7, sp, #0 + TIM1->CR1 &= ~TIM_CR1_CEN; //disable counter + 80095c8: 4b07 ldr r3, [pc, #28] ; (80095e8 ) + 80095ca: 881b ldrh r3, [r3, #0] + 80095cc: b29b uxth r3, r3 + 80095ce: 4a06 ldr r2, [pc, #24] ; (80095e8 ) + 80095d0: f023 0301 bic.w r3, r3, #1 + 80095d4: b29b uxth r3, r3 + 80095d6: 8013 strh r3, [r2, #0] + TIM1->EGR = TIM_EGR_UG; //software update generation + 80095d8: 4b03 ldr r3, [pc, #12] ; (80095e8 ) + 80095da: 2201 movs r2, #1 + 80095dc: 829a strh r2, [r3, #20] +} + 80095de: bf00 nop + 80095e0: 46bd mov sp, r7 + 80095e2: bc80 pop {r7} + 80095e4: 4770 bx lr + 80095e6: bf00 nop + 80095e8: 40012c00 .word 0x40012c00 + +080095ec : + + + +//Timer 2 init (gating timer, the length of the "beep") +void timer2_init(void) +{ + 80095ec: b580 push {r7, lr} + 80095ee: af00 add r7, sp, #0 + RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; //enable timer clock + 80095f0: 4b10 ldr r3, [pc, #64] ; (8009634 ) + 80095f2: 69db ldr r3, [r3, #28] + 80095f4: 4a0f ldr r2, [pc, #60] ; (8009634 ) + 80095f6: f043 0301 orr.w r3, r3, #1 + 80095fa: 61d3 str r3, [r2, #28] + TIM2->PSC = (uint16_t)35999; //72MHz/(35999+1)=2kHz + 80095fc: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8009600: f648 429f movw r2, #35999 ; 0x8c9f + 8009604: 851a strh r2, [r3, #40] ; 0x28 + TIM2->ARR = (uint16_t)199; //2kHz/(199+1)=10Hz(100ms) + 8009606: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 800960a: 22c7 movs r2, #199 ; 0xc7 + 800960c: 859a strh r2, [r3, #44] ; 0x2c + TIM2->EGR = TIM_EGR_UG; //software update generation + 800960e: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8009612: 2201 movs r2, #1 + 8009614: 829a strh r2, [r3, #20] + TIM2->DIER |= TIM_DIER_UIE; //update interrupt enable + 8009616: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 800961a: 899b ldrh r3, [r3, #12] + 800961c: b29b uxth r3, r3 + 800961e: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8009622: f043 0301 orr.w r3, r3, #1 + 8009626: b29b uxth r3, r3 + 8009628: 8193 strh r3, [r2, #12] + + NVIC_EnableIRQ(TIM2_IRQn); + 800962a: 201c movs r0, #28 + 800962c: f7ff ff16 bl 800945c +} + 8009630: bf00 nop + 8009632: bd80 pop {r7, pc} + 8009634: 40021000 .word 0x40021000 + +08009638 : + + + +void timer2_stop(void) +{ + 8009638: b480 push {r7} + 800963a: af00 add r7, sp, #0 + TIM2->CR1 &= ~TIM_CR1_CEN; //stop gating timer + 800963c: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8009640: 881b ldrh r3, [r3, #0] + 8009642: b29b uxth r3, r3 + 8009644: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8009648: f023 0301 bic.w r3, r3, #1 + 800964c: b29b uxth r3, r3 + 800964e: 8013 strh r3, [r2, #0] +} + 8009650: bf00 nop + 8009652: 46bd mov sp, r7 + 8009654: bc80 pop {r7} + 8009656: 4770 bx lr + +08009658 : + + + +void timer2_start(void) +{ + 8009658: b480 push {r7} + 800965a: af00 add r7, sp, #0 + TIM2->CR1 |= TIM_CR1_CEN; //start gating timer + 800965c: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8009660: 881b ldrh r3, [r3, #0] + 8009662: b29b uxth r3, r3 + 8009664: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8009668: f043 0301 orr.w r3, r3, #1 + 800966c: b29b uxth r3, r3 + 800966e: 8013 strh r3, [r2, #0] +} + 8009670: bf00 nop + 8009672: 46bd mov sp, r7 + 8009674: bc80 pop {r7} + 8009676: 4770 bx lr + +08009678 : + + + +//Timer 3 init (pwm timer, the frequency of the "beep") +void timer3_init(void) +{ + 8009678: b480 push {r7} + 800967a: af00 add r7, sp, #0 + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; //enable timer clock + 800967c: 4b19 ldr r3, [pc, #100] ; (80096e4 ) + 800967e: 69db ldr r3, [r3, #28] + 8009680: 4a18 ldr r2, [pc, #96] ; (80096e4 ) + 8009682: f043 0302 orr.w r3, r3, #2 + 8009686: 61d3 str r3, [r2, #28] + TIM3->PSC = (uint16_t)8999; //72MHz/(8999+1)=8kHz + 8009688: 4b17 ldr r3, [pc, #92] ; (80096e8 ) + 800968a: f242 3227 movw r2, #8999 ; 0x2327 + 800968e: 851a strh r2, [r3, #40] ; 0x28 + TIM3->ARR = (uint16_t)3; //8kHz/(3+1)=2kHz + 8009690: 4b15 ldr r3, [pc, #84] ; (80096e8 ) + 8009692: 2203 movs r2, #3 + 8009694: 859a strh r2, [r3, #44] ; 0x2c + TIM3->CCR2 = (uint16_t)2; //duty cycle 2/(3+1)=0.5 + 8009696: 4b14 ldr r3, [pc, #80] ; (80096e8 ) + 8009698: 2202 movs r2, #2 + 800969a: 871a strh r2, [r3, #56] ; 0x38 + TIM3->CCMR1 |= TIM_CCMR1_OC2M_2; //PWM mode 2 + 800969c: 4b12 ldr r3, [pc, #72] ; (80096e8 ) + 800969e: 8b1b ldrh r3, [r3, #24] + 80096a0: b29b uxth r3, r3 + 80096a2: 4a11 ldr r2, [pc, #68] ; (80096e8 ) + 80096a4: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80096a8: b29b uxth r3, r3 + 80096aa: 8313 strh r3, [r2, #24] + TIM3->CCMR1 |= TIM_CCMR1_OC2M_1; + 80096ac: 4b0e ldr r3, [pc, #56] ; (80096e8 ) + 80096ae: 8b1b ldrh r3, [r3, #24] + 80096b0: b29b uxth r3, r3 + 80096b2: 4a0d ldr r2, [pc, #52] ; (80096e8 ) + 80096b4: f443 5300 orr.w r3, r3, #8192 ; 0x2000 + 80096b8: b29b uxth r3, r3 + 80096ba: 8313 strh r3, [r2, #24] + TIM3->CCMR1 |= TIM_CCMR1_OC2M_0; + 80096bc: 4b0a ldr r3, [pc, #40] ; (80096e8 ) + 80096be: 8b1b ldrh r3, [r3, #24] + 80096c0: b29b uxth r3, r3 + 80096c2: 4a09 ldr r2, [pc, #36] ; (80096e8 ) + 80096c4: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 80096c8: b29b uxth r3, r3 + 80096ca: 8313 strh r3, [r2, #24] + TIM3->CCER |= TIM_CCER_CC2E; //CH2 output enable + 80096cc: 4b06 ldr r3, [pc, #24] ; (80096e8 ) + 80096ce: 8c1b ldrh r3, [r3, #32] + 80096d0: b29b uxth r3, r3 + 80096d2: 4a05 ldr r2, [pc, #20] ; (80096e8 ) + 80096d4: f043 0310 orr.w r3, r3, #16 + 80096d8: b29b uxth r3, r3 + 80096da: 8413 strh r3, [r2, #32] +} + 80096dc: bf00 nop + 80096de: 46bd mov sp, r7 + 80096e0: bc80 pop {r7} + 80096e2: 4770 bx lr + 80096e4: 40021000 .word 0x40021000 + 80096e8: 40000400 .word 0x40000400 + +080096ec : + + + +void timer3_stop(void) +{ + 80096ec: b480 push {r7} + 80096ee: af00 add r7, sp, #0 + TIM3->CR1 &= ~TIM_CR1_CEN; //disable PWM timer + 80096f0: 4b07 ldr r3, [pc, #28] ; (8009710 ) + 80096f2: 881b ldrh r3, [r3, #0] + 80096f4: b29b uxth r3, r3 + 80096f6: 4a06 ldr r2, [pc, #24] ; (8009710 ) + 80096f8: f023 0301 bic.w r3, r3, #1 + 80096fc: b29b uxth r3, r3 + 80096fe: 8013 strh r3, [r2, #0] + TIM3->CNT = 0; //force output low + 8009700: 4b03 ldr r3, [pc, #12] ; (8009710 ) + 8009702: 2200 movs r2, #0 + 8009704: 849a strh r2, [r3, #36] ; 0x24 +} + 8009706: bf00 nop + 8009708: 46bd mov sp, r7 + 800970a: bc80 pop {r7} + 800970c: 4770 bx lr + 800970e: bf00 nop + 8009710: 40000400 .word 0x40000400 + +08009714 : + + + +void timer3_start(void) +{ + 8009714: b480 push {r7} + 8009716: af00 add r7, sp, #0 + TIM3->CR1 |= TIM_CR1_CEN; //enable PWM timer + 8009718: 4b05 ldr r3, [pc, #20] ; (8009730 ) + 800971a: 881b ldrh r3, [r3, #0] + 800971c: b29b uxth r3, r3 + 800971e: 4a04 ldr r2, [pc, #16] ; (8009730 ) + 8009720: f043 0301 orr.w r3, r3, #1 + 8009724: b29b uxth r3, r3 + 8009726: 8013 strh r3, [r2, #0] +} + 8009728: bf00 nop + 800972a: 46bd mov sp, r7 + 800972c: bc80 pop {r7} + 800972e: 4770 bx lr + 8009730: 40000400 .word 0x40000400 + +08009734 : +{ + 8009734: b480 push {r7} + 8009736: b083 sub sp, #12 + 8009738: af00 add r7, sp, #0 + 800973a: 4603 mov r3, r0 + 800973c: 71fb strb r3, [r7, #7] + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ + 800973e: 79fb ldrb r3, [r7, #7] + 8009740: f003 031f and.w r3, r3, #31 + 8009744: 2201 movs r2, #1 + 8009746: fa02 f103 lsl.w r1, r2, r3 + 800974a: 4a05 ldr r2, [pc, #20] ; (8009760 ) + 800974c: f997 3007 ldrsb.w r3, [r7, #7] + 8009750: 095b lsrs r3, r3, #5 + 8009752: f842 1023 str.w r1, [r2, r3, lsl #2] +} + 8009756: bf00 nop + 8009758: 370c adds r7, #12 + 800975a: 46bd mov sp, r7 + 800975c: bc80 pop {r7} + 800975e: 4770 bx lr + 8009760: e000e100 .word 0xe000e100 + +08009764 : + + + +//UART Init +void uart_dma_init(void) +{ + 8009764: b580 push {r7, lr} + 8009766: af00 add r7, sp, #0 + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; //ENABLE usart clock + 8009768: 4b2c ldr r3, [pc, #176] ; (800981c ) + 800976a: 699b ldr r3, [r3, #24] + 800976c: 4a2b ldr r2, [pc, #172] ; (800981c ) + 800976e: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8009772: 6193 str r3, [r2, #24] + + USART1->BRR = 0x1D4C; //9600 bod + 8009774: 4b2a ldr r3, [pc, #168] ; (8009820 ) + 8009776: f641 524c movw r2, #7500 ; 0x1d4c + 800977a: 811a strh r2, [r3, #8] + USART1->CR1 |= USART_CR1_TE; //enable tx + 800977c: 4b28 ldr r3, [pc, #160] ; (8009820 ) + 800977e: 899b ldrh r3, [r3, #12] + 8009780: b29b uxth r3, r3 + 8009782: 4a27 ldr r2, [pc, #156] ; (8009820 ) + 8009784: f043 0308 orr.w r3, r3, #8 + 8009788: b29b uxth r3, r3 + 800978a: 8193 strh r3, [r2, #12] + USART1->CR1 |= USART_CR1_RE; //enable rx + 800978c: 4b24 ldr r3, [pc, #144] ; (8009820 ) + 800978e: 899b ldrh r3, [r3, #12] + 8009790: b29b uxth r3, r3 + 8009792: 4a23 ldr r2, [pc, #140] ; (8009820 ) + 8009794: f043 0304 orr.w r3, r3, #4 + 8009798: b29b uxth r3, r3 + 800979a: 8193 strh r3, [r2, #12] + USART1->CR1 |= USART_CR1_UE; //uart enable + 800979c: 4b20 ldr r3, [pc, #128] ; (8009820 ) + 800979e: 899b ldrh r3, [r3, #12] + 80097a0: b29b uxth r3, r3 + 80097a2: 4a1f ldr r2, [pc, #124] ; (8009820 ) + 80097a4: f443 5300 orr.w r3, r3, #8192 ; 0x2000 + 80097a8: b29b uxth r3, r3 + 80097aa: 8193 strh r3, [r2, #12] + + USART1->CR3 |= USART_CR3_DMAR; //enable DMA mode USART + 80097ac: 4b1c ldr r3, [pc, #112] ; (8009820 ) + 80097ae: 8a9b ldrh r3, [r3, #20] + 80097b0: b29b uxth r3, r3 + 80097b2: 4a1b ldr r2, [pc, #108] ; (8009820 ) + 80097b4: f043 0340 orr.w r3, r3, #64 ; 0x40 + 80097b8: b29b uxth r3, r3 + 80097ba: 8293 strh r3, [r2, #20] + RCC->AHBENR |= RCC_AHBENR_DMA1EN; //enable dma1 clock + 80097bc: 4b17 ldr r3, [pc, #92] ; (800981c ) + 80097be: 695b ldr r3, [r3, #20] + 80097c0: 4a16 ldr r2, [pc, #88] ; (800981c ) + 80097c2: f043 0301 orr.w r3, r3, #1 + 80097c6: 6153 str r3, [r2, #20] + + DMA1_Channel5->CPAR = (uint32_t)(&(USART1->DR)); //transfer source + 80097c8: 4b16 ldr r3, [pc, #88] ; (8009824 ) + 80097ca: 4a17 ldr r2, [pc, #92] ; (8009828 ) + 80097cc: 609a str r2, [r3, #8] + DMA1_Channel5->CMAR = (uint32_t)(&uart_buffer[0]); //transfer destination + 80097ce: 4b15 ldr r3, [pc, #84] ; (8009824 ) + 80097d0: 4a16 ldr r2, [pc, #88] ; (800982c ) + 80097d2: 60da str r2, [r3, #12] + DMA1_Channel5->CNDTR = UART_BUF_LEN; //bytes amount to receive + 80097d4: 4b13 ldr r3, [pc, #76] ; (8009824 ) + 80097d6: f44f 6280 mov.w r2, #1024 ; 0x400 + 80097da: 605a str r2, [r3, #4] + + DMA1_Channel5->CCR |= DMA_CCR5_MINC; //enable memory increment + 80097dc: 4b11 ldr r3, [pc, #68] ; (8009824 ) + 80097de: 681b ldr r3, [r3, #0] + 80097e0: 4a10 ldr r2, [pc, #64] ; (8009824 ) + 80097e2: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80097e6: 6013 str r3, [r2, #0] + DMA1_Channel5->CCR |= DMA_CCR5_TCIE; //enable transfer complete interrupt + 80097e8: 4b0e ldr r3, [pc, #56] ; (8009824 ) + 80097ea: 681b ldr r3, [r3, #0] + 80097ec: 4a0d ldr r2, [pc, #52] ; (8009824 ) + 80097ee: f043 0302 orr.w r3, r3, #2 + 80097f2: 6013 str r3, [r2, #0] + DMA1_Channel5->CCR |= DMA_CCR5_EN; //enable channel + 80097f4: 4b0b ldr r3, [pc, #44] ; (8009824 ) + 80097f6: 681b ldr r3, [r3, #0] + 80097f8: 4a0a ldr r2, [pc, #40] ; (8009824 ) + 80097fa: f043 0301 orr.w r3, r3, #1 + 80097fe: 6013 str r3, [r2, #0] + + NVIC_EnableIRQ(DMA1_Channel5_IRQn); //enable interrupts + 8009800: 200f movs r0, #15 + 8009802: f7ff ff97 bl 8009734 + DMA1->IFCR = DMA_IFCR_CGIF5; //clear all interrupt flags for DMA channel 5 + 8009806: 4b0a ldr r3, [pc, #40] ; (8009830 ) + 8009808: f44f 3280 mov.w r2, #65536 ; 0x10000 + 800980c: 605a str r2, [r3, #4] + + backup_buf = get_nmea_buf(); + 800980e: f7f8 ff0b bl 8002628 + 8009812: 4602 mov r2, r0 + 8009814: 4b07 ldr r3, [pc, #28] ; (8009834 ) + 8009816: 601a str r2, [r3, #0] +} + 8009818: bf00 nop + 800981a: bd80 pop {r7, pc} + 800981c: 40021000 .word 0x40021000 + 8009820: 40013800 .word 0x40013800 + 8009824: 40020058 .word 0x40020058 + 8009828: 40013804 .word 0x40013804 + 800982c: 20000d38 .word 0x20000d38 + 8009830: 40020000 .word 0x40020000 + 8009834: 20000d34 .word 0x20000d34 + +08009838 : + + + +//Stop UART DMA +void uart_dma_stop(void) +{ + 8009838: b480 push {r7} + 800983a: af00 add r7, sp, #0 + DMA1_Channel5->CCR &= ~DMA_CCR5_EN; //disable channel + 800983c: 4b04 ldr r3, [pc, #16] ; (8009850 ) + 800983e: 681b ldr r3, [r3, #0] + 8009840: 4a03 ldr r2, [pc, #12] ; (8009850 ) + 8009842: f023 0301 bic.w r3, r3, #1 + 8009846: 6013 str r3, [r2, #0] +} + 8009848: bf00 nop + 800984a: 46bd mov sp, r7 + 800984c: bc80 pop {r7} + 800984e: 4770 bx lr + 8009850: 40020058 .word 0x40020058 + +08009854 : + + + +//Restart UART DMA +void uart_dma_restart(void) +{ + 8009854: b480 push {r7} + 8009856: af00 add r7, sp, #0 + DMA1_Channel5->CNDTR = UART_BUF_LEN; //reload bytes amount to receive + 8009858: 4b06 ldr r3, [pc, #24] ; (8009874 ) + 800985a: f44f 6280 mov.w r2, #1024 ; 0x400 + 800985e: 605a str r2, [r3, #4] + DMA1_Channel5->CCR |= DMA_CCR5_EN; //enable channel + 8009860: 4b04 ldr r3, [pc, #16] ; (8009874 ) + 8009862: 681b ldr r3, [r3, #0] + 8009864: 4a03 ldr r2, [pc, #12] ; (8009874 ) + 8009866: f043 0301 orr.w r3, r3, #1 + 800986a: 6013 str r3, [r2, #0] +} + 800986c: bf00 nop + 800986e: 46bd mov sp, r7 + 8009870: bc80 pop {r7} + 8009872: 4770 bx lr + 8009874: 40020058 .word 0x40020058 + +08009878 : + + + +//Backup uart buffer and then clear it +void backup_and_clear_uart_buffer(void) +{ + 8009878: b480 push {r7} + 800987a: b083 sub sp, #12 + 800987c: af00 add r7, sp, #0 + for (uint16_t i = 0; i < UART_BUF_LEN; i++) //copy received data to buffer and clear uart_buffer + 800987e: 2300 movs r3, #0 + 8009880: 80fb strh r3, [r7, #6] + 8009882: e00e b.n 80098a2 + { + backup_buf[i] = uart_buffer[i]; + 8009884: 88fa ldrh r2, [r7, #6] + 8009886: 4b0b ldr r3, [pc, #44] ; (80098b4 ) + 8009888: 6819 ldr r1, [r3, #0] + 800988a: 88fb ldrh r3, [r7, #6] + 800988c: 440b add r3, r1 + 800988e: 490a ldr r1, [pc, #40] ; (80098b8 ) + 8009890: 5c8a ldrb r2, [r1, r2] + 8009892: 701a strb r2, [r3, #0] + uart_buffer[i] = 0; + 8009894: 88fb ldrh r3, [r7, #6] + 8009896: 4a08 ldr r2, [pc, #32] ; (80098b8 ) + 8009898: 2100 movs r1, #0 + 800989a: 54d1 strb r1, [r2, r3] + for (uint16_t i = 0; i < UART_BUF_LEN; i++) //copy received data to buffer and clear uart_buffer + 800989c: 88fb ldrh r3, [r7, #6] + 800989e: 3301 adds r3, #1 + 80098a0: 80fb strh r3, [r7, #6] + 80098a2: 88fb ldrh r3, [r7, #6] + 80098a4: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80098a8: d3ec bcc.n 8009884 + } +} + 80098aa: bf00 nop + 80098ac: 370c adds r7, #12 + 80098ae: 46bd mov sp, r7 + 80098b0: bc80 pop {r7} + 80098b2: 4770 bx lr + 80098b4: 20000d34 .word 0x20000d34 + 80098b8: 20000d38 .word 0x20000d38 + +080098bc : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 80098bc: 480d ldr r0, [pc, #52] ; (80098f4 ) + mov sp, r0 /* set stack pointer */ + 80098be: 4685 mov sp, r0 +/* Call the clock system intitialization function.*/ + bl SystemInit + 80098c0: f7f7 fc74 bl 80011ac + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 80098c4: 480c ldr r0, [pc, #48] ; (80098f8 ) + ldr r1, =_edata + 80098c6: 490d ldr r1, [pc, #52] ; (80098fc ) + ldr r2, =_sidata + 80098c8: 4a0d ldr r2, [pc, #52] ; (8009900 ) + movs r3, #0 + 80098ca: 2300 movs r3, #0 + b LoopCopyDataInit + 80098cc: e002 b.n 80098d4 + +080098ce : + +CopyDataInit: + ldr r4, [r2, r3] + 80098ce: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 80098d0: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 80098d2: 3304 adds r3, #4 + +080098d4 : + +LoopCopyDataInit: + adds r4, r0, r3 + 80098d4: 18c4 adds r4, r0, r3 + cmp r4, r1 + 80098d6: 428c cmp r4, r1 + bcc CopyDataInit + 80098d8: d3f9 bcc.n 80098ce + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 80098da: 4a0a ldr r2, [pc, #40] ; (8009904 ) + ldr r4, =_ebss + 80098dc: 4c0a ldr r4, [pc, #40] ; (8009908 ) + movs r3, #0 + 80098de: 2300 movs r3, #0 + b LoopFillZerobss + 80098e0: e001 b.n 80098e6 + +080098e2 : + +FillZerobss: + str r3, [r2] + 80098e2: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 80098e4: 3204 adds r2, #4 + +080098e6 : + +LoopFillZerobss: + cmp r2, r4 + 80098e6: 42a2 cmp r2, r4 + bcc FillZerobss + 80098e8: d3fb bcc.n 80098e2 + +/* Call static constructors */ + bl __libc_init_array + 80098ea: f000 f811 bl 8009910 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 80098ee: f7fa f8c3 bl 8003a78
+ +080098f2 : + +LoopForever: + b LoopForever + 80098f2: e7fe b.n 80098f2 + ldr r0, =_estack + 80098f4: 20005000 .word 0x20005000 + ldr r0, =_sdata + 80098f8: 20000000 .word 0x20000000 + ldr r1, =_edata + 80098fc: 200000c8 .word 0x200000c8 + ldr r2, =_sidata + 8009900: 0800e7c0 .word 0x0800e7c0 + ldr r2, =_sbss + 8009904: 200000c8 .word 0x200000c8 + ldr r4, =_ebss + 8009908: 20001138 .word 0x20001138 + +0800990c : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 800990c: e7fe b.n 800990c + ... + +08009910 <__libc_init_array>: + 8009910: b570 push {r4, r5, r6, lr} + 8009912: 2500 movs r5, #0 + 8009914: 4e0c ldr r6, [pc, #48] ; (8009948 <__libc_init_array+0x38>) + 8009916: 4c0d ldr r4, [pc, #52] ; (800994c <__libc_init_array+0x3c>) + 8009918: 1ba4 subs r4, r4, r6 + 800991a: 10a4 asrs r4, r4, #2 + 800991c: 42a5 cmp r5, r4 + 800991e: d109 bne.n 8009934 <__libc_init_array+0x24> + 8009920: f003 f84c bl 800c9bc <_init> + 8009924: 2500 movs r5, #0 + 8009926: 4e0a ldr r6, [pc, #40] ; (8009950 <__libc_init_array+0x40>) + 8009928: 4c0a ldr r4, [pc, #40] ; (8009954 <__libc_init_array+0x44>) + 800992a: 1ba4 subs r4, r4, r6 + 800992c: 10a4 asrs r4, r4, #2 + 800992e: 42a5 cmp r5, r4 + 8009930: d105 bne.n 800993e <__libc_init_array+0x2e> + 8009932: bd70 pop {r4, r5, r6, pc} + 8009934: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 8009938: 4798 blx r3 + 800993a: 3501 adds r5, #1 + 800993c: e7ee b.n 800991c <__libc_init_array+0xc> + 800993e: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 8009942: 4798 blx r3 + 8009944: 3501 adds r5, #1 + 8009946: e7f2 b.n 800992e <__libc_init_array+0x1e> + 8009948: 0800e7b8 .word 0x0800e7b8 + 800994c: 0800e7b8 .word 0x0800e7b8 + 8009950: 0800e7b8 .word 0x0800e7b8 + 8009954: 0800e7bc .word 0x0800e7bc + +08009958 : + 8009958: b510 push {r4, lr} + 800995a: 1e43 subs r3, r0, #1 + 800995c: 440a add r2, r1 + 800995e: 4291 cmp r1, r2 + 8009960: d100 bne.n 8009964 + 8009962: bd10 pop {r4, pc} + 8009964: f811 4b01 ldrb.w r4, [r1], #1 + 8009968: f803 4f01 strb.w r4, [r3, #1]! + 800996c: e7f7 b.n 800995e + +0800996e : + 800996e: 4603 mov r3, r0 + 8009970: 4402 add r2, r0 + 8009972: 4293 cmp r3, r2 + 8009974: d100 bne.n 8009978 + 8009976: 4770 bx lr + 8009978: f803 1b01 strb.w r1, [r3], #1 + 800997c: e7f9 b.n 8009972 + ... + +08009980 : + 8009980: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8009984: 4bb6 ldr r3, [pc, #728] ; (8009c60 ) + 8009986: f021 4600 bic.w r6, r1, #2147483648 ; 0x80000000 + 800998a: 429e cmp r6, r3 + 800998c: 4604 mov r4, r0 + 800998e: 460d mov r5, r1 + 8009990: 468b mov fp, r1 + 8009992: dd17 ble.n 80099c4 + 8009994: 4bb3 ldr r3, [pc, #716] ; (8009c64 ) + 8009996: 429e cmp r6, r3 + 8009998: dc01 bgt.n 800999e + 800999a: d109 bne.n 80099b0 + 800999c: b140 cbz r0, 80099b0 + 800999e: 4622 mov r2, r4 + 80099a0: 462b mov r3, r5 + 80099a2: 4620 mov r0, r4 + 80099a4: 4629 mov r1, r5 + 80099a6: f7f6 fbe9 bl 800017c <__adddf3> + 80099aa: 4604 mov r4, r0 + 80099ac: 460d mov r5, r1 + 80099ae: e005 b.n 80099bc + 80099b0: f1bb 0f00 cmp.w fp, #0 + 80099b4: 4cac ldr r4, [pc, #688] ; (8009c68 ) + 80099b6: f340 8121 ble.w 8009bfc + 80099ba: 4dac ldr r5, [pc, #688] ; (8009c6c ) + 80099bc: 4620 mov r0, r4 + 80099be: 4629 mov r1, r5 + 80099c0: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80099c4: 4baa ldr r3, [pc, #680] ; (8009c70 ) + 80099c6: 429e cmp r6, r3 + 80099c8: dc11 bgt.n 80099ee + 80099ca: f1a3 73de sub.w r3, r3, #29097984 ; 0x1bc0000 + 80099ce: 429e cmp r6, r3 + 80099d0: dc0a bgt.n 80099e8 + 80099d2: a38b add r3, pc, #556 ; (adr r3, 8009c00 ) + 80099d4: e9d3 2300 ldrd r2, r3, [r3] + 80099d8: f7f6 fbd0 bl 800017c <__adddf3> + 80099dc: 2200 movs r2, #0 + 80099de: 4ba5 ldr r3, [pc, #660] ; (8009c74 ) + 80099e0: f7f7 f812 bl 8000a08 <__aeabi_dcmpgt> + 80099e4: 2800 cmp r0, #0 + 80099e6: d1e9 bne.n 80099bc + 80099e8: f04f 3aff mov.w sl, #4294967295 + 80099ec: e027 b.n 8009a3e + 80099ee: f000 f987 bl 8009d00 + 80099f2: 4ba1 ldr r3, [pc, #644] ; (8009c78 ) + 80099f4: 4604 mov r4, r0 + 80099f6: 429e cmp r6, r3 + 80099f8: 460d mov r5, r1 + 80099fa: f300 80b8 bgt.w 8009b6e + 80099fe: f5a3 2350 sub.w r3, r3, #851968 ; 0xd0000 + 8009a02: 429e cmp r6, r3 + 8009a04: f300 809c bgt.w 8009b40 + 8009a08: 4602 mov r2, r0 + 8009a0a: 460b mov r3, r1 + 8009a0c: f7f6 fbb6 bl 800017c <__adddf3> + 8009a10: 2200 movs r2, #0 + 8009a12: 4b98 ldr r3, [pc, #608] ; (8009c74 ) + 8009a14: f7f6 fbb0 bl 8000178 <__aeabi_dsub> + 8009a18: 2200 movs r2, #0 + 8009a1a: 4606 mov r6, r0 + 8009a1c: 460f mov r7, r1 + 8009a1e: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8009a22: 4620 mov r0, r4 + 8009a24: 4629 mov r1, r5 + 8009a26: f7f6 fba9 bl 800017c <__adddf3> + 8009a2a: 4602 mov r2, r0 + 8009a2c: 460b mov r3, r1 + 8009a2e: 4630 mov r0, r6 + 8009a30: 4639 mov r1, r7 + 8009a32: f7f6 fe83 bl 800073c <__aeabi_ddiv> + 8009a36: f04f 0a00 mov.w sl, #0 + 8009a3a: 4604 mov r4, r0 + 8009a3c: 460d mov r5, r1 + 8009a3e: 4622 mov r2, r4 + 8009a40: 462b mov r3, r5 + 8009a42: 4620 mov r0, r4 + 8009a44: 4629 mov r1, r5 + 8009a46: f7f6 fd4f bl 80004e8 <__aeabi_dmul> + 8009a4a: 4602 mov r2, r0 + 8009a4c: 460b mov r3, r1 + 8009a4e: 4680 mov r8, r0 + 8009a50: 4689 mov r9, r1 + 8009a52: f7f6 fd49 bl 80004e8 <__aeabi_dmul> + 8009a56: a36c add r3, pc, #432 ; (adr r3, 8009c08 ) + 8009a58: e9d3 2300 ldrd r2, r3, [r3] + 8009a5c: 4606 mov r6, r0 + 8009a5e: 460f mov r7, r1 + 8009a60: f7f6 fd42 bl 80004e8 <__aeabi_dmul> + 8009a64: a36a add r3, pc, #424 ; (adr r3, 8009c10 ) + 8009a66: e9d3 2300 ldrd r2, r3, [r3] + 8009a6a: f7f6 fb87 bl 800017c <__adddf3> + 8009a6e: 4632 mov r2, r6 + 8009a70: 463b mov r3, r7 + 8009a72: f7f6 fd39 bl 80004e8 <__aeabi_dmul> + 8009a76: a368 add r3, pc, #416 ; (adr r3, 8009c18 ) + 8009a78: e9d3 2300 ldrd r2, r3, [r3] + 8009a7c: f7f6 fb7e bl 800017c <__adddf3> + 8009a80: 4632 mov r2, r6 + 8009a82: 463b mov r3, r7 + 8009a84: f7f6 fd30 bl 80004e8 <__aeabi_dmul> + 8009a88: a365 add r3, pc, #404 ; (adr r3, 8009c20 ) + 8009a8a: e9d3 2300 ldrd r2, r3, [r3] + 8009a8e: f7f6 fb75 bl 800017c <__adddf3> + 8009a92: 4632 mov r2, r6 + 8009a94: 463b mov r3, r7 + 8009a96: f7f6 fd27 bl 80004e8 <__aeabi_dmul> + 8009a9a: a363 add r3, pc, #396 ; (adr r3, 8009c28 ) + 8009a9c: e9d3 2300 ldrd r2, r3, [r3] + 8009aa0: f7f6 fb6c bl 800017c <__adddf3> + 8009aa4: 4632 mov r2, r6 + 8009aa6: 463b mov r3, r7 + 8009aa8: f7f6 fd1e bl 80004e8 <__aeabi_dmul> + 8009aac: a360 add r3, pc, #384 ; (adr r3, 8009c30 ) + 8009aae: e9d3 2300 ldrd r2, r3, [r3] + 8009ab2: f7f6 fb63 bl 800017c <__adddf3> + 8009ab6: 4642 mov r2, r8 + 8009ab8: 464b mov r3, r9 + 8009aba: f7f6 fd15 bl 80004e8 <__aeabi_dmul> + 8009abe: a35e add r3, pc, #376 ; (adr r3, 8009c38 ) + 8009ac0: e9d3 2300 ldrd r2, r3, [r3] + 8009ac4: 4680 mov r8, r0 + 8009ac6: 4689 mov r9, r1 + 8009ac8: 4630 mov r0, r6 + 8009aca: 4639 mov r1, r7 + 8009acc: f7f6 fd0c bl 80004e8 <__aeabi_dmul> + 8009ad0: a35b add r3, pc, #364 ; (adr r3, 8009c40 ) + 8009ad2: e9d3 2300 ldrd r2, r3, [r3] + 8009ad6: f7f6 fb4f bl 8000178 <__aeabi_dsub> + 8009ada: 4632 mov r2, r6 + 8009adc: 463b mov r3, r7 + 8009ade: f7f6 fd03 bl 80004e8 <__aeabi_dmul> + 8009ae2: a359 add r3, pc, #356 ; (adr r3, 8009c48 ) + 8009ae4: e9d3 2300 ldrd r2, r3, [r3] + 8009ae8: f7f6 fb46 bl 8000178 <__aeabi_dsub> + 8009aec: 4632 mov r2, r6 + 8009aee: 463b mov r3, r7 + 8009af0: f7f6 fcfa bl 80004e8 <__aeabi_dmul> + 8009af4: a356 add r3, pc, #344 ; (adr r3, 8009c50 ) + 8009af6: e9d3 2300 ldrd r2, r3, [r3] + 8009afa: f7f6 fb3d bl 8000178 <__aeabi_dsub> + 8009afe: 4632 mov r2, r6 + 8009b00: 463b mov r3, r7 + 8009b02: f7f6 fcf1 bl 80004e8 <__aeabi_dmul> + 8009b06: a354 add r3, pc, #336 ; (adr r3, 8009c58 ) + 8009b08: e9d3 2300 ldrd r2, r3, [r3] + 8009b0c: f7f6 fb34 bl 8000178 <__aeabi_dsub> + 8009b10: 4632 mov r2, r6 + 8009b12: 463b mov r3, r7 + 8009b14: f7f6 fce8 bl 80004e8 <__aeabi_dmul> + 8009b18: 4602 mov r2, r0 + 8009b1a: 460b mov r3, r1 + 8009b1c: 4640 mov r0, r8 + 8009b1e: 4649 mov r1, r9 + 8009b20: f7f6 fb2c bl 800017c <__adddf3> + 8009b24: 4622 mov r2, r4 + 8009b26: 462b mov r3, r5 + 8009b28: f7f6 fcde bl 80004e8 <__aeabi_dmul> + 8009b2c: f1ba 3fff cmp.w sl, #4294967295 + 8009b30: 4602 mov r2, r0 + 8009b32: 460b mov r3, r1 + 8009b34: d144 bne.n 8009bc0 + 8009b36: 4620 mov r0, r4 + 8009b38: 4629 mov r1, r5 + 8009b3a: f7f6 fb1d bl 8000178 <__aeabi_dsub> + 8009b3e: e734 b.n 80099aa + 8009b40: 2200 movs r2, #0 + 8009b42: 4b4c ldr r3, [pc, #304] ; (8009c74 ) + 8009b44: f7f6 fb18 bl 8000178 <__aeabi_dsub> + 8009b48: 2200 movs r2, #0 + 8009b4a: 4606 mov r6, r0 + 8009b4c: 460f mov r7, r1 + 8009b4e: 4b49 ldr r3, [pc, #292] ; (8009c74 ) + 8009b50: 4620 mov r0, r4 + 8009b52: 4629 mov r1, r5 + 8009b54: f7f6 fb12 bl 800017c <__adddf3> + 8009b58: 4602 mov r2, r0 + 8009b5a: 460b mov r3, r1 + 8009b5c: 4630 mov r0, r6 + 8009b5e: 4639 mov r1, r7 + 8009b60: f7f6 fdec bl 800073c <__aeabi_ddiv> + 8009b64: f04f 0a01 mov.w sl, #1 + 8009b68: 4604 mov r4, r0 + 8009b6a: 460d mov r5, r1 + 8009b6c: e767 b.n 8009a3e + 8009b6e: 4b43 ldr r3, [pc, #268] ; (8009c7c ) + 8009b70: 429e cmp r6, r3 + 8009b72: dc1a bgt.n 8009baa + 8009b74: 2200 movs r2, #0 + 8009b76: 4b42 ldr r3, [pc, #264] ; (8009c80 ) + 8009b78: f7f6 fafe bl 8000178 <__aeabi_dsub> + 8009b7c: 2200 movs r2, #0 + 8009b7e: 4606 mov r6, r0 + 8009b80: 460f mov r7, r1 + 8009b82: 4b3f ldr r3, [pc, #252] ; (8009c80 ) + 8009b84: 4620 mov r0, r4 + 8009b86: 4629 mov r1, r5 + 8009b88: f7f6 fcae bl 80004e8 <__aeabi_dmul> + 8009b8c: 2200 movs r2, #0 + 8009b8e: 4b39 ldr r3, [pc, #228] ; (8009c74 ) + 8009b90: f7f6 faf4 bl 800017c <__adddf3> + 8009b94: 4602 mov r2, r0 + 8009b96: 460b mov r3, r1 + 8009b98: 4630 mov r0, r6 + 8009b9a: 4639 mov r1, r7 + 8009b9c: f7f6 fdce bl 800073c <__aeabi_ddiv> + 8009ba0: f04f 0a02 mov.w sl, #2 + 8009ba4: 4604 mov r4, r0 + 8009ba6: 460d mov r5, r1 + 8009ba8: e749 b.n 8009a3e + 8009baa: 4602 mov r2, r0 + 8009bac: 460b mov r3, r1 + 8009bae: 2000 movs r0, #0 + 8009bb0: 4934 ldr r1, [pc, #208] ; (8009c84 ) + 8009bb2: f7f6 fdc3 bl 800073c <__aeabi_ddiv> + 8009bb6: f04f 0a03 mov.w sl, #3 + 8009bba: 4604 mov r4, r0 + 8009bbc: 460d mov r5, r1 + 8009bbe: e73e b.n 8009a3e + 8009bc0: 4b31 ldr r3, [pc, #196] ; (8009c88 ) + 8009bc2: 4e32 ldr r6, [pc, #200] ; (8009c8c ) + 8009bc4: ea4f 0aca mov.w sl, sl, lsl #3 + 8009bc8: 4456 add r6, sl + 8009bca: 449a add sl, r3 + 8009bcc: e9da 2300 ldrd r2, r3, [sl] + 8009bd0: f7f6 fad2 bl 8000178 <__aeabi_dsub> + 8009bd4: 4622 mov r2, r4 + 8009bd6: 462b mov r3, r5 + 8009bd8: f7f6 face bl 8000178 <__aeabi_dsub> + 8009bdc: 4602 mov r2, r0 + 8009bde: 460b mov r3, r1 + 8009be0: e9d6 0100 ldrd r0, r1, [r6] + 8009be4: f7f6 fac8 bl 8000178 <__aeabi_dsub> + 8009be8: f1bb 0f00 cmp.w fp, #0 + 8009bec: 4604 mov r4, r0 + 8009bee: 460d mov r5, r1 + 8009bf0: f6bf aee4 bge.w 80099bc + 8009bf4: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8009bf8: 461d mov r5, r3 + 8009bfa: e6df b.n 80099bc + 8009bfc: 4d24 ldr r5, [pc, #144] ; (8009c90 ) + 8009bfe: e6dd b.n 80099bc + 8009c00: 8800759c .word 0x8800759c + 8009c04: 7e37e43c .word 0x7e37e43c + 8009c08: e322da11 .word 0xe322da11 + 8009c0c: 3f90ad3a .word 0x3f90ad3a + 8009c10: 24760deb .word 0x24760deb + 8009c14: 3fa97b4b .word 0x3fa97b4b + 8009c18: a0d03d51 .word 0xa0d03d51 + 8009c1c: 3fb10d66 .word 0x3fb10d66 + 8009c20: c54c206e .word 0xc54c206e + 8009c24: 3fb745cd .word 0x3fb745cd + 8009c28: 920083ff .word 0x920083ff + 8009c2c: 3fc24924 .word 0x3fc24924 + 8009c30: 5555550d .word 0x5555550d + 8009c34: 3fd55555 .word 0x3fd55555 + 8009c38: 2c6a6c2f .word 0x2c6a6c2f + 8009c3c: bfa2b444 .word 0xbfa2b444 + 8009c40: 52defd9a .word 0x52defd9a + 8009c44: 3fadde2d .word 0x3fadde2d + 8009c48: af749a6d .word 0xaf749a6d + 8009c4c: 3fb3b0f2 .word 0x3fb3b0f2 + 8009c50: fe231671 .word 0xfe231671 + 8009c54: 3fbc71c6 .word 0x3fbc71c6 + 8009c58: 9998ebc4 .word 0x9998ebc4 + 8009c5c: 3fc99999 .word 0x3fc99999 + 8009c60: 440fffff .word 0x440fffff + 8009c64: 7ff00000 .word 0x7ff00000 + 8009c68: 54442d18 .word 0x54442d18 + 8009c6c: 3ff921fb .word 0x3ff921fb + 8009c70: 3fdbffff .word 0x3fdbffff + 8009c74: 3ff00000 .word 0x3ff00000 + 8009c78: 3ff2ffff .word 0x3ff2ffff + 8009c7c: 40037fff .word 0x40037fff + 8009c80: 3ff80000 .word 0x3ff80000 + 8009c84: bff00000 .word 0xbff00000 + 8009c88: 0800e568 .word 0x0800e568 + 8009c8c: 0800e548 .word 0x0800e548 + 8009c90: bff921fb .word 0xbff921fb + +08009c94 : + 8009c94: b530 push {r4, r5, lr} + 8009c96: 4a18 ldr r2, [pc, #96] ; (8009cf8 ) + 8009c98: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 8009c9c: 4293 cmp r3, r2 + 8009c9e: b087 sub sp, #28 + 8009ca0: dc04 bgt.n 8009cac + 8009ca2: 2200 movs r2, #0 + 8009ca4: 2300 movs r3, #0 + 8009ca6: f001 fe6b bl 800b980 <__kernel_cos> + 8009caa: e006 b.n 8009cba + 8009cac: 4a13 ldr r2, [pc, #76] ; (8009cfc ) + 8009cae: 4293 cmp r3, r2 + 8009cb0: dd05 ble.n 8009cbe + 8009cb2: 4602 mov r2, r0 + 8009cb4: 460b mov r3, r1 + 8009cb6: f7f6 fa5f bl 8000178 <__aeabi_dsub> + 8009cba: b007 add sp, #28 + 8009cbc: bd30 pop {r4, r5, pc} + 8009cbe: aa02 add r2, sp, #8 + 8009cc0: f001 fbc2 bl 800b448 <__ieee754_rem_pio2> + 8009cc4: e9dd 2304 ldrd r2, r3, [sp, #16] + 8009cc8: f000 0403 and.w r4, r0, #3 + 8009ccc: 2c01 cmp r4, #1 + 8009cce: e9dd 0102 ldrd r0, r1, [sp, #8] + 8009cd2: d008 beq.n 8009ce6 + 8009cd4: 2c02 cmp r4, #2 + 8009cd6: d00c beq.n 8009cf2 + 8009cd8: 2c00 cmp r4, #0 + 8009cda: d0e4 beq.n 8009ca6 + 8009cdc: 2401 movs r4, #1 + 8009cde: 9400 str r4, [sp, #0] + 8009ce0: f002 fa56 bl 800c190 <__kernel_sin> + 8009ce4: e7e9 b.n 8009cba + 8009ce6: 9400 str r4, [sp, #0] + 8009ce8: f002 fa52 bl 800c190 <__kernel_sin> + 8009cec: f101 4100 add.w r1, r1, #2147483648 ; 0x80000000 + 8009cf0: e7e3 b.n 8009cba + 8009cf2: f001 fe45 bl 800b980 <__kernel_cos> + 8009cf6: e7f9 b.n 8009cec + 8009cf8: 3fe921fb .word 0x3fe921fb + 8009cfc: 7fefffff .word 0x7fefffff + +08009d00 : + 8009d00: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 8009d04: 4619 mov r1, r3 + 8009d06: 4770 bx lr + +08009d08 : + 8009d08: b530 push {r4, r5, lr} + 8009d0a: 4a1a ldr r2, [pc, #104] ; (8009d74 ) + 8009d0c: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 8009d10: 4293 cmp r3, r2 + 8009d12: b087 sub sp, #28 + 8009d14: dc06 bgt.n 8009d24 + 8009d16: 2300 movs r3, #0 + 8009d18: 2200 movs r2, #0 + 8009d1a: 9300 str r3, [sp, #0] + 8009d1c: 2300 movs r3, #0 + 8009d1e: f002 fa37 bl 800c190 <__kernel_sin> + 8009d22: e006 b.n 8009d32 + 8009d24: 4a14 ldr r2, [pc, #80] ; (8009d78 ) + 8009d26: 4293 cmp r3, r2 + 8009d28: dd05 ble.n 8009d36 + 8009d2a: 4602 mov r2, r0 + 8009d2c: 460b mov r3, r1 + 8009d2e: f7f6 fa23 bl 8000178 <__aeabi_dsub> + 8009d32: b007 add sp, #28 + 8009d34: bd30 pop {r4, r5, pc} + 8009d36: aa02 add r2, sp, #8 + 8009d38: f001 fb86 bl 800b448 <__ieee754_rem_pio2> + 8009d3c: e9dd 2304 ldrd r2, r3, [sp, #16] + 8009d40: f000 0403 and.w r4, r0, #3 + 8009d44: 2c01 cmp r4, #1 + 8009d46: e9dd 0102 ldrd r0, r1, [sp, #8] + 8009d4a: d005 beq.n 8009d58 + 8009d4c: 2c02 cmp r4, #2 + 8009d4e: d006 beq.n 8009d5e + 8009d50: b964 cbnz r4, 8009d6c + 8009d52: 2401 movs r4, #1 + 8009d54: 9400 str r4, [sp, #0] + 8009d56: e7e2 b.n 8009d1e + 8009d58: f001 fe12 bl 800b980 <__kernel_cos> + 8009d5c: e7e9 b.n 8009d32 + 8009d5e: 2401 movs r4, #1 + 8009d60: 9400 str r4, [sp, #0] + 8009d62: f002 fa15 bl 800c190 <__kernel_sin> + 8009d66: f101 4100 add.w r1, r1, #2147483648 ; 0x80000000 + 8009d6a: e7e2 b.n 8009d32 + 8009d6c: f001 fe08 bl 800b980 <__kernel_cos> + 8009d70: e7f9 b.n 8009d66 + 8009d72: bf00 nop + 8009d74: 3fe921fb .word 0x3fe921fb + 8009d78: 7fefffff .word 0x7fefffff + +08009d7c : + 8009d7c: b530 push {r4, r5, lr} + 8009d7e: 4a12 ldr r2, [pc, #72] ; (8009dc8 ) + 8009d80: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 8009d84: 4293 cmp r3, r2 + 8009d86: b087 sub sp, #28 + 8009d88: dc06 bgt.n 8009d98 + 8009d8a: 2301 movs r3, #1 + 8009d8c: 2200 movs r2, #0 + 8009d8e: 9300 str r3, [sp, #0] + 8009d90: 2300 movs r3, #0 + 8009d92: f002 fab5 bl 800c300 <__kernel_tan> + 8009d96: e006 b.n 8009da6 + 8009d98: 4a0c ldr r2, [pc, #48] ; (8009dcc ) + 8009d9a: 4293 cmp r3, r2 + 8009d9c: dd05 ble.n 8009daa + 8009d9e: 4602 mov r2, r0 + 8009da0: 460b mov r3, r1 + 8009da2: f7f6 f9e9 bl 8000178 <__aeabi_dsub> + 8009da6: b007 add sp, #28 + 8009da8: bd30 pop {r4, r5, pc} + 8009daa: aa02 add r2, sp, #8 + 8009dac: f001 fb4c bl 800b448 <__ieee754_rem_pio2> + 8009db0: e9dd 2304 ldrd r2, r3, [sp, #16] + 8009db4: 0040 lsls r0, r0, #1 + 8009db6: f000 0002 and.w r0, r0, #2 + 8009dba: f1c0 0001 rsb r0, r0, #1 + 8009dbe: 9000 str r0, [sp, #0] + 8009dc0: e9dd 0102 ldrd r0, r1, [sp, #8] + 8009dc4: e7e5 b.n 8009d92 + 8009dc6: bf00 nop + 8009dc8: 3fe921fb .word 0x3fe921fb + 8009dcc: 7fefffff .word 0x7fefffff + +08009dd0 : + 8009dd0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8009dd4: b08b sub sp, #44 ; 0x2c + 8009dd6: 4604 mov r4, r0 + 8009dd8: 460d mov r5, r1 + 8009dda: f000 fa79 bl 800a2d0 <__ieee754_asin> + 8009dde: f8df 8094 ldr.w r8, [pc, #148] ; 8009e74 + 8009de2: 4606 mov r6, r0 + 8009de4: f998 3000 ldrsb.w r3, [r8] + 8009de8: 460f mov r7, r1 + 8009dea: 3301 adds r3, #1 + 8009dec: d036 beq.n 8009e5c + 8009dee: 4622 mov r2, r4 + 8009df0: 462b mov r3, r5 + 8009df2: 4620 mov r0, r4 + 8009df4: 4629 mov r1, r5 + 8009df6: f7f6 fe11 bl 8000a1c <__aeabi_dcmpun> + 8009dfa: 4681 mov r9, r0 + 8009dfc: 2800 cmp r0, #0 + 8009dfe: d12d bne.n 8009e5c + 8009e00: 4620 mov r0, r4 + 8009e02: 4629 mov r1, r5 + 8009e04: f7ff ff7c bl 8009d00 + 8009e08: 2200 movs r2, #0 + 8009e0a: 4b17 ldr r3, [pc, #92] ; (8009e68 ) + 8009e0c: f7f6 fdfc bl 8000a08 <__aeabi_dcmpgt> + 8009e10: b320 cbz r0, 8009e5c + 8009e12: 2301 movs r3, #1 + 8009e14: 9300 str r3, [sp, #0] + 8009e16: 4b15 ldr r3, [pc, #84] ; (8009e6c ) + 8009e18: 4815 ldr r0, [pc, #84] ; (8009e70 ) + 8009e1a: 9301 str r3, [sp, #4] + 8009e1c: f8cd 9020 str.w r9, [sp, #32] + 8009e20: e9cd 4504 strd r4, r5, [sp, #16] + 8009e24: e9cd 4502 strd r4, r5, [sp, #8] + 8009e28: f002 fcb8 bl 800c79c + 8009e2c: f998 3000 ldrsb.w r3, [r8] + 8009e30: e9cd 0106 strd r0, r1, [sp, #24] + 8009e34: 2b02 cmp r3, #2 + 8009e36: d104 bne.n 8009e42 + 8009e38: f002 fdba bl 800c9b0 <__errno> + 8009e3c: 2321 movs r3, #33 ; 0x21 + 8009e3e: 6003 str r3, [r0, #0] + 8009e40: e004 b.n 8009e4c + 8009e42: 4668 mov r0, sp + 8009e44: f002 fca8 bl 800c798 + 8009e48: 2800 cmp r0, #0 + 8009e4a: d0f5 beq.n 8009e38 + 8009e4c: 9b08 ldr r3, [sp, #32] + 8009e4e: b11b cbz r3, 8009e58 + 8009e50: f002 fdae bl 800c9b0 <__errno> + 8009e54: 9b08 ldr r3, [sp, #32] + 8009e56: 6003 str r3, [r0, #0] + 8009e58: e9dd 6706 ldrd r6, r7, [sp, #24] + 8009e5c: 4630 mov r0, r6 + 8009e5e: 4639 mov r1, r7 + 8009e60: b00b add sp, #44 ; 0x2c + 8009e62: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8009e66: bf00 nop + 8009e68: 3ff00000 .word 0x3ff00000 + 8009e6c: 0800e588 .word 0x0800e588 + 8009e70: 0800e590 .word 0x0800e590 + 8009e74: 200000c4 .word 0x200000c4 + +08009e78 : + 8009e78: e92d 4370 stmdb sp!, {r4, r5, r6, r8, r9, lr} + 8009e7c: b08a sub sp, #40 ; 0x28 + 8009e7e: 4604 mov r4, r0 + 8009e80: 460d mov r5, r1 + 8009e82: f000 fc21 bl 800a6c8 <__ieee754_log> + 8009e86: 4b34 ldr r3, [pc, #208] ; (8009f58 ) + 8009e88: 4680 mov r8, r0 + 8009e8a: f993 6000 ldrsb.w r6, [r3] + 8009e8e: 4689 mov r9, r1 + 8009e90: 1c73 adds r3, r6, #1 + 8009e92: d05b beq.n 8009f4c + 8009e94: 4622 mov r2, r4 + 8009e96: 462b mov r3, r5 + 8009e98: 4620 mov r0, r4 + 8009e9a: 4629 mov r1, r5 + 8009e9c: f7f6 fdbe bl 8000a1c <__aeabi_dcmpun> + 8009ea0: 2800 cmp r0, #0 + 8009ea2: d153 bne.n 8009f4c + 8009ea4: 2200 movs r2, #0 + 8009ea6: 2300 movs r3, #0 + 8009ea8: 4620 mov r0, r4 + 8009eaa: 4629 mov r1, r5 + 8009eac: f7f6 fdac bl 8000a08 <__aeabi_dcmpgt> + 8009eb0: 2800 cmp r0, #0 + 8009eb2: d14b bne.n 8009f4c + 8009eb4: 4b29 ldr r3, [pc, #164] ; (8009f5c ) + 8009eb6: 9008 str r0, [sp, #32] + 8009eb8: 9301 str r3, [sp, #4] + 8009eba: e9cd 4502 strd r4, r5, [sp, #8] + 8009ebe: e9cd 4504 strd r4, r5, [sp, #16] + 8009ec2: b9a6 cbnz r6, 8009eee + 8009ec4: f04f 4260 mov.w r2, #3758096384 ; 0xe0000000 + 8009ec8: 4b25 ldr r3, [pc, #148] ; (8009f60 ) + 8009eca: 4620 mov r0, r4 + 8009ecc: e9cd 2306 strd r2, r3, [sp, #24] + 8009ed0: 4629 mov r1, r5 + 8009ed2: 2200 movs r2, #0 + 8009ed4: 2300 movs r3, #0 + 8009ed6: f7f6 fd6f bl 80009b8 <__aeabi_dcmpeq> + 8009eda: bb40 cbnz r0, 8009f2e + 8009edc: 2301 movs r3, #1 + 8009ede: 2e02 cmp r6, #2 + 8009ee0: 9300 str r3, [sp, #0] + 8009ee2: d119 bne.n 8009f18 + 8009ee4: f002 fd64 bl 800c9b0 <__errno> + 8009ee8: 2321 movs r3, #33 ; 0x21 + 8009eea: 6003 str r3, [r0, #0] + 8009eec: e019 b.n 8009f22 + 8009eee: 2200 movs r2, #0 + 8009ef0: 4b1c ldr r3, [pc, #112] ; (8009f64 ) + 8009ef2: 4620 mov r0, r4 + 8009ef4: e9cd 2306 strd r2, r3, [sp, #24] + 8009ef8: 4629 mov r1, r5 + 8009efa: 2200 movs r2, #0 + 8009efc: 2300 movs r3, #0 + 8009efe: f7f6 fd5b bl 80009b8 <__aeabi_dcmpeq> + 8009f02: 2800 cmp r0, #0 + 8009f04: d0ea beq.n 8009edc + 8009f06: 2302 movs r3, #2 + 8009f08: 429e cmp r6, r3 + 8009f0a: 9300 str r3, [sp, #0] + 8009f0c: d111 bne.n 8009f32 + 8009f0e: f002 fd4f bl 800c9b0 <__errno> + 8009f12: 2322 movs r3, #34 ; 0x22 + 8009f14: 6003 str r3, [r0, #0] + 8009f16: e011 b.n 8009f3c + 8009f18: 4668 mov r0, sp + 8009f1a: f002 fc3d bl 800c798 + 8009f1e: 2800 cmp r0, #0 + 8009f20: d0e0 beq.n 8009ee4 + 8009f22: 4811 ldr r0, [pc, #68] ; (8009f68 ) + 8009f24: f002 fc3a bl 800c79c + 8009f28: e9cd 0106 strd r0, r1, [sp, #24] + 8009f2c: e006 b.n 8009f3c + 8009f2e: 2302 movs r3, #2 + 8009f30: 9300 str r3, [sp, #0] + 8009f32: 4668 mov r0, sp + 8009f34: f002 fc30 bl 800c798 + 8009f38: 2800 cmp r0, #0 + 8009f3a: d0e8 beq.n 8009f0e + 8009f3c: 9b08 ldr r3, [sp, #32] + 8009f3e: b11b cbz r3, 8009f48 + 8009f40: f002 fd36 bl 800c9b0 <__errno> + 8009f44: 9b08 ldr r3, [sp, #32] + 8009f46: 6003 str r3, [r0, #0] + 8009f48: e9dd 8906 ldrd r8, r9, [sp, #24] + 8009f4c: 4640 mov r0, r8 + 8009f4e: 4649 mov r1, r9 + 8009f50: b00a add sp, #40 ; 0x28 + 8009f52: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} + 8009f56: bf00 nop + 8009f58: 200000c4 .word 0x200000c4 + 8009f5c: 0800e58d .word 0x0800e58d + 8009f60: c7efffff .word 0xc7efffff + 8009f64: fff00000 .word 0xfff00000 + 8009f68: 0800e590 .word 0x0800e590 + +08009f6c : + 8009f6c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8009f70: b08f sub sp, #60 ; 0x3c + 8009f72: 461d mov r5, r3 + 8009f74: 4680 mov r8, r0 + 8009f76: 4689 mov r9, r1 + 8009f78: 4614 mov r4, r2 + 8009f7a: f000 fd59 bl 800aa30 <__ieee754_pow> + 8009f7e: 4fa1 ldr r7, [pc, #644] ; (800a204 ) + 8009f80: e9cd 0100 strd r0, r1, [sp] + 8009f84: f997 3000 ldrsb.w r3, [r7] + 8009f88: 463e mov r6, r7 + 8009f8a: 9302 str r3, [sp, #8] + 8009f8c: 3301 adds r3, #1 + 8009f8e: d05f beq.n 800a050 + 8009f90: 4622 mov r2, r4 + 8009f92: 462b mov r3, r5 + 8009f94: 4620 mov r0, r4 + 8009f96: 4629 mov r1, r5 + 8009f98: f7f6 fd40 bl 8000a1c <__aeabi_dcmpun> + 8009f9c: 4682 mov sl, r0 + 8009f9e: 2800 cmp r0, #0 + 8009fa0: d156 bne.n 800a050 + 8009fa2: 4642 mov r2, r8 + 8009fa4: 464b mov r3, r9 + 8009fa6: 4640 mov r0, r8 + 8009fa8: 4649 mov r1, r9 + 8009faa: f7f6 fd37 bl 8000a1c <__aeabi_dcmpun> + 8009fae: 9003 str r0, [sp, #12] + 8009fb0: b1e8 cbz r0, 8009fee + 8009fb2: 2200 movs r2, #0 + 8009fb4: 2300 movs r3, #0 + 8009fb6: 4620 mov r0, r4 + 8009fb8: 4629 mov r1, r5 + 8009fba: f7f6 fcfd bl 80009b8 <__aeabi_dcmpeq> + 8009fbe: 2800 cmp r0, #0 + 8009fc0: d046 beq.n 800a050 + 8009fc2: 2301 movs r3, #1 + 8009fc4: 2200 movs r2, #0 + 8009fc6: 9304 str r3, [sp, #16] + 8009fc8: 4b8f ldr r3, [pc, #572] ; (800a208 ) + 8009fca: f8cd a030 str.w sl, [sp, #48] ; 0x30 + 8009fce: 9305 str r3, [sp, #20] + 8009fd0: 4b8e ldr r3, [pc, #568] ; (800a20c ) + 8009fd2: e9cd 8906 strd r8, r9, [sp, #24] + 8009fd6: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 8009fda: 9b02 ldr r3, [sp, #8] + 8009fdc: e9cd 4508 strd r4, r5, [sp, #32] + 8009fe0: 2b02 cmp r3, #2 + 8009fe2: d031 beq.n 800a048 + 8009fe4: a804 add r0, sp, #16 + 8009fe6: f002 fbd7 bl 800c798 + 8009fea: bb38 cbnz r0, 800a03c + 8009fec: e058 b.n 800a0a0 + 8009fee: f04f 0a00 mov.w sl, #0 + 8009ff2: f04f 0b00 mov.w fp, #0 + 8009ff6: 4652 mov r2, sl + 8009ff8: 465b mov r3, fp + 8009ffa: 4640 mov r0, r8 + 8009ffc: 4649 mov r1, r9 + 8009ffe: f7f6 fcdb bl 80009b8 <__aeabi_dcmpeq> + 800a002: 2800 cmp r0, #0 + 800a004: d051 beq.n 800a0aa + 800a006: 4652 mov r2, sl + 800a008: 465b mov r3, fp + 800a00a: 4620 mov r0, r4 + 800a00c: 4629 mov r1, r5 + 800a00e: f7f6 fcd3 bl 80009b8 <__aeabi_dcmpeq> + 800a012: 4606 mov r6, r0 + 800a014: b308 cbz r0, 800a05a + 800a016: 2301 movs r3, #1 + 800a018: 9304 str r3, [sp, #16] + 800a01a: 4b7b ldr r3, [pc, #492] ; (800a208 ) + 800a01c: e9cd 8906 strd r8, r9, [sp, #24] + 800a020: 9305 str r3, [sp, #20] + 800a022: 9b03 ldr r3, [sp, #12] + 800a024: e9cd 4508 strd r4, r5, [sp, #32] + 800a028: 930c str r3, [sp, #48] ; 0x30 + 800a02a: 9b02 ldr r3, [sp, #8] + 800a02c: e9cd ab0a strd sl, fp, [sp, #40] ; 0x28 + 800a030: 2b00 cmp r3, #0 + 800a032: d0d7 beq.n 8009fe4 + 800a034: 2200 movs r2, #0 + 800a036: 4b75 ldr r3, [pc, #468] ; (800a20c ) + 800a038: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 800a03c: 9b0c ldr r3, [sp, #48] ; 0x30 + 800a03e: b11b cbz r3, 800a048 + 800a040: f002 fcb6 bl 800c9b0 <__errno> + 800a044: 9b0c ldr r3, [sp, #48] ; 0x30 + 800a046: 6003 str r3, [r0, #0] + 800a048: e9dd 340a ldrd r3, r4, [sp, #40] ; 0x28 + 800a04c: e9cd 3400 strd r3, r4, [sp] + 800a050: e9dd 0100 ldrd r0, r1, [sp] + 800a054: b00f add sp, #60 ; 0x3c + 800a056: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800a05a: 4620 mov r0, r4 + 800a05c: 4629 mov r1, r5 + 800a05e: f002 fb0f bl 800c680 + 800a062: 2800 cmp r0, #0 + 800a064: d0f4 beq.n 800a050 + 800a066: 4652 mov r2, sl + 800a068: 465b mov r3, fp + 800a06a: 4620 mov r0, r4 + 800a06c: 4629 mov r1, r5 + 800a06e: f7f6 fcad bl 80009cc <__aeabi_dcmplt> + 800a072: 2800 cmp r0, #0 + 800a074: d0ec beq.n 800a050 + 800a076: 2301 movs r3, #1 + 800a078: 9304 str r3, [sp, #16] + 800a07a: 4b63 ldr r3, [pc, #396] ; (800a208 ) + 800a07c: 960c str r6, [sp, #48] ; 0x30 + 800a07e: 9305 str r3, [sp, #20] + 800a080: f997 3000 ldrsb.w r3, [r7] + 800a084: e9cd 8906 strd r8, r9, [sp, #24] + 800a088: e9cd 4508 strd r4, r5, [sp, #32] + 800a08c: b913 cbnz r3, 800a094 + 800a08e: e9cd ab0a strd sl, fp, [sp, #40] ; 0x28 + 800a092: e7a7 b.n 8009fe4 + 800a094: 2000 movs r0, #0 + 800a096: 495e ldr r1, [pc, #376] ; (800a210 ) + 800a098: 2b02 cmp r3, #2 + 800a09a: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 + 800a09e: d1a1 bne.n 8009fe4 + 800a0a0: f002 fc86 bl 800c9b0 <__errno> + 800a0a4: 2321 movs r3, #33 ; 0x21 + 800a0a6: 6003 str r3, [r0, #0] + 800a0a8: e7c8 b.n 800a03c + 800a0aa: e9dd 0100 ldrd r0, r1, [sp] + 800a0ae: f002 fae7 bl 800c680 + 800a0b2: 9002 str r0, [sp, #8] + 800a0b4: 2800 cmp r0, #0 + 800a0b6: d177 bne.n 800a1a8 + 800a0b8: 4640 mov r0, r8 + 800a0ba: 4649 mov r1, r9 + 800a0bc: f002 fae0 bl 800c680 + 800a0c0: 2800 cmp r0, #0 + 800a0c2: d071 beq.n 800a1a8 + 800a0c4: 4620 mov r0, r4 + 800a0c6: 4629 mov r1, r5 + 800a0c8: f002 fada bl 800c680 + 800a0cc: 2800 cmp r0, #0 + 800a0ce: d06b beq.n 800a1a8 + 800a0d0: e9dd 2300 ldrd r2, r3, [sp] + 800a0d4: 4619 mov r1, r3 + 800a0d6: 4610 mov r0, r2 + 800a0d8: f7f6 fca0 bl 8000a1c <__aeabi_dcmpun> + 800a0dc: f997 7000 ldrsb.w r7, [r7] + 800a0e0: 4b49 ldr r3, [pc, #292] ; (800a208 ) + 800a0e2: b1a0 cbz r0, 800a10e + 800a0e4: 2201 movs r2, #1 + 800a0e6: e9cd 2304 strd r2, r3, [sp, #16] + 800a0ea: 9b02 ldr r3, [sp, #8] + 800a0ec: e9cd 8906 strd r8, r9, [sp, #24] + 800a0f0: 930c str r3, [sp, #48] ; 0x30 + 800a0f2: e9cd 4508 strd r4, r5, [sp, #32] + 800a0f6: 2f00 cmp r7, #0 + 800a0f8: d0c9 beq.n 800a08e + 800a0fa: 4652 mov r2, sl + 800a0fc: 465b mov r3, fp + 800a0fe: 4650 mov r0, sl + 800a100: 4659 mov r1, fp + 800a102: f7f6 fb1b bl 800073c <__aeabi_ddiv> + 800a106: 2f02 cmp r7, #2 + 800a108: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 + 800a10c: e7c7 b.n 800a09e + 800a10e: 2203 movs r2, #3 + 800a110: 900c str r0, [sp, #48] ; 0x30 + 800a112: e9cd 2304 strd r2, r3, [sp, #16] + 800a116: 4620 mov r0, r4 + 800a118: 4629 mov r1, r5 + 800a11a: 2200 movs r2, #0 + 800a11c: 4b3d ldr r3, [pc, #244] ; (800a214 ) + 800a11e: e9cd 4508 strd r4, r5, [sp, #32] + 800a122: e9cd 8906 strd r8, r9, [sp, #24] + 800a126: f7f6 f9df bl 80004e8 <__aeabi_dmul> + 800a12a: 4604 mov r4, r0 + 800a12c: 460d mov r5, r1 + 800a12e: bb17 cbnz r7, 800a176 + 800a130: f04f 4260 mov.w r2, #3758096384 ; 0xe0000000 + 800a134: 4b38 ldr r3, [pc, #224] ; (800a218 ) + 800a136: 4640 mov r0, r8 + 800a138: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 800a13c: 4649 mov r1, r9 + 800a13e: 4652 mov r2, sl + 800a140: 465b mov r3, fp + 800a142: f7f6 fc43 bl 80009cc <__aeabi_dcmplt> + 800a146: 2800 cmp r0, #0 + 800a148: d054 beq.n 800a1f4 + 800a14a: 4620 mov r0, r4 + 800a14c: 4629 mov r1, r5 + 800a14e: f002 fb2b bl 800c7a8 + 800a152: 4622 mov r2, r4 + 800a154: 462b mov r3, r5 + 800a156: f7f6 fc2f bl 80009b8 <__aeabi_dcmpeq> + 800a15a: b920 cbnz r0, 800a166 + 800a15c: f04f 4260 mov.w r2, #3758096384 ; 0xe0000000 + 800a160: 4b2e ldr r3, [pc, #184] ; (800a21c ) + 800a162: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 800a166: f996 3000 ldrsb.w r3, [r6] + 800a16a: 2b02 cmp r3, #2 + 800a16c: d142 bne.n 800a1f4 + 800a16e: f002 fc1f bl 800c9b0 <__errno> + 800a172: 2322 movs r3, #34 ; 0x22 + 800a174: e797 b.n 800a0a6 + 800a176: 2200 movs r2, #0 + 800a178: 4b29 ldr r3, [pc, #164] ; (800a220 ) + 800a17a: 4640 mov r0, r8 + 800a17c: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 + 800a180: 4649 mov r1, r9 + 800a182: 4652 mov r2, sl + 800a184: 465b mov r3, fp + 800a186: f7f6 fc21 bl 80009cc <__aeabi_dcmplt> + 800a18a: 2800 cmp r0, #0 + 800a18c: d0eb beq.n 800a166 + 800a18e: 4620 mov r0, r4 + 800a190: 4629 mov r1, r5 + 800a192: f002 fb09 bl 800c7a8 + 800a196: 4622 mov r2, r4 + 800a198: 462b mov r3, r5 + 800a19a: f7f6 fc0d bl 80009b8 <__aeabi_dcmpeq> + 800a19e: 2800 cmp r0, #0 + 800a1a0: d1e1 bne.n 800a166 + 800a1a2: 2200 movs r2, #0 + 800a1a4: 4b1a ldr r3, [pc, #104] ; (800a210 ) + 800a1a6: e7dc b.n 800a162 + 800a1a8: 2200 movs r2, #0 + 800a1aa: e9dd 0100 ldrd r0, r1, [sp] + 800a1ae: 2300 movs r3, #0 + 800a1b0: f7f6 fc02 bl 80009b8 <__aeabi_dcmpeq> + 800a1b4: 2800 cmp r0, #0 + 800a1b6: f43f af4b beq.w 800a050 + 800a1ba: 4640 mov r0, r8 + 800a1bc: 4649 mov r1, r9 + 800a1be: f002 fa5f bl 800c680 + 800a1c2: 2800 cmp r0, #0 + 800a1c4: f43f af44 beq.w 800a050 + 800a1c8: 4620 mov r0, r4 + 800a1ca: 4629 mov r1, r5 + 800a1cc: f002 fa58 bl 800c680 + 800a1d0: 2800 cmp r0, #0 + 800a1d2: f43f af3d beq.w 800a050 + 800a1d6: 2304 movs r3, #4 + 800a1d8: 9304 str r3, [sp, #16] + 800a1da: 4b0b ldr r3, [pc, #44] ; (800a208 ) + 800a1dc: e9cd 4508 strd r4, r5, [sp, #32] + 800a1e0: 9305 str r3, [sp, #20] + 800a1e2: 2300 movs r3, #0 + 800a1e4: 2400 movs r4, #0 + 800a1e6: 930c str r3, [sp, #48] ; 0x30 + 800a1e8: 2300 movs r3, #0 + 800a1ea: e9cd 8906 strd r8, r9, [sp, #24] + 800a1ee: e9cd 340a strd r3, r4, [sp, #40] ; 0x28 + 800a1f2: e7b8 b.n 800a166 + 800a1f4: a804 add r0, sp, #16 + 800a1f6: f002 facf bl 800c798 + 800a1fa: 2800 cmp r0, #0 + 800a1fc: f47f af1e bne.w 800a03c + 800a200: e7b5 b.n 800a16e + 800a202: bf00 nop + 800a204: 200000c4 .word 0x200000c4 + 800a208: 0800e591 .word 0x0800e591 + 800a20c: 3ff00000 .word 0x3ff00000 + 800a210: fff00000 .word 0xfff00000 + 800a214: 3fe00000 .word 0x3fe00000 + 800a218: 47efffff .word 0x47efffff + 800a21c: c7efffff .word 0xc7efffff + 800a220: 7ff00000 .word 0x7ff00000 + +0800a224 : + 800a224: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800a228: b08b sub sp, #44 ; 0x2c + 800a22a: 4604 mov r4, r0 + 800a22c: 460d mov r5, r1 + 800a22e: f001 fafb bl 800b828 <__ieee754_sqrt> + 800a232: 4b24 ldr r3, [pc, #144] ; (800a2c4 ) + 800a234: 4680 mov r8, r0 + 800a236: f993 a000 ldrsb.w sl, [r3] + 800a23a: 4689 mov r9, r1 + 800a23c: f1ba 3fff cmp.w sl, #4294967295 + 800a240: d02b beq.n 800a29a + 800a242: 4622 mov r2, r4 + 800a244: 462b mov r3, r5 + 800a246: 4620 mov r0, r4 + 800a248: 4629 mov r1, r5 + 800a24a: f7f6 fbe7 bl 8000a1c <__aeabi_dcmpun> + 800a24e: 4683 mov fp, r0 + 800a250: bb18 cbnz r0, 800a29a + 800a252: 2600 movs r6, #0 + 800a254: 2700 movs r7, #0 + 800a256: 4632 mov r2, r6 + 800a258: 463b mov r3, r7 + 800a25a: 4620 mov r0, r4 + 800a25c: 4629 mov r1, r5 + 800a25e: f7f6 fbb5 bl 80009cc <__aeabi_dcmplt> + 800a262: b1d0 cbz r0, 800a29a + 800a264: 2301 movs r3, #1 + 800a266: 9300 str r3, [sp, #0] + 800a268: 4b17 ldr r3, [pc, #92] ; (800a2c8 ) + 800a26a: f8cd b020 str.w fp, [sp, #32] + 800a26e: 9301 str r3, [sp, #4] + 800a270: e9cd 4504 strd r4, r5, [sp, #16] + 800a274: e9cd 4502 strd r4, r5, [sp, #8] + 800a278: f1ba 0f00 cmp.w sl, #0 + 800a27c: d112 bne.n 800a2a4 + 800a27e: e9cd 6706 strd r6, r7, [sp, #24] + 800a282: 4668 mov r0, sp + 800a284: f002 fa88 bl 800c798 + 800a288: b1b8 cbz r0, 800a2ba + 800a28a: 9b08 ldr r3, [sp, #32] + 800a28c: b11b cbz r3, 800a296 + 800a28e: f002 fb8f bl 800c9b0 <__errno> + 800a292: 9b08 ldr r3, [sp, #32] + 800a294: 6003 str r3, [r0, #0] + 800a296: e9dd 8906 ldrd r8, r9, [sp, #24] + 800a29a: 4640 mov r0, r8 + 800a29c: 4649 mov r1, r9 + 800a29e: b00b add sp, #44 ; 0x2c + 800a2a0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800a2a4: 4632 mov r2, r6 + 800a2a6: 463b mov r3, r7 + 800a2a8: 4630 mov r0, r6 + 800a2aa: 4639 mov r1, r7 + 800a2ac: f7f6 fa46 bl 800073c <__aeabi_ddiv> + 800a2b0: f1ba 0f02 cmp.w sl, #2 + 800a2b4: e9cd 0106 strd r0, r1, [sp, #24] + 800a2b8: d1e3 bne.n 800a282 + 800a2ba: f002 fb79 bl 800c9b0 <__errno> + 800a2be: 2321 movs r3, #33 ; 0x21 + 800a2c0: 6003 str r3, [r0, #0] + 800a2c2: e7e2 b.n 800a28a + 800a2c4: 200000c4 .word 0x200000c4 + 800a2c8: 0800e595 .word 0x0800e595 + 800a2cc: 00000000 .word 0x00000000 + +0800a2d0 <__ieee754_asin>: + 800a2d0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800a2d4: 4bc4 ldr r3, [pc, #784] ; (800a5e8 <__ieee754_asin+0x318>) + 800a2d6: f021 4700 bic.w r7, r1, #2147483648 ; 0x80000000 + 800a2da: b087 sub sp, #28 + 800a2dc: 429f cmp r7, r3 + 800a2de: 4604 mov r4, r0 + 800a2e0: 460d mov r5, r1 + 800a2e2: 9103 str r1, [sp, #12] + 800a2e4: dd2a ble.n 800a33c <__ieee754_asin+0x6c> + 800a2e6: 4603 mov r3, r0 + 800a2e8: f107 4740 add.w r7, r7, #3221225472 ; 0xc0000000 + 800a2ec: f507 1780 add.w r7, r7, #1048576 ; 0x100000 + 800a2f0: 433b orrs r3, r7 + 800a2f2: d114 bne.n 800a31e <__ieee754_asin+0x4e> + 800a2f4: a3a2 add r3, pc, #648 ; (adr r3, 800a580 <__ieee754_asin+0x2b0>) + 800a2f6: e9d3 2300 ldrd r2, r3, [r3] + 800a2fa: f7f6 f8f5 bl 80004e8 <__aeabi_dmul> + 800a2fe: a3a2 add r3, pc, #648 ; (adr r3, 800a588 <__ieee754_asin+0x2b8>) + 800a300: e9d3 2300 ldrd r2, r3, [r3] + 800a304: 4606 mov r6, r0 + 800a306: 460f mov r7, r1 + 800a308: 4620 mov r0, r4 + 800a30a: 4629 mov r1, r5 + 800a30c: f7f6 f8ec bl 80004e8 <__aeabi_dmul> + 800a310: 4602 mov r2, r0 + 800a312: 460b mov r3, r1 + 800a314: 4630 mov r0, r6 + 800a316: 4639 mov r1, r7 + 800a318: f7f5 ff30 bl 800017c <__adddf3> + 800a31c: e007 b.n 800a32e <__ieee754_asin+0x5e> + 800a31e: 4602 mov r2, r0 + 800a320: 460b mov r3, r1 + 800a322: f7f5 ff29 bl 8000178 <__aeabi_dsub> + 800a326: 4602 mov r2, r0 + 800a328: 460b mov r3, r1 + 800a32a: f7f6 fa07 bl 800073c <__aeabi_ddiv> + 800a32e: 4604 mov r4, r0 + 800a330: 460d mov r5, r1 + 800a332: 4620 mov r0, r4 + 800a334: 4629 mov r1, r5 + 800a336: b007 add sp, #28 + 800a338: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800a33c: 4bab ldr r3, [pc, #684] ; (800a5ec <__ieee754_asin+0x31c>) + 800a33e: 429f cmp r7, r3 + 800a340: dc0e bgt.n 800a360 <__ieee754_asin+0x90> + 800a342: f1b7 5f79 cmp.w r7, #1044381696 ; 0x3e400000 + 800a346: f280 80ab bge.w 800a4a0 <__ieee754_asin+0x1d0> + 800a34a: a391 add r3, pc, #580 ; (adr r3, 800a590 <__ieee754_asin+0x2c0>) + 800a34c: e9d3 2300 ldrd r2, r3, [r3] + 800a350: f7f5 ff14 bl 800017c <__adddf3> + 800a354: 2200 movs r2, #0 + 800a356: 4ba6 ldr r3, [pc, #664] ; (800a5f0 <__ieee754_asin+0x320>) + 800a358: f7f6 fb56 bl 8000a08 <__aeabi_dcmpgt> + 800a35c: 2800 cmp r0, #0 + 800a35e: d1e8 bne.n 800a332 <__ieee754_asin+0x62> + 800a360: 4620 mov r0, r4 + 800a362: 4629 mov r1, r5 + 800a364: f7ff fccc bl 8009d00 + 800a368: 4602 mov r2, r0 + 800a36a: 460b mov r3, r1 + 800a36c: 2000 movs r0, #0 + 800a36e: 49a0 ldr r1, [pc, #640] ; (800a5f0 <__ieee754_asin+0x320>) + 800a370: f7f5 ff02 bl 8000178 <__aeabi_dsub> + 800a374: 2200 movs r2, #0 + 800a376: 4b9f ldr r3, [pc, #636] ; (800a5f4 <__ieee754_asin+0x324>) + 800a378: f7f6 f8b6 bl 80004e8 <__aeabi_dmul> + 800a37c: a386 add r3, pc, #536 ; (adr r3, 800a598 <__ieee754_asin+0x2c8>) + 800a37e: e9d3 2300 ldrd r2, r3, [r3] + 800a382: 4604 mov r4, r0 + 800a384: 460d mov r5, r1 + 800a386: f7f6 f8af bl 80004e8 <__aeabi_dmul> + 800a38a: a385 add r3, pc, #532 ; (adr r3, 800a5a0 <__ieee754_asin+0x2d0>) + 800a38c: e9d3 2300 ldrd r2, r3, [r3] + 800a390: f7f5 fef4 bl 800017c <__adddf3> + 800a394: 4622 mov r2, r4 + 800a396: 462b mov r3, r5 + 800a398: f7f6 f8a6 bl 80004e8 <__aeabi_dmul> + 800a39c: a382 add r3, pc, #520 ; (adr r3, 800a5a8 <__ieee754_asin+0x2d8>) + 800a39e: e9d3 2300 ldrd r2, r3, [r3] + 800a3a2: f7f5 fee9 bl 8000178 <__aeabi_dsub> + 800a3a6: 4622 mov r2, r4 + 800a3a8: 462b mov r3, r5 + 800a3aa: f7f6 f89d bl 80004e8 <__aeabi_dmul> + 800a3ae: a380 add r3, pc, #512 ; (adr r3, 800a5b0 <__ieee754_asin+0x2e0>) + 800a3b0: e9d3 2300 ldrd r2, r3, [r3] + 800a3b4: f7f5 fee2 bl 800017c <__adddf3> + 800a3b8: 4622 mov r2, r4 + 800a3ba: 462b mov r3, r5 + 800a3bc: f7f6 f894 bl 80004e8 <__aeabi_dmul> + 800a3c0: a37d add r3, pc, #500 ; (adr r3, 800a5b8 <__ieee754_asin+0x2e8>) + 800a3c2: e9d3 2300 ldrd r2, r3, [r3] + 800a3c6: f7f5 fed7 bl 8000178 <__aeabi_dsub> + 800a3ca: 4622 mov r2, r4 + 800a3cc: 462b mov r3, r5 + 800a3ce: f7f6 f88b bl 80004e8 <__aeabi_dmul> + 800a3d2: a37b add r3, pc, #492 ; (adr r3, 800a5c0 <__ieee754_asin+0x2f0>) + 800a3d4: e9d3 2300 ldrd r2, r3, [r3] + 800a3d8: f7f5 fed0 bl 800017c <__adddf3> + 800a3dc: 4622 mov r2, r4 + 800a3de: 462b mov r3, r5 + 800a3e0: f7f6 f882 bl 80004e8 <__aeabi_dmul> + 800a3e4: a378 add r3, pc, #480 ; (adr r3, 800a5c8 <__ieee754_asin+0x2f8>) + 800a3e6: e9d3 2300 ldrd r2, r3, [r3] + 800a3ea: 4680 mov r8, r0 + 800a3ec: 4689 mov r9, r1 + 800a3ee: 4620 mov r0, r4 + 800a3f0: 4629 mov r1, r5 + 800a3f2: f7f6 f879 bl 80004e8 <__aeabi_dmul> + 800a3f6: a376 add r3, pc, #472 ; (adr r3, 800a5d0 <__ieee754_asin+0x300>) + 800a3f8: e9d3 2300 ldrd r2, r3, [r3] + 800a3fc: f7f5 febc bl 8000178 <__aeabi_dsub> + 800a400: 4622 mov r2, r4 + 800a402: 462b mov r3, r5 + 800a404: f7f6 f870 bl 80004e8 <__aeabi_dmul> + 800a408: a373 add r3, pc, #460 ; (adr r3, 800a5d8 <__ieee754_asin+0x308>) + 800a40a: e9d3 2300 ldrd r2, r3, [r3] + 800a40e: f7f5 feb5 bl 800017c <__adddf3> + 800a412: 4622 mov r2, r4 + 800a414: 462b mov r3, r5 + 800a416: f7f6 f867 bl 80004e8 <__aeabi_dmul> + 800a41a: a371 add r3, pc, #452 ; (adr r3, 800a5e0 <__ieee754_asin+0x310>) + 800a41c: e9d3 2300 ldrd r2, r3, [r3] + 800a420: f7f5 feaa bl 8000178 <__aeabi_dsub> + 800a424: 4622 mov r2, r4 + 800a426: 462b mov r3, r5 + 800a428: f7f6 f85e bl 80004e8 <__aeabi_dmul> + 800a42c: 4b70 ldr r3, [pc, #448] ; (800a5f0 <__ieee754_asin+0x320>) + 800a42e: 2200 movs r2, #0 + 800a430: f7f5 fea4 bl 800017c <__adddf3> + 800a434: e9cd 0100 strd r0, r1, [sp] + 800a438: 4620 mov r0, r4 + 800a43a: 4629 mov r1, r5 + 800a43c: f001 f9f4 bl 800b828 <__ieee754_sqrt> + 800a440: 4b6d ldr r3, [pc, #436] ; (800a5f8 <__ieee754_asin+0x328>) + 800a442: 4682 mov sl, r0 + 800a444: 429f cmp r7, r3 + 800a446: 468b mov fp, r1 + 800a448: f340 80d8 ble.w 800a5fc <__ieee754_asin+0x32c> + 800a44c: e9dd 2300 ldrd r2, r3, [sp] + 800a450: 4640 mov r0, r8 + 800a452: 4649 mov r1, r9 + 800a454: f7f6 f972 bl 800073c <__aeabi_ddiv> + 800a458: 4652 mov r2, sl + 800a45a: 465b mov r3, fp + 800a45c: f7f6 f844 bl 80004e8 <__aeabi_dmul> + 800a460: 4652 mov r2, sl + 800a462: 465b mov r3, fp + 800a464: f7f5 fe8a bl 800017c <__adddf3> + 800a468: 4602 mov r2, r0 + 800a46a: 460b mov r3, r1 + 800a46c: f7f5 fe86 bl 800017c <__adddf3> + 800a470: a345 add r3, pc, #276 ; (adr r3, 800a588 <__ieee754_asin+0x2b8>) + 800a472: e9d3 2300 ldrd r2, r3, [r3] + 800a476: f7f5 fe7f bl 8000178 <__aeabi_dsub> + 800a47a: 4602 mov r2, r0 + 800a47c: 460b mov r3, r1 + 800a47e: a140 add r1, pc, #256 ; (adr r1, 800a580 <__ieee754_asin+0x2b0>) + 800a480: e9d1 0100 ldrd r0, r1, [r1] + 800a484: f7f5 fe78 bl 8000178 <__aeabi_dsub> + 800a488: 9b03 ldr r3, [sp, #12] + 800a48a: 4604 mov r4, r0 + 800a48c: 2b00 cmp r3, #0 + 800a48e: bfdc itt le + 800a490: 4602 movle r2, r0 + 800a492: f101 4300 addle.w r3, r1, #2147483648 ; 0x80000000 + 800a496: 460d mov r5, r1 + 800a498: bfdc itt le + 800a49a: 4614 movle r4, r2 + 800a49c: 461d movle r5, r3 + 800a49e: e748 b.n 800a332 <__ieee754_asin+0x62> + 800a4a0: 4602 mov r2, r0 + 800a4a2: 460b mov r3, r1 + 800a4a4: f7f6 f820 bl 80004e8 <__aeabi_dmul> + 800a4a8: a33b add r3, pc, #236 ; (adr r3, 800a598 <__ieee754_asin+0x2c8>) + 800a4aa: e9d3 2300 ldrd r2, r3, [r3] + 800a4ae: 4606 mov r6, r0 + 800a4b0: 460f mov r7, r1 + 800a4b2: f7f6 f819 bl 80004e8 <__aeabi_dmul> + 800a4b6: a33a add r3, pc, #232 ; (adr r3, 800a5a0 <__ieee754_asin+0x2d0>) + 800a4b8: e9d3 2300 ldrd r2, r3, [r3] + 800a4bc: f7f5 fe5e bl 800017c <__adddf3> + 800a4c0: 4632 mov r2, r6 + 800a4c2: 463b mov r3, r7 + 800a4c4: f7f6 f810 bl 80004e8 <__aeabi_dmul> + 800a4c8: a337 add r3, pc, #220 ; (adr r3, 800a5a8 <__ieee754_asin+0x2d8>) + 800a4ca: e9d3 2300 ldrd r2, r3, [r3] + 800a4ce: f7f5 fe53 bl 8000178 <__aeabi_dsub> + 800a4d2: 4632 mov r2, r6 + 800a4d4: 463b mov r3, r7 + 800a4d6: f7f6 f807 bl 80004e8 <__aeabi_dmul> + 800a4da: a335 add r3, pc, #212 ; (adr r3, 800a5b0 <__ieee754_asin+0x2e0>) + 800a4dc: e9d3 2300 ldrd r2, r3, [r3] + 800a4e0: f7f5 fe4c bl 800017c <__adddf3> + 800a4e4: 4632 mov r2, r6 + 800a4e6: 463b mov r3, r7 + 800a4e8: f7f5 fffe bl 80004e8 <__aeabi_dmul> + 800a4ec: a332 add r3, pc, #200 ; (adr r3, 800a5b8 <__ieee754_asin+0x2e8>) + 800a4ee: e9d3 2300 ldrd r2, r3, [r3] + 800a4f2: f7f5 fe41 bl 8000178 <__aeabi_dsub> + 800a4f6: 4632 mov r2, r6 + 800a4f8: 463b mov r3, r7 + 800a4fa: f7f5 fff5 bl 80004e8 <__aeabi_dmul> + 800a4fe: a330 add r3, pc, #192 ; (adr r3, 800a5c0 <__ieee754_asin+0x2f0>) + 800a500: e9d3 2300 ldrd r2, r3, [r3] + 800a504: f7f5 fe3a bl 800017c <__adddf3> + 800a508: 4632 mov r2, r6 + 800a50a: 463b mov r3, r7 + 800a50c: f7f5 ffec bl 80004e8 <__aeabi_dmul> + 800a510: a32d add r3, pc, #180 ; (adr r3, 800a5c8 <__ieee754_asin+0x2f8>) + 800a512: e9d3 2300 ldrd r2, r3, [r3] + 800a516: 4680 mov r8, r0 + 800a518: 4689 mov r9, r1 + 800a51a: 4630 mov r0, r6 + 800a51c: 4639 mov r1, r7 + 800a51e: f7f5 ffe3 bl 80004e8 <__aeabi_dmul> + 800a522: a32b add r3, pc, #172 ; (adr r3, 800a5d0 <__ieee754_asin+0x300>) + 800a524: e9d3 2300 ldrd r2, r3, [r3] + 800a528: f7f5 fe26 bl 8000178 <__aeabi_dsub> + 800a52c: 4632 mov r2, r6 + 800a52e: 463b mov r3, r7 + 800a530: f7f5 ffda bl 80004e8 <__aeabi_dmul> + 800a534: a328 add r3, pc, #160 ; (adr r3, 800a5d8 <__ieee754_asin+0x308>) + 800a536: e9d3 2300 ldrd r2, r3, [r3] + 800a53a: f7f5 fe1f bl 800017c <__adddf3> + 800a53e: 4632 mov r2, r6 + 800a540: 463b mov r3, r7 + 800a542: f7f5 ffd1 bl 80004e8 <__aeabi_dmul> + 800a546: a326 add r3, pc, #152 ; (adr r3, 800a5e0 <__ieee754_asin+0x310>) + 800a548: e9d3 2300 ldrd r2, r3, [r3] + 800a54c: f7f5 fe14 bl 8000178 <__aeabi_dsub> + 800a550: 4632 mov r2, r6 + 800a552: 463b mov r3, r7 + 800a554: f7f5 ffc8 bl 80004e8 <__aeabi_dmul> + 800a558: 2200 movs r2, #0 + 800a55a: 4b25 ldr r3, [pc, #148] ; (800a5f0 <__ieee754_asin+0x320>) + 800a55c: f7f5 fe0e bl 800017c <__adddf3> + 800a560: 4602 mov r2, r0 + 800a562: 460b mov r3, r1 + 800a564: 4640 mov r0, r8 + 800a566: 4649 mov r1, r9 + 800a568: f7f6 f8e8 bl 800073c <__aeabi_ddiv> + 800a56c: 4622 mov r2, r4 + 800a56e: 462b mov r3, r5 + 800a570: f7f5 ffba bl 80004e8 <__aeabi_dmul> + 800a574: 4602 mov r2, r0 + 800a576: 460b mov r3, r1 + 800a578: 4620 mov r0, r4 + 800a57a: 4629 mov r1, r5 + 800a57c: e6cc b.n 800a318 <__ieee754_asin+0x48> + 800a57e: bf00 nop + 800a580: 54442d18 .word 0x54442d18 + 800a584: 3ff921fb .word 0x3ff921fb + 800a588: 33145c07 .word 0x33145c07 + 800a58c: 3c91a626 .word 0x3c91a626 + 800a590: 8800759c .word 0x8800759c + 800a594: 7e37e43c .word 0x7e37e43c + 800a598: 0dfdf709 .word 0x0dfdf709 + 800a59c: 3f023de1 .word 0x3f023de1 + 800a5a0: 7501b288 .word 0x7501b288 + 800a5a4: 3f49efe0 .word 0x3f49efe0 + 800a5a8: b5688f3b .word 0xb5688f3b + 800a5ac: 3fa48228 .word 0x3fa48228 + 800a5b0: 0e884455 .word 0x0e884455 + 800a5b4: 3fc9c155 .word 0x3fc9c155 + 800a5b8: 03eb6f7d .word 0x03eb6f7d + 800a5bc: 3fd4d612 .word 0x3fd4d612 + 800a5c0: 55555555 .word 0x55555555 + 800a5c4: 3fc55555 .word 0x3fc55555 + 800a5c8: b12e9282 .word 0xb12e9282 + 800a5cc: 3fb3b8c5 .word 0x3fb3b8c5 + 800a5d0: 1b8d0159 .word 0x1b8d0159 + 800a5d4: 3fe6066c .word 0x3fe6066c + 800a5d8: 9c598ac8 .word 0x9c598ac8 + 800a5dc: 40002ae5 .word 0x40002ae5 + 800a5e0: 1c8a2d4b .word 0x1c8a2d4b + 800a5e4: 40033a27 .word 0x40033a27 + 800a5e8: 3fefffff .word 0x3fefffff + 800a5ec: 3fdfffff .word 0x3fdfffff + 800a5f0: 3ff00000 .word 0x3ff00000 + 800a5f4: 3fe00000 .word 0x3fe00000 + 800a5f8: 3fef3332 .word 0x3fef3332 + 800a5fc: 4602 mov r2, r0 + 800a5fe: 460b mov r3, r1 + 800a600: 460f mov r7, r1 + 800a602: f7f5 fdbb bl 800017c <__adddf3> + 800a606: e9dd 2300 ldrd r2, r3, [sp] + 800a60a: e9cd 0104 strd r0, r1, [sp, #16] + 800a60e: 4640 mov r0, r8 + 800a610: 4649 mov r1, r9 + 800a612: f7f6 f893 bl 800073c <__aeabi_ddiv> + 800a616: 4602 mov r2, r0 + 800a618: 460b mov r3, r1 + 800a61a: e9dd 0104 ldrd r0, r1, [sp, #16] + 800a61e: f7f5 ff63 bl 80004e8 <__aeabi_dmul> + 800a622: 2600 movs r6, #0 + 800a624: 4680 mov r8, r0 + 800a626: 4689 mov r9, r1 + 800a628: 4632 mov r2, r6 + 800a62a: 465b mov r3, fp + 800a62c: 4630 mov r0, r6 + 800a62e: 4659 mov r1, fp + 800a630: f7f5 ff5a bl 80004e8 <__aeabi_dmul> + 800a634: 4602 mov r2, r0 + 800a636: 460b mov r3, r1 + 800a638: 4620 mov r0, r4 + 800a63a: 4629 mov r1, r5 + 800a63c: f7f5 fd9c bl 8000178 <__aeabi_dsub> + 800a640: 4632 mov r2, r6 + 800a642: 4604 mov r4, r0 + 800a644: 460d mov r5, r1 + 800a646: 465b mov r3, fp + 800a648: 4650 mov r0, sl + 800a64a: 4659 mov r1, fp + 800a64c: f7f5 fd96 bl 800017c <__adddf3> + 800a650: 4602 mov r2, r0 + 800a652: 460b mov r3, r1 + 800a654: 4620 mov r0, r4 + 800a656: 4629 mov r1, r5 + 800a658: f7f6 f870 bl 800073c <__aeabi_ddiv> + 800a65c: 4602 mov r2, r0 + 800a65e: 460b mov r3, r1 + 800a660: f7f5 fd8c bl 800017c <__adddf3> + 800a664: 4602 mov r2, r0 + 800a666: 460b mov r3, r1 + 800a668: a113 add r1, pc, #76 ; (adr r1, 800a6b8 <__ieee754_asin+0x3e8>) + 800a66a: e9d1 0100 ldrd r0, r1, [r1] + 800a66e: f7f5 fd83 bl 8000178 <__aeabi_dsub> + 800a672: 4602 mov r2, r0 + 800a674: 460b mov r3, r1 + 800a676: 4640 mov r0, r8 + 800a678: 4649 mov r1, r9 + 800a67a: f7f5 fd7d bl 8000178 <__aeabi_dsub> + 800a67e: 4632 mov r2, r6 + 800a680: 4604 mov r4, r0 + 800a682: 460d mov r5, r1 + 800a684: 465b mov r3, fp + 800a686: 4630 mov r0, r6 + 800a688: 4639 mov r1, r7 + 800a68a: f7f5 fd77 bl 800017c <__adddf3> + 800a68e: 4602 mov r2, r0 + 800a690: 460b mov r3, r1 + 800a692: a10b add r1, pc, #44 ; (adr r1, 800a6c0 <__ieee754_asin+0x3f0>) + 800a694: e9d1 0100 ldrd r0, r1, [r1] + 800a698: f7f5 fd6e bl 8000178 <__aeabi_dsub> + 800a69c: 4602 mov r2, r0 + 800a69e: 460b mov r3, r1 + 800a6a0: 4620 mov r0, r4 + 800a6a2: 4629 mov r1, r5 + 800a6a4: f7f5 fd68 bl 8000178 <__aeabi_dsub> + 800a6a8: 4602 mov r2, r0 + 800a6aa: 460b mov r3, r1 + 800a6ac: a104 add r1, pc, #16 ; (adr r1, 800a6c0 <__ieee754_asin+0x3f0>) + 800a6ae: e9d1 0100 ldrd r0, r1, [r1] + 800a6b2: e6e7 b.n 800a484 <__ieee754_asin+0x1b4> + 800a6b4: f3af 8000 nop.w + 800a6b8: 33145c07 .word 0x33145c07 + 800a6bc: 3c91a626 .word 0x3c91a626 + 800a6c0: 54442d18 .word 0x54442d18 + 800a6c4: 3fe921fb .word 0x3fe921fb + +0800a6c8 <__ieee754_log>: + 800a6c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800a6cc: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 + 800a6d0: b087 sub sp, #28 + 800a6d2: 4602 mov r2, r0 + 800a6d4: 460b mov r3, r1 + 800a6d6: 460d mov r5, r1 + 800a6d8: da24 bge.n 800a724 <__ieee754_log+0x5c> + 800a6da: f021 4400 bic.w r4, r1, #2147483648 ; 0x80000000 + 800a6de: 4304 orrs r4, r0 + 800a6e0: d108 bne.n 800a6f4 <__ieee754_log+0x2c> + 800a6e2: 2200 movs r2, #0 + 800a6e4: 2300 movs r3, #0 + 800a6e6: 2000 movs r0, #0 + 800a6e8: 49cb ldr r1, [pc, #812] ; (800aa18 <__ieee754_log+0x350>) + 800a6ea: f7f6 f827 bl 800073c <__aeabi_ddiv> + 800a6ee: b007 add sp, #28 + 800a6f0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800a6f4: 2900 cmp r1, #0 + 800a6f6: da04 bge.n 800a702 <__ieee754_log+0x3a> + 800a6f8: f7f5 fd3e bl 8000178 <__aeabi_dsub> + 800a6fc: 2200 movs r2, #0 + 800a6fe: 2300 movs r3, #0 + 800a700: e7f3 b.n 800a6ea <__ieee754_log+0x22> + 800a702: 2200 movs r2, #0 + 800a704: 4bc5 ldr r3, [pc, #788] ; (800aa1c <__ieee754_log+0x354>) + 800a706: f7f5 feef bl 80004e8 <__aeabi_dmul> + 800a70a: f06f 0635 mvn.w r6, #53 ; 0x35 + 800a70e: 4602 mov r2, r0 + 800a710: 460b mov r3, r1 + 800a712: 460d mov r5, r1 + 800a714: 49c2 ldr r1, [pc, #776] ; (800aa20 <__ieee754_log+0x358>) + 800a716: 428d cmp r5, r1 + 800a718: dd06 ble.n 800a728 <__ieee754_log+0x60> + 800a71a: 4610 mov r0, r2 + 800a71c: 4619 mov r1, r3 + 800a71e: f7f5 fd2d bl 800017c <__adddf3> + 800a722: e7e4 b.n 800a6ee <__ieee754_log+0x26> + 800a724: 2600 movs r6, #0 + 800a726: e7f5 b.n 800a714 <__ieee754_log+0x4c> + 800a728: 152c asrs r4, r5, #20 + 800a72a: f3c5 0513 ubfx r5, r5, #0, #20 + 800a72e: f505 2115 add.w r1, r5, #610304 ; 0x95000 + 800a732: f2a4 34ff subw r4, r4, #1023 ; 0x3ff + 800a736: f601 7164 addw r1, r1, #3940 ; 0xf64 + 800a73a: 4426 add r6, r4 + 800a73c: f401 1480 and.w r4, r1, #1048576 ; 0x100000 + 800a740: f084 517f eor.w r1, r4, #1069547520 ; 0x3fc00000 + 800a744: f481 1140 eor.w r1, r1, #3145728 ; 0x300000 + 800a748: ea41 0305 orr.w r3, r1, r5 + 800a74c: 4610 mov r0, r2 + 800a74e: 4619 mov r1, r3 + 800a750: 2200 movs r2, #0 + 800a752: 4bb4 ldr r3, [pc, #720] ; (800aa24 <__ieee754_log+0x35c>) + 800a754: f7f5 fd10 bl 8000178 <__aeabi_dsub> + 800a758: 1cab adds r3, r5, #2 + 800a75a: f3c3 0313 ubfx r3, r3, #0, #20 + 800a75e: 2b02 cmp r3, #2 + 800a760: eb06 5414 add.w r4, r6, r4, lsr #20 + 800a764: 4682 mov sl, r0 + 800a766: 468b mov fp, r1 + 800a768: f04f 0200 mov.w r2, #0 + 800a76c: dc53 bgt.n 800a816 <__ieee754_log+0x14e> + 800a76e: 2300 movs r3, #0 + 800a770: f7f6 f922 bl 80009b8 <__aeabi_dcmpeq> + 800a774: b1d0 cbz r0, 800a7ac <__ieee754_log+0xe4> + 800a776: 2c00 cmp r4, #0 + 800a778: f000 8120 beq.w 800a9bc <__ieee754_log+0x2f4> + 800a77c: 4620 mov r0, r4 + 800a77e: f7f5 fe49 bl 8000414 <__aeabi_i2d> + 800a782: a391 add r3, pc, #580 ; (adr r3, 800a9c8 <__ieee754_log+0x300>) + 800a784: e9d3 2300 ldrd r2, r3, [r3] + 800a788: 4606 mov r6, r0 + 800a78a: 460f mov r7, r1 + 800a78c: f7f5 feac bl 80004e8 <__aeabi_dmul> + 800a790: a38f add r3, pc, #572 ; (adr r3, 800a9d0 <__ieee754_log+0x308>) + 800a792: e9d3 2300 ldrd r2, r3, [r3] + 800a796: 4604 mov r4, r0 + 800a798: 460d mov r5, r1 + 800a79a: 4630 mov r0, r6 + 800a79c: 4639 mov r1, r7 + 800a79e: f7f5 fea3 bl 80004e8 <__aeabi_dmul> + 800a7a2: 4602 mov r2, r0 + 800a7a4: 460b mov r3, r1 + 800a7a6: 4620 mov r0, r4 + 800a7a8: 4629 mov r1, r5 + 800a7aa: e7b8 b.n 800a71e <__ieee754_log+0x56> + 800a7ac: a38a add r3, pc, #552 ; (adr r3, 800a9d8 <__ieee754_log+0x310>) + 800a7ae: e9d3 2300 ldrd r2, r3, [r3] + 800a7b2: 4650 mov r0, sl + 800a7b4: 4659 mov r1, fp + 800a7b6: f7f5 fe97 bl 80004e8 <__aeabi_dmul> + 800a7ba: 4602 mov r2, r0 + 800a7bc: 460b mov r3, r1 + 800a7be: 2000 movs r0, #0 + 800a7c0: 4999 ldr r1, [pc, #612] ; (800aa28 <__ieee754_log+0x360>) + 800a7c2: f7f5 fcd9 bl 8000178 <__aeabi_dsub> + 800a7c6: 4652 mov r2, sl + 800a7c8: 4606 mov r6, r0 + 800a7ca: 460f mov r7, r1 + 800a7cc: 465b mov r3, fp + 800a7ce: 4650 mov r0, sl + 800a7d0: 4659 mov r1, fp + 800a7d2: f7f5 fe89 bl 80004e8 <__aeabi_dmul> + 800a7d6: 4602 mov r2, r0 + 800a7d8: 460b mov r3, r1 + 800a7da: 4630 mov r0, r6 + 800a7dc: 4639 mov r1, r7 + 800a7de: f7f5 fe83 bl 80004e8 <__aeabi_dmul> + 800a7e2: 4606 mov r6, r0 + 800a7e4: 460f mov r7, r1 + 800a7e6: b914 cbnz r4, 800a7ee <__ieee754_log+0x126> + 800a7e8: 4632 mov r2, r6 + 800a7ea: 463b mov r3, r7 + 800a7ec: e0a0 b.n 800a930 <__ieee754_log+0x268> + 800a7ee: 4620 mov r0, r4 + 800a7f0: f7f5 fe10 bl 8000414 <__aeabi_i2d> + 800a7f4: a374 add r3, pc, #464 ; (adr r3, 800a9c8 <__ieee754_log+0x300>) + 800a7f6: e9d3 2300 ldrd r2, r3, [r3] + 800a7fa: 4680 mov r8, r0 + 800a7fc: 4689 mov r9, r1 + 800a7fe: f7f5 fe73 bl 80004e8 <__aeabi_dmul> + 800a802: a373 add r3, pc, #460 ; (adr r3, 800a9d0 <__ieee754_log+0x308>) + 800a804: e9d3 2300 ldrd r2, r3, [r3] + 800a808: 4604 mov r4, r0 + 800a80a: 460d mov r5, r1 + 800a80c: 4640 mov r0, r8 + 800a80e: 4649 mov r1, r9 + 800a810: f7f5 fe6a bl 80004e8 <__aeabi_dmul> + 800a814: e0a5 b.n 800a962 <__ieee754_log+0x29a> + 800a816: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 800a81a: f7f5 fcaf bl 800017c <__adddf3> + 800a81e: 4602 mov r2, r0 + 800a820: 460b mov r3, r1 + 800a822: 4650 mov r0, sl + 800a824: 4659 mov r1, fp + 800a826: f7f5 ff89 bl 800073c <__aeabi_ddiv> + 800a82a: e9cd 0100 strd r0, r1, [sp] + 800a82e: 4620 mov r0, r4 + 800a830: f7f5 fdf0 bl 8000414 <__aeabi_i2d> + 800a834: e9dd 2300 ldrd r2, r3, [sp] + 800a838: e9cd 0102 strd r0, r1, [sp, #8] + 800a83c: 4610 mov r0, r2 + 800a83e: 4619 mov r1, r3 + 800a840: f7f5 fe52 bl 80004e8 <__aeabi_dmul> + 800a844: 4602 mov r2, r0 + 800a846: 460b mov r3, r1 + 800a848: e9cd 0104 strd r0, r1, [sp, #16] + 800a84c: f7f5 fe4c bl 80004e8 <__aeabi_dmul> + 800a850: a363 add r3, pc, #396 ; (adr r3, 800a9e0 <__ieee754_log+0x318>) + 800a852: e9d3 2300 ldrd r2, r3, [r3] + 800a856: 4680 mov r8, r0 + 800a858: 4689 mov r9, r1 + 800a85a: f7f5 fe45 bl 80004e8 <__aeabi_dmul> + 800a85e: a362 add r3, pc, #392 ; (adr r3, 800a9e8 <__ieee754_log+0x320>) + 800a860: e9d3 2300 ldrd r2, r3, [r3] + 800a864: f7f5 fc8a bl 800017c <__adddf3> + 800a868: 4642 mov r2, r8 + 800a86a: 464b mov r3, r9 + 800a86c: f7f5 fe3c bl 80004e8 <__aeabi_dmul> + 800a870: a35f add r3, pc, #380 ; (adr r3, 800a9f0 <__ieee754_log+0x328>) + 800a872: e9d3 2300 ldrd r2, r3, [r3] + 800a876: f7f5 fc81 bl 800017c <__adddf3> + 800a87a: 4642 mov r2, r8 + 800a87c: 464b mov r3, r9 + 800a87e: f7f5 fe33 bl 80004e8 <__aeabi_dmul> + 800a882: a35d add r3, pc, #372 ; (adr r3, 800a9f8 <__ieee754_log+0x330>) + 800a884: e9d3 2300 ldrd r2, r3, [r3] + 800a888: f7f5 fc78 bl 800017c <__adddf3> + 800a88c: e9dd 2304 ldrd r2, r3, [sp, #16] + 800a890: f7f5 fe2a bl 80004e8 <__aeabi_dmul> + 800a894: a35a add r3, pc, #360 ; (adr r3, 800aa00 <__ieee754_log+0x338>) + 800a896: e9d3 2300 ldrd r2, r3, [r3] + 800a89a: e9cd 0104 strd r0, r1, [sp, #16] + 800a89e: 4640 mov r0, r8 + 800a8a0: 4649 mov r1, r9 + 800a8a2: f7f5 fe21 bl 80004e8 <__aeabi_dmul> + 800a8a6: a358 add r3, pc, #352 ; (adr r3, 800aa08 <__ieee754_log+0x340>) + 800a8a8: e9d3 2300 ldrd r2, r3, [r3] + 800a8ac: f7f5 fc66 bl 800017c <__adddf3> + 800a8b0: 4642 mov r2, r8 + 800a8b2: 464b mov r3, r9 + 800a8b4: f7f5 fe18 bl 80004e8 <__aeabi_dmul> + 800a8b8: a355 add r3, pc, #340 ; (adr r3, 800aa10 <__ieee754_log+0x348>) + 800a8ba: e9d3 2300 ldrd r2, r3, [r3] + 800a8be: f7f5 fc5d bl 800017c <__adddf3> + 800a8c2: 4642 mov r2, r8 + 800a8c4: 464b mov r3, r9 + 800a8c6: f7f5 fe0f bl 80004e8 <__aeabi_dmul> + 800a8ca: 4602 mov r2, r0 + 800a8cc: 460b mov r3, r1 + 800a8ce: e9dd 0104 ldrd r0, r1, [sp, #16] + 800a8d2: f7f5 fc53 bl 800017c <__adddf3> + 800a8d6: f5a5 26c2 sub.w r6, r5, #397312 ; 0x61000 + 800a8da: f5c5 25d7 rsb r5, r5, #440320 ; 0x6b800 + 800a8de: f2a6 467a subw r6, r6, #1146 ; 0x47a + 800a8e2: 3551 adds r5, #81 ; 0x51 + 800a8e4: 4335 orrs r5, r6 + 800a8e6: 2d00 cmp r5, #0 + 800a8e8: 4680 mov r8, r0 + 800a8ea: 4689 mov r9, r1 + 800a8ec: dd48 ble.n 800a980 <__ieee754_log+0x2b8> + 800a8ee: 2200 movs r2, #0 + 800a8f0: 4b4d ldr r3, [pc, #308] ; (800aa28 <__ieee754_log+0x360>) + 800a8f2: 4650 mov r0, sl + 800a8f4: 4659 mov r1, fp + 800a8f6: f7f5 fdf7 bl 80004e8 <__aeabi_dmul> + 800a8fa: 4652 mov r2, sl + 800a8fc: 465b mov r3, fp + 800a8fe: f7f5 fdf3 bl 80004e8 <__aeabi_dmul> + 800a902: 4602 mov r2, r0 + 800a904: 460b mov r3, r1 + 800a906: 4606 mov r6, r0 + 800a908: 460f mov r7, r1 + 800a90a: 4640 mov r0, r8 + 800a90c: 4649 mov r1, r9 + 800a90e: f7f5 fc35 bl 800017c <__adddf3> + 800a912: e9dd 2300 ldrd r2, r3, [sp] + 800a916: f7f5 fde7 bl 80004e8 <__aeabi_dmul> + 800a91a: 4680 mov r8, r0 + 800a91c: 4689 mov r9, r1 + 800a91e: b964 cbnz r4, 800a93a <__ieee754_log+0x272> + 800a920: 4602 mov r2, r0 + 800a922: 460b mov r3, r1 + 800a924: 4630 mov r0, r6 + 800a926: 4639 mov r1, r7 + 800a928: f7f5 fc26 bl 8000178 <__aeabi_dsub> + 800a92c: 4602 mov r2, r0 + 800a92e: 460b mov r3, r1 + 800a930: 4650 mov r0, sl + 800a932: 4659 mov r1, fp + 800a934: f7f5 fc20 bl 8000178 <__aeabi_dsub> + 800a938: e6d9 b.n 800a6ee <__ieee754_log+0x26> + 800a93a: a323 add r3, pc, #140 ; (adr r3, 800a9c8 <__ieee754_log+0x300>) + 800a93c: e9d3 2300 ldrd r2, r3, [r3] + 800a940: e9dd 0102 ldrd r0, r1, [sp, #8] + 800a944: f7f5 fdd0 bl 80004e8 <__aeabi_dmul> + 800a948: a321 add r3, pc, #132 ; (adr r3, 800a9d0 <__ieee754_log+0x308>) + 800a94a: e9d3 2300 ldrd r2, r3, [r3] + 800a94e: 4604 mov r4, r0 + 800a950: 460d mov r5, r1 + 800a952: e9dd 0102 ldrd r0, r1, [sp, #8] + 800a956: f7f5 fdc7 bl 80004e8 <__aeabi_dmul> + 800a95a: 4642 mov r2, r8 + 800a95c: 464b mov r3, r9 + 800a95e: f7f5 fc0d bl 800017c <__adddf3> + 800a962: 4602 mov r2, r0 + 800a964: 460b mov r3, r1 + 800a966: 4630 mov r0, r6 + 800a968: 4639 mov r1, r7 + 800a96a: f7f5 fc05 bl 8000178 <__aeabi_dsub> + 800a96e: 4652 mov r2, sl + 800a970: 465b mov r3, fp + 800a972: f7f5 fc01 bl 8000178 <__aeabi_dsub> + 800a976: 4602 mov r2, r0 + 800a978: 460b mov r3, r1 + 800a97a: 4620 mov r0, r4 + 800a97c: 4629 mov r1, r5 + 800a97e: e7d9 b.n 800a934 <__ieee754_log+0x26c> + 800a980: 4602 mov r2, r0 + 800a982: 460b mov r3, r1 + 800a984: 4650 mov r0, sl + 800a986: 4659 mov r1, fp + 800a988: f7f5 fbf6 bl 8000178 <__aeabi_dsub> + 800a98c: e9dd 2300 ldrd r2, r3, [sp] + 800a990: f7f5 fdaa bl 80004e8 <__aeabi_dmul> + 800a994: 4606 mov r6, r0 + 800a996: 460f mov r7, r1 + 800a998: 2c00 cmp r4, #0 + 800a99a: f43f af25 beq.w 800a7e8 <__ieee754_log+0x120> + 800a99e: a30a add r3, pc, #40 ; (adr r3, 800a9c8 <__ieee754_log+0x300>) + 800a9a0: e9d3 2300 ldrd r2, r3, [r3] + 800a9a4: e9dd 0102 ldrd r0, r1, [sp, #8] + 800a9a8: f7f5 fd9e bl 80004e8 <__aeabi_dmul> + 800a9ac: a308 add r3, pc, #32 ; (adr r3, 800a9d0 <__ieee754_log+0x308>) + 800a9ae: e9d3 2300 ldrd r2, r3, [r3] + 800a9b2: 4604 mov r4, r0 + 800a9b4: 460d mov r5, r1 + 800a9b6: e9dd 0102 ldrd r0, r1, [sp, #8] + 800a9ba: e729 b.n 800a810 <__ieee754_log+0x148> + 800a9bc: 2000 movs r0, #0 + 800a9be: 2100 movs r1, #0 + 800a9c0: e695 b.n 800a6ee <__ieee754_log+0x26> + 800a9c2: bf00 nop + 800a9c4: f3af 8000 nop.w + 800a9c8: fee00000 .word 0xfee00000 + 800a9cc: 3fe62e42 .word 0x3fe62e42 + 800a9d0: 35793c76 .word 0x35793c76 + 800a9d4: 3dea39ef .word 0x3dea39ef + 800a9d8: 55555555 .word 0x55555555 + 800a9dc: 3fd55555 .word 0x3fd55555 + 800a9e0: df3e5244 .word 0xdf3e5244 + 800a9e4: 3fc2f112 .word 0x3fc2f112 + 800a9e8: 96cb03de .word 0x96cb03de + 800a9ec: 3fc74664 .word 0x3fc74664 + 800a9f0: 94229359 .word 0x94229359 + 800a9f4: 3fd24924 .word 0x3fd24924 + 800a9f8: 55555593 .word 0x55555593 + 800a9fc: 3fe55555 .word 0x3fe55555 + 800aa00: d078c69f .word 0xd078c69f + 800aa04: 3fc39a09 .word 0x3fc39a09 + 800aa08: 1d8e78af .word 0x1d8e78af + 800aa0c: 3fcc71c5 .word 0x3fcc71c5 + 800aa10: 9997fa04 .word 0x9997fa04 + 800aa14: 3fd99999 .word 0x3fd99999 + 800aa18: c3500000 .word 0xc3500000 + 800aa1c: 43500000 .word 0x43500000 + 800aa20: 7fefffff .word 0x7fefffff + 800aa24: 3ff00000 .word 0x3ff00000 + 800aa28: 3fe00000 .word 0x3fe00000 + 800aa2c: 00000000 .word 0x00000000 + +0800aa30 <__ieee754_pow>: + 800aa30: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800aa34: b091 sub sp, #68 ; 0x44 + 800aa36: e9cd 2302 strd r2, r3, [sp, #8] + 800aa3a: e9dd 2602 ldrd r2, r6, [sp, #8] + 800aa3e: f026 4500 bic.w r5, r6, #2147483648 ; 0x80000000 + 800aa42: ea55 0302 orrs.w r3, r5, r2 + 800aa46: 4607 mov r7, r0 + 800aa48: 4688 mov r8, r1 + 800aa4a: f000 84b7 beq.w 800b3bc <__ieee754_pow+0x98c> + 800aa4e: 4b80 ldr r3, [pc, #512] ; (800ac50 <__ieee754_pow+0x220>) + 800aa50: f021 4400 bic.w r4, r1, #2147483648 ; 0x80000000 + 800aa54: 429c cmp r4, r3 + 800aa56: 4689 mov r9, r1 + 800aa58: 4682 mov sl, r0 + 800aa5a: dc09 bgt.n 800aa70 <__ieee754_pow+0x40> + 800aa5c: d103 bne.n 800aa66 <__ieee754_pow+0x36> + 800aa5e: b938 cbnz r0, 800aa70 <__ieee754_pow+0x40> + 800aa60: 42a5 cmp r5, r4 + 800aa62: dc0d bgt.n 800aa80 <__ieee754_pow+0x50> + 800aa64: e001 b.n 800aa6a <__ieee754_pow+0x3a> + 800aa66: 429d cmp r5, r3 + 800aa68: dc02 bgt.n 800aa70 <__ieee754_pow+0x40> + 800aa6a: 429d cmp r5, r3 + 800aa6c: d10e bne.n 800aa8c <__ieee754_pow+0x5c> + 800aa6e: b16a cbz r2, 800aa8c <__ieee754_pow+0x5c> + 800aa70: f104 4440 add.w r4, r4, #3221225472 ; 0xc0000000 + 800aa74: f504 1480 add.w r4, r4, #1048576 ; 0x100000 + 800aa78: ea54 030a orrs.w r3, r4, sl + 800aa7c: f000 849e beq.w 800b3bc <__ieee754_pow+0x98c> + 800aa80: 4874 ldr r0, [pc, #464] ; (800ac54 <__ieee754_pow+0x224>) + 800aa82: b011 add sp, #68 ; 0x44 + 800aa84: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800aa88: f001 be88 b.w 800c79c + 800aa8c: f1b9 0f00 cmp.w r9, #0 + 800aa90: da53 bge.n 800ab3a <__ieee754_pow+0x10a> + 800aa92: 4b71 ldr r3, [pc, #452] ; (800ac58 <__ieee754_pow+0x228>) + 800aa94: 429d cmp r5, r3 + 800aa96: dc4e bgt.n 800ab36 <__ieee754_pow+0x106> + 800aa98: f1a3 7354 sub.w r3, r3, #55574528 ; 0x3500000 + 800aa9c: 429d cmp r5, r3 + 800aa9e: dd4c ble.n 800ab3a <__ieee754_pow+0x10a> + 800aaa0: 152b asrs r3, r5, #20 + 800aaa2: f2a3 33ff subw r3, r3, #1023 ; 0x3ff + 800aaa6: 2b14 cmp r3, #20 + 800aaa8: dd28 ble.n 800aafc <__ieee754_pow+0xcc> + 800aaaa: f1c3 0334 rsb r3, r3, #52 ; 0x34 + 800aaae: fa22 f103 lsr.w r1, r2, r3 + 800aab2: fa01 f303 lsl.w r3, r1, r3 + 800aab6: 4293 cmp r3, r2 + 800aab8: d13f bne.n 800ab3a <__ieee754_pow+0x10a> + 800aaba: f001 0101 and.w r1, r1, #1 + 800aabe: f1c1 0302 rsb r3, r1, #2 + 800aac2: 9300 str r3, [sp, #0] + 800aac4: 2a00 cmp r2, #0 + 800aac6: d15c bne.n 800ab82 <__ieee754_pow+0x152> + 800aac8: 4b61 ldr r3, [pc, #388] ; (800ac50 <__ieee754_pow+0x220>) + 800aaca: 429d cmp r5, r3 + 800aacc: d126 bne.n 800ab1c <__ieee754_pow+0xec> + 800aace: f104 4340 add.w r3, r4, #3221225472 ; 0xc0000000 + 800aad2: f503 1380 add.w r3, r3, #1048576 ; 0x100000 + 800aad6: ea53 030a orrs.w r3, r3, sl + 800aada: f000 846f beq.w 800b3bc <__ieee754_pow+0x98c> + 800aade: 4b5f ldr r3, [pc, #380] ; (800ac5c <__ieee754_pow+0x22c>) + 800aae0: 429c cmp r4, r3 + 800aae2: dd2c ble.n 800ab3e <__ieee754_pow+0x10e> + 800aae4: 2e00 cmp r6, #0 + 800aae6: f280 846f bge.w 800b3c8 <__ieee754_pow+0x998> + 800aaea: f04f 0b00 mov.w fp, #0 + 800aaee: f04f 0c00 mov.w ip, #0 + 800aaf2: 4658 mov r0, fp + 800aaf4: 4661 mov r1, ip + 800aaf6: b011 add sp, #68 ; 0x44 + 800aaf8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800aafc: 2a00 cmp r2, #0 + 800aafe: d13e bne.n 800ab7e <__ieee754_pow+0x14e> + 800ab00: f1c3 0314 rsb r3, r3, #20 + 800ab04: fa45 f103 asr.w r1, r5, r3 + 800ab08: fa01 f303 lsl.w r3, r1, r3 + 800ab0c: 42ab cmp r3, r5 + 800ab0e: f040 8463 bne.w 800b3d8 <__ieee754_pow+0x9a8> + 800ab12: f001 0101 and.w r1, r1, #1 + 800ab16: f1c1 0302 rsb r3, r1, #2 + 800ab1a: 9300 str r3, [sp, #0] + 800ab1c: 4b50 ldr r3, [pc, #320] ; (800ac60 <__ieee754_pow+0x230>) + 800ab1e: 429d cmp r5, r3 + 800ab20: d114 bne.n 800ab4c <__ieee754_pow+0x11c> + 800ab22: 2e00 cmp r6, #0 + 800ab24: f280 8454 bge.w 800b3d0 <__ieee754_pow+0x9a0> + 800ab28: 463a mov r2, r7 + 800ab2a: 4643 mov r3, r8 + 800ab2c: 2000 movs r0, #0 + 800ab2e: 494c ldr r1, [pc, #304] ; (800ac60 <__ieee754_pow+0x230>) + 800ab30: f7f5 fe04 bl 800073c <__aeabi_ddiv> + 800ab34: e013 b.n 800ab5e <__ieee754_pow+0x12e> + 800ab36: 2302 movs r3, #2 + 800ab38: e7c3 b.n 800aac2 <__ieee754_pow+0x92> + 800ab3a: 2300 movs r3, #0 + 800ab3c: e7c1 b.n 800aac2 <__ieee754_pow+0x92> + 800ab3e: 2e00 cmp r6, #0 + 800ab40: dad3 bge.n 800aaea <__ieee754_pow+0xba> + 800ab42: e9dd b302 ldrd fp, r3, [sp, #8] + 800ab46: f103 4c00 add.w ip, r3, #2147483648 ; 0x80000000 + 800ab4a: e7d2 b.n 800aaf2 <__ieee754_pow+0xc2> + 800ab4c: f1b6 4f80 cmp.w r6, #1073741824 ; 0x40000000 + 800ab50: d108 bne.n 800ab64 <__ieee754_pow+0x134> + 800ab52: 463a mov r2, r7 + 800ab54: 4643 mov r3, r8 + 800ab56: 4638 mov r0, r7 + 800ab58: 4641 mov r1, r8 + 800ab5a: f7f5 fcc5 bl 80004e8 <__aeabi_dmul> + 800ab5e: 4683 mov fp, r0 + 800ab60: 468c mov ip, r1 + 800ab62: e7c6 b.n 800aaf2 <__ieee754_pow+0xc2> + 800ab64: 4b3f ldr r3, [pc, #252] ; (800ac64 <__ieee754_pow+0x234>) + 800ab66: 429e cmp r6, r3 + 800ab68: d10b bne.n 800ab82 <__ieee754_pow+0x152> + 800ab6a: f1b9 0f00 cmp.w r9, #0 + 800ab6e: db08 blt.n 800ab82 <__ieee754_pow+0x152> + 800ab70: 4638 mov r0, r7 + 800ab72: 4641 mov r1, r8 + 800ab74: b011 add sp, #68 ; 0x44 + 800ab76: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800ab7a: f000 be55 b.w 800b828 <__ieee754_sqrt> + 800ab7e: 2300 movs r3, #0 + 800ab80: 9300 str r3, [sp, #0] + 800ab82: 4638 mov r0, r7 + 800ab84: 4641 mov r1, r8 + 800ab86: f7ff f8bb bl 8009d00 + 800ab8a: 4683 mov fp, r0 + 800ab8c: 468c mov ip, r1 + 800ab8e: f1ba 0f00 cmp.w sl, #0 + 800ab92: d12b bne.n 800abec <__ieee754_pow+0x1bc> + 800ab94: b124 cbz r4, 800aba0 <__ieee754_pow+0x170> + 800ab96: 4b32 ldr r3, [pc, #200] ; (800ac60 <__ieee754_pow+0x230>) + 800ab98: f029 4240 bic.w r2, r9, #3221225472 ; 0xc0000000 + 800ab9c: 429a cmp r2, r3 + 800ab9e: d125 bne.n 800abec <__ieee754_pow+0x1bc> + 800aba0: 2e00 cmp r6, #0 + 800aba2: da07 bge.n 800abb4 <__ieee754_pow+0x184> + 800aba4: 465a mov r2, fp + 800aba6: 4663 mov r3, ip + 800aba8: 2000 movs r0, #0 + 800abaa: 492d ldr r1, [pc, #180] ; (800ac60 <__ieee754_pow+0x230>) + 800abac: f7f5 fdc6 bl 800073c <__aeabi_ddiv> + 800abb0: 4683 mov fp, r0 + 800abb2: 468c mov ip, r1 + 800abb4: f1b9 0f00 cmp.w r9, #0 + 800abb8: da9b bge.n 800aaf2 <__ieee754_pow+0xc2> + 800abba: f104 4440 add.w r4, r4, #3221225472 ; 0xc0000000 + 800abbe: 9b00 ldr r3, [sp, #0] + 800abc0: f504 1480 add.w r4, r4, #1048576 ; 0x100000 + 800abc4: 4323 orrs r3, r4 + 800abc6: d108 bne.n 800abda <__ieee754_pow+0x1aa> + 800abc8: 465a mov r2, fp + 800abca: 4663 mov r3, ip + 800abcc: 4658 mov r0, fp + 800abce: 4661 mov r1, ip + 800abd0: f7f5 fad2 bl 8000178 <__aeabi_dsub> + 800abd4: 4602 mov r2, r0 + 800abd6: 460b mov r3, r1 + 800abd8: e7aa b.n 800ab30 <__ieee754_pow+0x100> + 800abda: 9b00 ldr r3, [sp, #0] + 800abdc: 2b01 cmp r3, #1 + 800abde: d188 bne.n 800aaf2 <__ieee754_pow+0xc2> + 800abe0: 4658 mov r0, fp + 800abe2: f10c 4300 add.w r3, ip, #2147483648 ; 0x80000000 + 800abe6: 4683 mov fp, r0 + 800abe8: 469c mov ip, r3 + 800abea: e782 b.n 800aaf2 <__ieee754_pow+0xc2> + 800abec: ea4f 79d9 mov.w r9, r9, lsr #31 + 800abf0: f109 33ff add.w r3, r9, #4294967295 + 800abf4: 930d str r3, [sp, #52] ; 0x34 + 800abf6: 9a0d ldr r2, [sp, #52] ; 0x34 + 800abf8: 9b00 ldr r3, [sp, #0] + 800abfa: 4313 orrs r3, r2 + 800abfc: d104 bne.n 800ac08 <__ieee754_pow+0x1d8> + 800abfe: 463a mov r2, r7 + 800ac00: 4643 mov r3, r8 + 800ac02: 4638 mov r0, r7 + 800ac04: 4641 mov r1, r8 + 800ac06: e7e3 b.n 800abd0 <__ieee754_pow+0x1a0> + 800ac08: 4b17 ldr r3, [pc, #92] ; (800ac68 <__ieee754_pow+0x238>) + 800ac0a: 429d cmp r5, r3 + 800ac0c: f340 80fe ble.w 800ae0c <__ieee754_pow+0x3dc> + 800ac10: f103 7304 add.w r3, r3, #34603008 ; 0x2100000 + 800ac14: 429d cmp r5, r3 + 800ac16: dd0b ble.n 800ac30 <__ieee754_pow+0x200> + 800ac18: 4b10 ldr r3, [pc, #64] ; (800ac5c <__ieee754_pow+0x22c>) + 800ac1a: 429c cmp r4, r3 + 800ac1c: dc0e bgt.n 800ac3c <__ieee754_pow+0x20c> + 800ac1e: 2e00 cmp r6, #0 + 800ac20: f6bf af63 bge.w 800aaea <__ieee754_pow+0xba> + 800ac24: a308 add r3, pc, #32 ; (adr r3, 800ac48 <__ieee754_pow+0x218>) + 800ac26: e9d3 2300 ldrd r2, r3, [r3] + 800ac2a: 4610 mov r0, r2 + 800ac2c: 4619 mov r1, r3 + 800ac2e: e794 b.n 800ab5a <__ieee754_pow+0x12a> + 800ac30: 4b0e ldr r3, [pc, #56] ; (800ac6c <__ieee754_pow+0x23c>) + 800ac32: 429c cmp r4, r3 + 800ac34: ddf3 ble.n 800ac1e <__ieee754_pow+0x1ee> + 800ac36: 4b0a ldr r3, [pc, #40] ; (800ac60 <__ieee754_pow+0x230>) + 800ac38: 429c cmp r4, r3 + 800ac3a: dd19 ble.n 800ac70 <__ieee754_pow+0x240> + 800ac3c: 2e00 cmp r6, #0 + 800ac3e: dcf1 bgt.n 800ac24 <__ieee754_pow+0x1f4> + 800ac40: e753 b.n 800aaea <__ieee754_pow+0xba> + 800ac42: bf00 nop + 800ac44: f3af 8000 nop.w + 800ac48: 8800759c .word 0x8800759c + 800ac4c: 7e37e43c .word 0x7e37e43c + 800ac50: 7ff00000 .word 0x7ff00000 + 800ac54: 0800e590 .word 0x0800e590 + 800ac58: 433fffff .word 0x433fffff + 800ac5c: 3fefffff .word 0x3fefffff + 800ac60: 3ff00000 .word 0x3ff00000 + 800ac64: 3fe00000 .word 0x3fe00000 + 800ac68: 41e00000 .word 0x41e00000 + 800ac6c: 3feffffe .word 0x3feffffe + 800ac70: 4661 mov r1, ip + 800ac72: 2200 movs r2, #0 + 800ac74: 4b60 ldr r3, [pc, #384] ; (800adf8 <__ieee754_pow+0x3c8>) + 800ac76: 4658 mov r0, fp + 800ac78: f7f5 fa7e bl 8000178 <__aeabi_dsub> + 800ac7c: a354 add r3, pc, #336 ; (adr r3, 800add0 <__ieee754_pow+0x3a0>) + 800ac7e: e9d3 2300 ldrd r2, r3, [r3] + 800ac82: 4604 mov r4, r0 + 800ac84: 460d mov r5, r1 + 800ac86: f7f5 fc2f bl 80004e8 <__aeabi_dmul> + 800ac8a: a353 add r3, pc, #332 ; (adr r3, 800add8 <__ieee754_pow+0x3a8>) + 800ac8c: e9d3 2300 ldrd r2, r3, [r3] + 800ac90: 4606 mov r6, r0 + 800ac92: 460f mov r7, r1 + 800ac94: 4620 mov r0, r4 + 800ac96: 4629 mov r1, r5 + 800ac98: f7f5 fc26 bl 80004e8 <__aeabi_dmul> + 800ac9c: 2200 movs r2, #0 + 800ac9e: 4682 mov sl, r0 + 800aca0: 468b mov fp, r1 + 800aca2: 4b56 ldr r3, [pc, #344] ; (800adfc <__ieee754_pow+0x3cc>) + 800aca4: 4620 mov r0, r4 + 800aca6: 4629 mov r1, r5 + 800aca8: f7f5 fc1e bl 80004e8 <__aeabi_dmul> + 800acac: 4602 mov r2, r0 + 800acae: 460b mov r3, r1 + 800acb0: a14b add r1, pc, #300 ; (adr r1, 800ade0 <__ieee754_pow+0x3b0>) + 800acb2: e9d1 0100 ldrd r0, r1, [r1] + 800acb6: f7f5 fa5f bl 8000178 <__aeabi_dsub> + 800acba: 4622 mov r2, r4 + 800acbc: 462b mov r3, r5 + 800acbe: f7f5 fc13 bl 80004e8 <__aeabi_dmul> + 800acc2: 4602 mov r2, r0 + 800acc4: 460b mov r3, r1 + 800acc6: 2000 movs r0, #0 + 800acc8: 494d ldr r1, [pc, #308] ; (800ae00 <__ieee754_pow+0x3d0>) + 800acca: f7f5 fa55 bl 8000178 <__aeabi_dsub> + 800acce: 4622 mov r2, r4 + 800acd0: 462b mov r3, r5 + 800acd2: 4680 mov r8, r0 + 800acd4: 4689 mov r9, r1 + 800acd6: 4620 mov r0, r4 + 800acd8: 4629 mov r1, r5 + 800acda: f7f5 fc05 bl 80004e8 <__aeabi_dmul> + 800acde: 4602 mov r2, r0 + 800ace0: 460b mov r3, r1 + 800ace2: 4640 mov r0, r8 + 800ace4: 4649 mov r1, r9 + 800ace6: f7f5 fbff bl 80004e8 <__aeabi_dmul> + 800acea: a33f add r3, pc, #252 ; (adr r3, 800ade8 <__ieee754_pow+0x3b8>) + 800acec: e9d3 2300 ldrd r2, r3, [r3] + 800acf0: f7f5 fbfa bl 80004e8 <__aeabi_dmul> + 800acf4: 4602 mov r2, r0 + 800acf6: 460b mov r3, r1 + 800acf8: 4650 mov r0, sl + 800acfa: 4659 mov r1, fp + 800acfc: f7f5 fa3c bl 8000178 <__aeabi_dsub> + 800ad00: 4602 mov r2, r0 + 800ad02: 460b mov r3, r1 + 800ad04: 4604 mov r4, r0 + 800ad06: 460d mov r5, r1 + 800ad08: 4630 mov r0, r6 + 800ad0a: 4639 mov r1, r7 + 800ad0c: f7f5 fa36 bl 800017c <__adddf3> + 800ad10: 2000 movs r0, #0 + 800ad12: 468b mov fp, r1 + 800ad14: 4682 mov sl, r0 + 800ad16: 4632 mov r2, r6 + 800ad18: 463b mov r3, r7 + 800ad1a: f7f5 fa2d bl 8000178 <__aeabi_dsub> + 800ad1e: 4602 mov r2, r0 + 800ad20: 460b mov r3, r1 + 800ad22: 4620 mov r0, r4 + 800ad24: 4629 mov r1, r5 + 800ad26: f7f5 fa27 bl 8000178 <__aeabi_dsub> + 800ad2a: 9b00 ldr r3, [sp, #0] + 800ad2c: 9a0d ldr r2, [sp, #52] ; 0x34 + 800ad2e: 3b01 subs r3, #1 + 800ad30: 4313 orrs r3, r2 + 800ad32: f04f 0300 mov.w r3, #0 + 800ad36: bf0c ite eq + 800ad38: 4c32 ldreq r4, [pc, #200] ; (800ae04 <__ieee754_pow+0x3d4>) + 800ad3a: 4c2f ldrne r4, [pc, #188] ; (800adf8 <__ieee754_pow+0x3c8>) + 800ad3c: 4606 mov r6, r0 + 800ad3e: e9cd 3400 strd r3, r4, [sp] + 800ad42: e9dd 4502 ldrd r4, r5, [sp, #8] + 800ad46: 2400 movs r4, #0 + 800ad48: 460f mov r7, r1 + 800ad4a: e9dd 0102 ldrd r0, r1, [sp, #8] + 800ad4e: 4622 mov r2, r4 + 800ad50: 462b mov r3, r5 + 800ad52: f7f5 fa11 bl 8000178 <__aeabi_dsub> + 800ad56: 4652 mov r2, sl + 800ad58: 465b mov r3, fp + 800ad5a: f7f5 fbc5 bl 80004e8 <__aeabi_dmul> + 800ad5e: e9dd 2302 ldrd r2, r3, [sp, #8] + 800ad62: 4680 mov r8, r0 + 800ad64: 4689 mov r9, r1 + 800ad66: 4630 mov r0, r6 + 800ad68: 4639 mov r1, r7 + 800ad6a: f7f5 fbbd bl 80004e8 <__aeabi_dmul> + 800ad6e: 4602 mov r2, r0 + 800ad70: 460b mov r3, r1 + 800ad72: 4640 mov r0, r8 + 800ad74: 4649 mov r1, r9 + 800ad76: f7f5 fa01 bl 800017c <__adddf3> + 800ad7a: 4622 mov r2, r4 + 800ad7c: 462b mov r3, r5 + 800ad7e: 4680 mov r8, r0 + 800ad80: 4689 mov r9, r1 + 800ad82: 4650 mov r0, sl + 800ad84: 4659 mov r1, fp + 800ad86: f7f5 fbaf bl 80004e8 <__aeabi_dmul> + 800ad8a: 4604 mov r4, r0 + 800ad8c: 460d mov r5, r1 + 800ad8e: 460b mov r3, r1 + 800ad90: 4602 mov r2, r0 + 800ad92: 4649 mov r1, r9 + 800ad94: 4640 mov r0, r8 + 800ad96: e9cd 4502 strd r4, r5, [sp, #8] + 800ad9a: f7f5 f9ef bl 800017c <__adddf3> + 800ad9e: 4b1a ldr r3, [pc, #104] ; (800ae08 <__ieee754_pow+0x3d8>) + 800ada0: 4682 mov sl, r0 + 800ada2: 4299 cmp r1, r3 + 800ada4: 460f mov r7, r1 + 800ada6: 460e mov r6, r1 + 800ada8: f340 82e1 ble.w 800b36e <__ieee754_pow+0x93e> + 800adac: f101 433f add.w r3, r1, #3204448256 ; 0xbf000000 + 800adb0: f503 03e0 add.w r3, r3, #7340032 ; 0x700000 + 800adb4: 4303 orrs r3, r0 + 800adb6: f000 81db beq.w 800b170 <__ieee754_pow+0x740> + 800adba: a30d add r3, pc, #52 ; (adr r3, 800adf0 <__ieee754_pow+0x3c0>) + 800adbc: e9d3 2300 ldrd r2, r3, [r3] + 800adc0: e9dd 0100 ldrd r0, r1, [sp] + 800adc4: f7f5 fb90 bl 80004e8 <__aeabi_dmul> + 800adc8: a309 add r3, pc, #36 ; (adr r3, 800adf0 <__ieee754_pow+0x3c0>) + 800adca: e9d3 2300 ldrd r2, r3, [r3] + 800adce: e6c4 b.n 800ab5a <__ieee754_pow+0x12a> + 800add0: 60000000 .word 0x60000000 + 800add4: 3ff71547 .word 0x3ff71547 + 800add8: f85ddf44 .word 0xf85ddf44 + 800addc: 3e54ae0b .word 0x3e54ae0b + 800ade0: 55555555 .word 0x55555555 + 800ade4: 3fd55555 .word 0x3fd55555 + 800ade8: 652b82fe .word 0x652b82fe + 800adec: 3ff71547 .word 0x3ff71547 + 800adf0: 8800759c .word 0x8800759c + 800adf4: 7e37e43c .word 0x7e37e43c + 800adf8: 3ff00000 .word 0x3ff00000 + 800adfc: 3fd00000 .word 0x3fd00000 + 800ae00: 3fe00000 .word 0x3fe00000 + 800ae04: bff00000 .word 0xbff00000 + 800ae08: 408fffff .word 0x408fffff + 800ae0c: f5b4 1f80 cmp.w r4, #1048576 ; 0x100000 + 800ae10: f04f 0200 mov.w r2, #0 + 800ae14: da08 bge.n 800ae28 <__ieee754_pow+0x3f8> + 800ae16: 4658 mov r0, fp + 800ae18: 4bcd ldr r3, [pc, #820] ; (800b150 <__ieee754_pow+0x720>) + 800ae1a: 4661 mov r1, ip + 800ae1c: f7f5 fb64 bl 80004e8 <__aeabi_dmul> + 800ae20: f06f 0234 mvn.w r2, #52 ; 0x34 + 800ae24: 4683 mov fp, r0 + 800ae26: 460c mov r4, r1 + 800ae28: 1523 asrs r3, r4, #20 + 800ae2a: f2a3 33ff subw r3, r3, #1023 ; 0x3ff + 800ae2e: 4413 add r3, r2 + 800ae30: 930c str r3, [sp, #48] ; 0x30 + 800ae32: 4bc8 ldr r3, [pc, #800] ; (800b154 <__ieee754_pow+0x724>) + 800ae34: f3c4 0413 ubfx r4, r4, #0, #20 + 800ae38: f044 557f orr.w r5, r4, #1069547520 ; 0x3fc00000 + 800ae3c: 429c cmp r4, r3 + 800ae3e: f445 1540 orr.w r5, r5, #3145728 ; 0x300000 + 800ae42: dd08 ble.n 800ae56 <__ieee754_pow+0x426> + 800ae44: 4bc4 ldr r3, [pc, #784] ; (800b158 <__ieee754_pow+0x728>) + 800ae46: 429c cmp r4, r3 + 800ae48: f340 815b ble.w 800b102 <__ieee754_pow+0x6d2> + 800ae4c: 9b0c ldr r3, [sp, #48] ; 0x30 + 800ae4e: f5a5 1580 sub.w r5, r5, #1048576 ; 0x100000 + 800ae52: 3301 adds r3, #1 + 800ae54: 930c str r3, [sp, #48] ; 0x30 + 800ae56: f04f 0800 mov.w r8, #0 + 800ae5a: 4658 mov r0, fp + 800ae5c: 4629 mov r1, r5 + 800ae5e: 4bbf ldr r3, [pc, #764] ; (800b15c <__ieee754_pow+0x72c>) + 800ae60: ea4f 09c8 mov.w r9, r8, lsl #3 + 800ae64: 444b add r3, r9 + 800ae66: e9d3 3400 ldrd r3, r4, [r3] + 800ae6a: e9cd 3408 strd r3, r4, [sp, #32] + 800ae6e: 461a mov r2, r3 + 800ae70: 4623 mov r3, r4 + 800ae72: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 + 800ae76: f7f5 f97f bl 8000178 <__aeabi_dsub> + 800ae7a: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 + 800ae7e: 4606 mov r6, r0 + 800ae80: 460f mov r7, r1 + 800ae82: e9dd 0108 ldrd r0, r1, [sp, #32] + 800ae86: f7f5 f979 bl 800017c <__adddf3> + 800ae8a: 4602 mov r2, r0 + 800ae8c: 460b mov r3, r1 + 800ae8e: 2000 movs r0, #0 + 800ae90: 49b3 ldr r1, [pc, #716] ; (800b160 <__ieee754_pow+0x730>) + 800ae92: f7f5 fc53 bl 800073c <__aeabi_ddiv> + 800ae96: e9cd 010e strd r0, r1, [sp, #56] ; 0x38 + 800ae9a: 4602 mov r2, r0 + 800ae9c: 460b mov r3, r1 + 800ae9e: 4630 mov r0, r6 + 800aea0: 4639 mov r1, r7 + 800aea2: f7f5 fb21 bl 80004e8 <__aeabi_dmul> + 800aea6: e9cd 0106 strd r0, r1, [sp, #24] + 800aeaa: e9dd 3406 ldrd r3, r4, [sp, #24] + 800aeae: e9cd 3404 strd r3, r4, [sp, #16] + 800aeb2: 2300 movs r3, #0 + 800aeb4: 2200 movs r2, #0 + 800aeb6: 106d asrs r5, r5, #1 + 800aeb8: f045 5500 orr.w r5, r5, #536870912 ; 0x20000000 + 800aebc: 9304 str r3, [sp, #16] + 800aebe: f505 2500 add.w r5, r5, #524288 ; 0x80000 + 800aec2: e9dd ab04 ldrd sl, fp, [sp, #16] + 800aec6: eb05 4388 add.w r3, r5, r8, lsl #18 + 800aeca: 4650 mov r0, sl + 800aecc: 4659 mov r1, fp + 800aece: 4614 mov r4, r2 + 800aed0: 461d mov r5, r3 + 800aed2: f7f5 fb09 bl 80004e8 <__aeabi_dmul> + 800aed6: 4602 mov r2, r0 + 800aed8: 460b mov r3, r1 + 800aeda: 4630 mov r0, r6 + 800aedc: 4639 mov r1, r7 + 800aede: f7f5 f94b bl 8000178 <__aeabi_dsub> + 800aee2: e9dd 2308 ldrd r2, r3, [sp, #32] + 800aee6: 4606 mov r6, r0 + 800aee8: 460f mov r7, r1 + 800aeea: 4620 mov r0, r4 + 800aeec: 4629 mov r1, r5 + 800aeee: f7f5 f943 bl 8000178 <__aeabi_dsub> + 800aef2: 4602 mov r2, r0 + 800aef4: 460b mov r3, r1 + 800aef6: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 + 800aefa: f7f5 f93d bl 8000178 <__aeabi_dsub> + 800aefe: 4652 mov r2, sl + 800af00: 465b mov r3, fp + 800af02: f7f5 faf1 bl 80004e8 <__aeabi_dmul> + 800af06: 4602 mov r2, r0 + 800af08: 460b mov r3, r1 + 800af0a: 4630 mov r0, r6 + 800af0c: 4639 mov r1, r7 + 800af0e: f7f5 f933 bl 8000178 <__aeabi_dsub> + 800af12: e9dd 230e ldrd r2, r3, [sp, #56] ; 0x38 + 800af16: f7f5 fae7 bl 80004e8 <__aeabi_dmul> + 800af1a: e9dd 2306 ldrd r2, r3, [sp, #24] + 800af1e: e9cd 0108 strd r0, r1, [sp, #32] + 800af22: 4610 mov r0, r2 + 800af24: 4619 mov r1, r3 + 800af26: f7f5 fadf bl 80004e8 <__aeabi_dmul> + 800af2a: a377 add r3, pc, #476 ; (adr r3, 800b108 <__ieee754_pow+0x6d8>) + 800af2c: e9d3 2300 ldrd r2, r3, [r3] + 800af30: 4604 mov r4, r0 + 800af32: 460d mov r5, r1 + 800af34: f7f5 fad8 bl 80004e8 <__aeabi_dmul> + 800af38: a375 add r3, pc, #468 ; (adr r3, 800b110 <__ieee754_pow+0x6e0>) + 800af3a: e9d3 2300 ldrd r2, r3, [r3] + 800af3e: f7f5 f91d bl 800017c <__adddf3> + 800af42: 4622 mov r2, r4 + 800af44: 462b mov r3, r5 + 800af46: f7f5 facf bl 80004e8 <__aeabi_dmul> + 800af4a: a373 add r3, pc, #460 ; (adr r3, 800b118 <__ieee754_pow+0x6e8>) + 800af4c: e9d3 2300 ldrd r2, r3, [r3] + 800af50: f7f5 f914 bl 800017c <__adddf3> + 800af54: 4622 mov r2, r4 + 800af56: 462b mov r3, r5 + 800af58: f7f5 fac6 bl 80004e8 <__aeabi_dmul> + 800af5c: a370 add r3, pc, #448 ; (adr r3, 800b120 <__ieee754_pow+0x6f0>) + 800af5e: e9d3 2300 ldrd r2, r3, [r3] + 800af62: f7f5 f90b bl 800017c <__adddf3> + 800af66: 4622 mov r2, r4 + 800af68: 462b mov r3, r5 + 800af6a: f7f5 fabd bl 80004e8 <__aeabi_dmul> + 800af6e: a36e add r3, pc, #440 ; (adr r3, 800b128 <__ieee754_pow+0x6f8>) + 800af70: e9d3 2300 ldrd r2, r3, [r3] + 800af74: f7f5 f902 bl 800017c <__adddf3> + 800af78: 4622 mov r2, r4 + 800af7a: 462b mov r3, r5 + 800af7c: f7f5 fab4 bl 80004e8 <__aeabi_dmul> + 800af80: a36b add r3, pc, #428 ; (adr r3, 800b130 <__ieee754_pow+0x700>) + 800af82: e9d3 2300 ldrd r2, r3, [r3] + 800af86: f7f5 f8f9 bl 800017c <__adddf3> + 800af8a: 4622 mov r2, r4 + 800af8c: 4606 mov r6, r0 + 800af8e: 460f mov r7, r1 + 800af90: 462b mov r3, r5 + 800af92: 4620 mov r0, r4 + 800af94: 4629 mov r1, r5 + 800af96: f7f5 faa7 bl 80004e8 <__aeabi_dmul> + 800af9a: 4602 mov r2, r0 + 800af9c: 460b mov r3, r1 + 800af9e: 4630 mov r0, r6 + 800afa0: 4639 mov r1, r7 + 800afa2: f7f5 faa1 bl 80004e8 <__aeabi_dmul> + 800afa6: 4604 mov r4, r0 + 800afa8: 460d mov r5, r1 + 800afaa: e9dd 0106 ldrd r0, r1, [sp, #24] + 800afae: 4652 mov r2, sl + 800afb0: 465b mov r3, fp + 800afb2: f7f5 f8e3 bl 800017c <__adddf3> + 800afb6: e9dd 2308 ldrd r2, r3, [sp, #32] + 800afba: f7f5 fa95 bl 80004e8 <__aeabi_dmul> + 800afbe: 4622 mov r2, r4 + 800afc0: 462b mov r3, r5 + 800afc2: f7f5 f8db bl 800017c <__adddf3> + 800afc6: 4652 mov r2, sl + 800afc8: 4606 mov r6, r0 + 800afca: 460f mov r7, r1 + 800afcc: 465b mov r3, fp + 800afce: 4650 mov r0, sl + 800afd0: 4659 mov r1, fp + 800afd2: f7f5 fa89 bl 80004e8 <__aeabi_dmul> + 800afd6: 2200 movs r2, #0 + 800afd8: 4b62 ldr r3, [pc, #392] ; (800b164 <__ieee754_pow+0x734>) + 800afda: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 + 800afde: f7f5 f8cd bl 800017c <__adddf3> + 800afe2: 4632 mov r2, r6 + 800afe4: 463b mov r3, r7 + 800afe6: f7f5 f8c9 bl 800017c <__adddf3> + 800afea: 9804 ldr r0, [sp, #16] + 800afec: 460d mov r5, r1 + 800afee: 4604 mov r4, r0 + 800aff0: 4602 mov r2, r0 + 800aff2: 460b mov r3, r1 + 800aff4: 4650 mov r0, sl + 800aff6: 4659 mov r1, fp + 800aff8: f7f5 fa76 bl 80004e8 <__aeabi_dmul> + 800affc: 2200 movs r2, #0 + 800affe: 4682 mov sl, r0 + 800b000: 468b mov fp, r1 + 800b002: 4b58 ldr r3, [pc, #352] ; (800b164 <__ieee754_pow+0x734>) + 800b004: 4620 mov r0, r4 + 800b006: 4629 mov r1, r5 + 800b008: f7f5 f8b6 bl 8000178 <__aeabi_dsub> + 800b00c: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 + 800b010: f7f5 f8b2 bl 8000178 <__aeabi_dsub> + 800b014: 4602 mov r2, r0 + 800b016: 460b mov r3, r1 + 800b018: 4630 mov r0, r6 + 800b01a: 4639 mov r1, r7 + 800b01c: f7f5 f8ac bl 8000178 <__aeabi_dsub> + 800b020: e9dd 2306 ldrd r2, r3, [sp, #24] + 800b024: f7f5 fa60 bl 80004e8 <__aeabi_dmul> + 800b028: 4622 mov r2, r4 + 800b02a: 4606 mov r6, r0 + 800b02c: 460f mov r7, r1 + 800b02e: e9dd 0108 ldrd r0, r1, [sp, #32] + 800b032: 462b mov r3, r5 + 800b034: f7f5 fa58 bl 80004e8 <__aeabi_dmul> + 800b038: 4602 mov r2, r0 + 800b03a: 460b mov r3, r1 + 800b03c: 4630 mov r0, r6 + 800b03e: 4639 mov r1, r7 + 800b040: f7f5 f89c bl 800017c <__adddf3> + 800b044: 4606 mov r6, r0 + 800b046: 460f mov r7, r1 + 800b048: 4602 mov r2, r0 + 800b04a: 460b mov r3, r1 + 800b04c: 4650 mov r0, sl + 800b04e: 4659 mov r1, fp + 800b050: f7f5 f894 bl 800017c <__adddf3> + 800b054: a338 add r3, pc, #224 ; (adr r3, 800b138 <__ieee754_pow+0x708>) + 800b056: e9d3 2300 ldrd r2, r3, [r3] + 800b05a: 9804 ldr r0, [sp, #16] + 800b05c: 460d mov r5, r1 + 800b05e: 4604 mov r4, r0 + 800b060: f7f5 fa42 bl 80004e8 <__aeabi_dmul> + 800b064: 4652 mov r2, sl + 800b066: e9cd 0106 strd r0, r1, [sp, #24] + 800b06a: 465b mov r3, fp + 800b06c: 4620 mov r0, r4 + 800b06e: 4629 mov r1, r5 + 800b070: f7f5 f882 bl 8000178 <__aeabi_dsub> + 800b074: 4602 mov r2, r0 + 800b076: 460b mov r3, r1 + 800b078: 4630 mov r0, r6 + 800b07a: 4639 mov r1, r7 + 800b07c: f7f5 f87c bl 8000178 <__aeabi_dsub> + 800b080: a32f add r3, pc, #188 ; (adr r3, 800b140 <__ieee754_pow+0x710>) + 800b082: e9d3 2300 ldrd r2, r3, [r3] + 800b086: f7f5 fa2f bl 80004e8 <__aeabi_dmul> + 800b08a: a32f add r3, pc, #188 ; (adr r3, 800b148 <__ieee754_pow+0x718>) + 800b08c: e9d3 2300 ldrd r2, r3, [r3] + 800b090: 4606 mov r6, r0 + 800b092: 460f mov r7, r1 + 800b094: 4620 mov r0, r4 + 800b096: 4629 mov r1, r5 + 800b098: f7f5 fa26 bl 80004e8 <__aeabi_dmul> + 800b09c: 4602 mov r2, r0 + 800b09e: 460b mov r3, r1 + 800b0a0: 4630 mov r0, r6 + 800b0a2: 4639 mov r1, r7 + 800b0a4: f7f5 f86a bl 800017c <__adddf3> + 800b0a8: 4b2f ldr r3, [pc, #188] ; (800b168 <__ieee754_pow+0x738>) + 800b0aa: 444b add r3, r9 + 800b0ac: e9d3 2300 ldrd r2, r3, [r3] + 800b0b0: f7f5 f864 bl 800017c <__adddf3> + 800b0b4: 4604 mov r4, r0 + 800b0b6: 980c ldr r0, [sp, #48] ; 0x30 + 800b0b8: 460d mov r5, r1 + 800b0ba: f7f5 f9ab bl 8000414 <__aeabi_i2d> + 800b0be: 4606 mov r6, r0 + 800b0c0: 460f mov r7, r1 + 800b0c2: 4b2a ldr r3, [pc, #168] ; (800b16c <__ieee754_pow+0x73c>) + 800b0c4: 4622 mov r2, r4 + 800b0c6: 444b add r3, r9 + 800b0c8: e9d3 8900 ldrd r8, r9, [r3] + 800b0cc: 462b mov r3, r5 + 800b0ce: e9dd 0106 ldrd r0, r1, [sp, #24] + 800b0d2: f7f5 f853 bl 800017c <__adddf3> + 800b0d6: 4642 mov r2, r8 + 800b0d8: 464b mov r3, r9 + 800b0da: f7f5 f84f bl 800017c <__adddf3> + 800b0de: 4632 mov r2, r6 + 800b0e0: 463b mov r3, r7 + 800b0e2: f7f5 f84b bl 800017c <__adddf3> + 800b0e6: 9804 ldr r0, [sp, #16] + 800b0e8: 4632 mov r2, r6 + 800b0ea: 463b mov r3, r7 + 800b0ec: 4682 mov sl, r0 + 800b0ee: 468b mov fp, r1 + 800b0f0: f7f5 f842 bl 8000178 <__aeabi_dsub> + 800b0f4: 4642 mov r2, r8 + 800b0f6: 464b mov r3, r9 + 800b0f8: f7f5 f83e bl 8000178 <__aeabi_dsub> + 800b0fc: e9dd 2306 ldrd r2, r3, [sp, #24] + 800b100: e60b b.n 800ad1a <__ieee754_pow+0x2ea> + 800b102: f04f 0801 mov.w r8, #1 + 800b106: e6a8 b.n 800ae5a <__ieee754_pow+0x42a> + 800b108: 4a454eef .word 0x4a454eef + 800b10c: 3fca7e28 .word 0x3fca7e28 + 800b110: 93c9db65 .word 0x93c9db65 + 800b114: 3fcd864a .word 0x3fcd864a + 800b118: a91d4101 .word 0xa91d4101 + 800b11c: 3fd17460 .word 0x3fd17460 + 800b120: 518f264d .word 0x518f264d + 800b124: 3fd55555 .word 0x3fd55555 + 800b128: db6fabff .word 0xdb6fabff + 800b12c: 3fdb6db6 .word 0x3fdb6db6 + 800b130: 33333303 .word 0x33333303 + 800b134: 3fe33333 .word 0x3fe33333 + 800b138: e0000000 .word 0xe0000000 + 800b13c: 3feec709 .word 0x3feec709 + 800b140: dc3a03fd .word 0xdc3a03fd + 800b144: 3feec709 .word 0x3feec709 + 800b148: 145b01f5 .word 0x145b01f5 + 800b14c: be3e2fe0 .word 0xbe3e2fe0 + 800b150: 43400000 .word 0x43400000 + 800b154: 0003988e .word 0x0003988e + 800b158: 000bb679 .word 0x000bb679 + 800b15c: 0800e5a0 .word 0x0800e5a0 + 800b160: 3ff00000 .word 0x3ff00000 + 800b164: 40080000 .word 0x40080000 + 800b168: 0800e5c0 .word 0x0800e5c0 + 800b16c: 0800e5b0 .word 0x0800e5b0 + 800b170: a39b add r3, pc, #620 ; (adr r3, 800b3e0 <__ieee754_pow+0x9b0>) + 800b172: e9d3 2300 ldrd r2, r3, [r3] + 800b176: 4640 mov r0, r8 + 800b178: 4649 mov r1, r9 + 800b17a: f7f4 ffff bl 800017c <__adddf3> + 800b17e: 4622 mov r2, r4 + 800b180: e9cd 0104 strd r0, r1, [sp, #16] + 800b184: 462b mov r3, r5 + 800b186: 4650 mov r0, sl + 800b188: 4639 mov r1, r7 + 800b18a: f7f4 fff5 bl 8000178 <__aeabi_dsub> + 800b18e: 4602 mov r2, r0 + 800b190: 460b mov r3, r1 + 800b192: e9dd 0104 ldrd r0, r1, [sp, #16] + 800b196: f7f5 fc37 bl 8000a08 <__aeabi_dcmpgt> + 800b19a: 2800 cmp r0, #0 + 800b19c: f47f ae0d bne.w 800adba <__ieee754_pow+0x38a> + 800b1a0: 4aa3 ldr r2, [pc, #652] ; (800b430 <__ieee754_pow+0xa00>) + 800b1a2: f026 4300 bic.w r3, r6, #2147483648 ; 0x80000000 + 800b1a6: 4293 cmp r3, r2 + 800b1a8: f340 8103 ble.w 800b3b2 <__ieee754_pow+0x982> + 800b1ac: f44f 1a80 mov.w sl, #1048576 ; 0x100000 + 800b1b0: 2000 movs r0, #0 + 800b1b2: 151b asrs r3, r3, #20 + 800b1b4: f2a3 33fe subw r3, r3, #1022 ; 0x3fe + 800b1b8: fa4a f303 asr.w r3, sl, r3 + 800b1bc: 4433 add r3, r6 + 800b1be: f3c3 520a ubfx r2, r3, #20, #11 + 800b1c2: 4f9c ldr r7, [pc, #624] ; (800b434 <__ieee754_pow+0xa04>) + 800b1c4: f2a2 32ff subw r2, r2, #1023 ; 0x3ff + 800b1c8: 4117 asrs r7, r2 + 800b1ca: f3c3 0a13 ubfx sl, r3, #0, #20 + 800b1ce: ea23 0107 bic.w r1, r3, r7 + 800b1d2: f1c2 0214 rsb r2, r2, #20 + 800b1d6: f44a 1a80 orr.w sl, sl, #1048576 ; 0x100000 + 800b1da: fa4a fa02 asr.w sl, sl, r2 + 800b1de: 2e00 cmp r6, #0 + 800b1e0: 4602 mov r2, r0 + 800b1e2: 460b mov r3, r1 + 800b1e4: 4620 mov r0, r4 + 800b1e6: 4629 mov r1, r5 + 800b1e8: bfb8 it lt + 800b1ea: f1ca 0a00 rsblt sl, sl, #0 + 800b1ee: f7f4 ffc3 bl 8000178 <__aeabi_dsub> + 800b1f2: e9cd 0102 strd r0, r1, [sp, #8] + 800b1f6: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b1fa: 4642 mov r2, r8 + 800b1fc: 464b mov r3, r9 + 800b1fe: f7f4 ffbd bl 800017c <__adddf3> + 800b202: a379 add r3, pc, #484 ; (adr r3, 800b3e8 <__ieee754_pow+0x9b8>) + 800b204: e9d3 2300 ldrd r2, r3, [r3] + 800b208: 2000 movs r0, #0 + 800b20a: 460d mov r5, r1 + 800b20c: 4604 mov r4, r0 + 800b20e: f7f5 f96b bl 80004e8 <__aeabi_dmul> + 800b212: e9dd 2302 ldrd r2, r3, [sp, #8] + 800b216: 4606 mov r6, r0 + 800b218: 460f mov r7, r1 + 800b21a: 4620 mov r0, r4 + 800b21c: 4629 mov r1, r5 + 800b21e: f7f4 ffab bl 8000178 <__aeabi_dsub> + 800b222: 4602 mov r2, r0 + 800b224: 460b mov r3, r1 + 800b226: 4640 mov r0, r8 + 800b228: 4649 mov r1, r9 + 800b22a: f7f4 ffa5 bl 8000178 <__aeabi_dsub> + 800b22e: a370 add r3, pc, #448 ; (adr r3, 800b3f0 <__ieee754_pow+0x9c0>) + 800b230: e9d3 2300 ldrd r2, r3, [r3] + 800b234: f7f5 f958 bl 80004e8 <__aeabi_dmul> + 800b238: a36f add r3, pc, #444 ; (adr r3, 800b3f8 <__ieee754_pow+0x9c8>) + 800b23a: e9d3 2300 ldrd r2, r3, [r3] + 800b23e: 4680 mov r8, r0 + 800b240: 4689 mov r9, r1 + 800b242: 4620 mov r0, r4 + 800b244: 4629 mov r1, r5 + 800b246: f7f5 f94f bl 80004e8 <__aeabi_dmul> + 800b24a: 4602 mov r2, r0 + 800b24c: 460b mov r3, r1 + 800b24e: 4640 mov r0, r8 + 800b250: 4649 mov r1, r9 + 800b252: f7f4 ff93 bl 800017c <__adddf3> + 800b256: 4604 mov r4, r0 + 800b258: 460d mov r5, r1 + 800b25a: 4602 mov r2, r0 + 800b25c: 460b mov r3, r1 + 800b25e: 4630 mov r0, r6 + 800b260: 4639 mov r1, r7 + 800b262: f7f4 ff8b bl 800017c <__adddf3> + 800b266: 4632 mov r2, r6 + 800b268: 463b mov r3, r7 + 800b26a: 4680 mov r8, r0 + 800b26c: 4689 mov r9, r1 + 800b26e: f7f4 ff83 bl 8000178 <__aeabi_dsub> + 800b272: 4602 mov r2, r0 + 800b274: 460b mov r3, r1 + 800b276: 4620 mov r0, r4 + 800b278: 4629 mov r1, r5 + 800b27a: f7f4 ff7d bl 8000178 <__aeabi_dsub> + 800b27e: 4642 mov r2, r8 + 800b280: 4606 mov r6, r0 + 800b282: 460f mov r7, r1 + 800b284: 464b mov r3, r9 + 800b286: 4640 mov r0, r8 + 800b288: 4649 mov r1, r9 + 800b28a: f7f5 f92d bl 80004e8 <__aeabi_dmul> + 800b28e: a35c add r3, pc, #368 ; (adr r3, 800b400 <__ieee754_pow+0x9d0>) + 800b290: e9d3 2300 ldrd r2, r3, [r3] + 800b294: 4604 mov r4, r0 + 800b296: 460d mov r5, r1 + 800b298: f7f5 f926 bl 80004e8 <__aeabi_dmul> + 800b29c: a35a add r3, pc, #360 ; (adr r3, 800b408 <__ieee754_pow+0x9d8>) + 800b29e: e9d3 2300 ldrd r2, r3, [r3] + 800b2a2: f7f4 ff69 bl 8000178 <__aeabi_dsub> + 800b2a6: 4622 mov r2, r4 + 800b2a8: 462b mov r3, r5 + 800b2aa: f7f5 f91d bl 80004e8 <__aeabi_dmul> + 800b2ae: a358 add r3, pc, #352 ; (adr r3, 800b410 <__ieee754_pow+0x9e0>) + 800b2b0: e9d3 2300 ldrd r2, r3, [r3] + 800b2b4: f7f4 ff62 bl 800017c <__adddf3> + 800b2b8: 4622 mov r2, r4 + 800b2ba: 462b mov r3, r5 + 800b2bc: f7f5 f914 bl 80004e8 <__aeabi_dmul> + 800b2c0: a355 add r3, pc, #340 ; (adr r3, 800b418 <__ieee754_pow+0x9e8>) + 800b2c2: e9d3 2300 ldrd r2, r3, [r3] + 800b2c6: f7f4 ff57 bl 8000178 <__aeabi_dsub> + 800b2ca: 4622 mov r2, r4 + 800b2cc: 462b mov r3, r5 + 800b2ce: f7f5 f90b bl 80004e8 <__aeabi_dmul> + 800b2d2: a353 add r3, pc, #332 ; (adr r3, 800b420 <__ieee754_pow+0x9f0>) + 800b2d4: e9d3 2300 ldrd r2, r3, [r3] + 800b2d8: f7f4 ff50 bl 800017c <__adddf3> + 800b2dc: 4622 mov r2, r4 + 800b2de: 462b mov r3, r5 + 800b2e0: f7f5 f902 bl 80004e8 <__aeabi_dmul> + 800b2e4: 4602 mov r2, r0 + 800b2e6: 460b mov r3, r1 + 800b2e8: 4640 mov r0, r8 + 800b2ea: 4649 mov r1, r9 + 800b2ec: f7f4 ff44 bl 8000178 <__aeabi_dsub> + 800b2f0: 4604 mov r4, r0 + 800b2f2: 460d mov r5, r1 + 800b2f4: 4602 mov r2, r0 + 800b2f6: 460b mov r3, r1 + 800b2f8: 4640 mov r0, r8 + 800b2fa: 4649 mov r1, r9 + 800b2fc: f7f5 f8f4 bl 80004e8 <__aeabi_dmul> + 800b300: 2200 movs r2, #0 + 800b302: e9cd 0102 strd r0, r1, [sp, #8] + 800b306: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 800b30a: 4620 mov r0, r4 + 800b30c: 4629 mov r1, r5 + 800b30e: f7f4 ff33 bl 8000178 <__aeabi_dsub> + 800b312: 4602 mov r2, r0 + 800b314: 460b mov r3, r1 + 800b316: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b31a: f7f5 fa0f bl 800073c <__aeabi_ddiv> + 800b31e: 4632 mov r2, r6 + 800b320: 4604 mov r4, r0 + 800b322: 460d mov r5, r1 + 800b324: 463b mov r3, r7 + 800b326: 4640 mov r0, r8 + 800b328: 4649 mov r1, r9 + 800b32a: f7f5 f8dd bl 80004e8 <__aeabi_dmul> + 800b32e: 4632 mov r2, r6 + 800b330: 463b mov r3, r7 + 800b332: f7f4 ff23 bl 800017c <__adddf3> + 800b336: 4602 mov r2, r0 + 800b338: 460b mov r3, r1 + 800b33a: 4620 mov r0, r4 + 800b33c: 4629 mov r1, r5 + 800b33e: f7f4 ff1b bl 8000178 <__aeabi_dsub> + 800b342: 4642 mov r2, r8 + 800b344: 464b mov r3, r9 + 800b346: f7f4 ff17 bl 8000178 <__aeabi_dsub> + 800b34a: 4602 mov r2, r0 + 800b34c: 460b mov r3, r1 + 800b34e: 2000 movs r0, #0 + 800b350: 4939 ldr r1, [pc, #228] ; (800b438 <__ieee754_pow+0xa08>) + 800b352: f7f4 ff11 bl 8000178 <__aeabi_dsub> + 800b356: eb01 540a add.w r4, r1, sl, lsl #20 + 800b35a: f5b4 1f80 cmp.w r4, #1048576 ; 0x100000 + 800b35e: da2b bge.n 800b3b8 <__ieee754_pow+0x988> + 800b360: 4652 mov r2, sl + 800b362: f001 faad bl 800c8c0 + 800b366: e9dd 2300 ldrd r2, r3, [sp] + 800b36a: f7ff bbf6 b.w 800ab5a <__ieee754_pow+0x12a> + 800b36e: 4b33 ldr r3, [pc, #204] ; (800b43c <__ieee754_pow+0xa0c>) + 800b370: f021 4700 bic.w r7, r1, #2147483648 ; 0x80000000 + 800b374: 429f cmp r7, r3 + 800b376: f77f af13 ble.w 800b1a0 <__ieee754_pow+0x770> + 800b37a: 4b31 ldr r3, [pc, #196] ; (800b440 <__ieee754_pow+0xa10>) + 800b37c: 440b add r3, r1 + 800b37e: 4303 orrs r3, r0 + 800b380: d00b beq.n 800b39a <__ieee754_pow+0x96a> + 800b382: a329 add r3, pc, #164 ; (adr r3, 800b428 <__ieee754_pow+0x9f8>) + 800b384: e9d3 2300 ldrd r2, r3, [r3] + 800b388: e9dd 0100 ldrd r0, r1, [sp] + 800b38c: f7f5 f8ac bl 80004e8 <__aeabi_dmul> + 800b390: a325 add r3, pc, #148 ; (adr r3, 800b428 <__ieee754_pow+0x9f8>) + 800b392: e9d3 2300 ldrd r2, r3, [r3] + 800b396: f7ff bbe0 b.w 800ab5a <__ieee754_pow+0x12a> + 800b39a: 4622 mov r2, r4 + 800b39c: 462b mov r3, r5 + 800b39e: f7f4 feeb bl 8000178 <__aeabi_dsub> + 800b3a2: 4642 mov r2, r8 + 800b3a4: 464b mov r3, r9 + 800b3a6: f7f5 fb25 bl 80009f4 <__aeabi_dcmpge> + 800b3aa: 2800 cmp r0, #0 + 800b3ac: f43f aef8 beq.w 800b1a0 <__ieee754_pow+0x770> + 800b3b0: e7e7 b.n 800b382 <__ieee754_pow+0x952> + 800b3b2: f04f 0a00 mov.w sl, #0 + 800b3b6: e71e b.n 800b1f6 <__ieee754_pow+0x7c6> + 800b3b8: 4621 mov r1, r4 + 800b3ba: e7d4 b.n 800b366 <__ieee754_pow+0x936> + 800b3bc: f04f 0b00 mov.w fp, #0 + 800b3c0: f8df c074 ldr.w ip, [pc, #116] ; 800b438 <__ieee754_pow+0xa08> + 800b3c4: f7ff bb95 b.w 800aaf2 <__ieee754_pow+0xc2> + 800b3c8: e9dd bc02 ldrd fp, ip, [sp, #8] + 800b3cc: f7ff bb91 b.w 800aaf2 <__ieee754_pow+0xc2> + 800b3d0: 4638 mov r0, r7 + 800b3d2: 4641 mov r1, r8 + 800b3d4: f7ff bbc3 b.w 800ab5e <__ieee754_pow+0x12e> + 800b3d8: 9200 str r2, [sp, #0] + 800b3da: f7ff bb9f b.w 800ab1c <__ieee754_pow+0xec> + 800b3de: bf00 nop + 800b3e0: 652b82fe .word 0x652b82fe + 800b3e4: 3c971547 .word 0x3c971547 + 800b3e8: 00000000 .word 0x00000000 + 800b3ec: 3fe62e43 .word 0x3fe62e43 + 800b3f0: fefa39ef .word 0xfefa39ef + 800b3f4: 3fe62e42 .word 0x3fe62e42 + 800b3f8: 0ca86c39 .word 0x0ca86c39 + 800b3fc: be205c61 .word 0xbe205c61 + 800b400: 72bea4d0 .word 0x72bea4d0 + 800b404: 3e663769 .word 0x3e663769 + 800b408: c5d26bf1 .word 0xc5d26bf1 + 800b40c: 3ebbbd41 .word 0x3ebbbd41 + 800b410: af25de2c .word 0xaf25de2c + 800b414: 3f11566a .word 0x3f11566a + 800b418: 16bebd93 .word 0x16bebd93 + 800b41c: 3f66c16c .word 0x3f66c16c + 800b420: 5555553e .word 0x5555553e + 800b424: 3fc55555 .word 0x3fc55555 + 800b428: c2f8f359 .word 0xc2f8f359 + 800b42c: 01a56e1f .word 0x01a56e1f + 800b430: 3fe00000 .word 0x3fe00000 + 800b434: 000fffff .word 0x000fffff + 800b438: 3ff00000 .word 0x3ff00000 + 800b43c: 4090cbff .word 0x4090cbff + 800b440: 3f6f3400 .word 0x3f6f3400 + 800b444: 00000000 .word 0x00000000 + +0800b448 <__ieee754_rem_pio2>: + 800b448: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800b44c: 4614 mov r4, r2 + 800b44e: 4ac2 ldr r2, [pc, #776] ; (800b758 <__ieee754_rem_pio2+0x310>) + 800b450: f021 4a00 bic.w sl, r1, #2147483648 ; 0x80000000 + 800b454: 4592 cmp sl, r2 + 800b456: b08d sub sp, #52 ; 0x34 + 800b458: 468b mov fp, r1 + 800b45a: dc07 bgt.n 800b46c <__ieee754_rem_pio2+0x24> + 800b45c: 2200 movs r2, #0 + 800b45e: 2300 movs r3, #0 + 800b460: e9c4 0100 strd r0, r1, [r4] + 800b464: e9c4 2302 strd r2, r3, [r4, #8] + 800b468: 2500 movs r5, #0 + 800b46a: e023 b.n 800b4b4 <__ieee754_rem_pio2+0x6c> + 800b46c: 4abb ldr r2, [pc, #748] ; (800b75c <__ieee754_rem_pio2+0x314>) + 800b46e: 4592 cmp sl, r2 + 800b470: dc71 bgt.n 800b556 <__ieee754_rem_pio2+0x10e> + 800b472: a3ab add r3, pc, #684 ; (adr r3, 800b720 <__ieee754_rem_pio2+0x2d8>) + 800b474: e9d3 2300 ldrd r2, r3, [r3] + 800b478: 2900 cmp r1, #0 + 800b47a: 4db9 ldr r5, [pc, #740] ; (800b760 <__ieee754_rem_pio2+0x318>) + 800b47c: dd36 ble.n 800b4ec <__ieee754_rem_pio2+0xa4> + 800b47e: f7f4 fe7b bl 8000178 <__aeabi_dsub> + 800b482: 45aa cmp sl, r5 + 800b484: 4606 mov r6, r0 + 800b486: 460f mov r7, r1 + 800b488: d018 beq.n 800b4bc <__ieee754_rem_pio2+0x74> + 800b48a: a3a7 add r3, pc, #668 ; (adr r3, 800b728 <__ieee754_rem_pio2+0x2e0>) + 800b48c: e9d3 2300 ldrd r2, r3, [r3] + 800b490: f7f4 fe72 bl 8000178 <__aeabi_dsub> + 800b494: 4602 mov r2, r0 + 800b496: 460b mov r3, r1 + 800b498: 4630 mov r0, r6 + 800b49a: e9c4 2300 strd r2, r3, [r4] + 800b49e: 4639 mov r1, r7 + 800b4a0: f7f4 fe6a bl 8000178 <__aeabi_dsub> + 800b4a4: a3a0 add r3, pc, #640 ; (adr r3, 800b728 <__ieee754_rem_pio2+0x2e0>) + 800b4a6: e9d3 2300 ldrd r2, r3, [r3] + 800b4aa: f7f4 fe65 bl 8000178 <__aeabi_dsub> + 800b4ae: 2501 movs r5, #1 + 800b4b0: e9c4 0102 strd r0, r1, [r4, #8] + 800b4b4: 4628 mov r0, r5 + 800b4b6: b00d add sp, #52 ; 0x34 + 800b4b8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800b4bc: a39c add r3, pc, #624 ; (adr r3, 800b730 <__ieee754_rem_pio2+0x2e8>) + 800b4be: e9d3 2300 ldrd r2, r3, [r3] + 800b4c2: f7f4 fe59 bl 8000178 <__aeabi_dsub> + 800b4c6: a39c add r3, pc, #624 ; (adr r3, 800b738 <__ieee754_rem_pio2+0x2f0>) + 800b4c8: e9d3 2300 ldrd r2, r3, [r3] + 800b4cc: 4606 mov r6, r0 + 800b4ce: 460f mov r7, r1 + 800b4d0: f7f4 fe52 bl 8000178 <__aeabi_dsub> + 800b4d4: 4602 mov r2, r0 + 800b4d6: 460b mov r3, r1 + 800b4d8: 4630 mov r0, r6 + 800b4da: e9c4 2300 strd r2, r3, [r4] + 800b4de: 4639 mov r1, r7 + 800b4e0: f7f4 fe4a bl 8000178 <__aeabi_dsub> + 800b4e4: a394 add r3, pc, #592 ; (adr r3, 800b738 <__ieee754_rem_pio2+0x2f0>) + 800b4e6: e9d3 2300 ldrd r2, r3, [r3] + 800b4ea: e7de b.n 800b4aa <__ieee754_rem_pio2+0x62> + 800b4ec: f7f4 fe46 bl 800017c <__adddf3> + 800b4f0: 45aa cmp sl, r5 + 800b4f2: 4606 mov r6, r0 + 800b4f4: 460f mov r7, r1 + 800b4f6: d016 beq.n 800b526 <__ieee754_rem_pio2+0xde> + 800b4f8: a38b add r3, pc, #556 ; (adr r3, 800b728 <__ieee754_rem_pio2+0x2e0>) + 800b4fa: e9d3 2300 ldrd r2, r3, [r3] + 800b4fe: f7f4 fe3d bl 800017c <__adddf3> + 800b502: 4602 mov r2, r0 + 800b504: 460b mov r3, r1 + 800b506: 4630 mov r0, r6 + 800b508: e9c4 2300 strd r2, r3, [r4] + 800b50c: 4639 mov r1, r7 + 800b50e: f7f4 fe33 bl 8000178 <__aeabi_dsub> + 800b512: a385 add r3, pc, #532 ; (adr r3, 800b728 <__ieee754_rem_pio2+0x2e0>) + 800b514: e9d3 2300 ldrd r2, r3, [r3] + 800b518: f7f4 fe30 bl 800017c <__adddf3> + 800b51c: f04f 35ff mov.w r5, #4294967295 + 800b520: e9c4 0102 strd r0, r1, [r4, #8] + 800b524: e7c6 b.n 800b4b4 <__ieee754_rem_pio2+0x6c> + 800b526: a382 add r3, pc, #520 ; (adr r3, 800b730 <__ieee754_rem_pio2+0x2e8>) + 800b528: e9d3 2300 ldrd r2, r3, [r3] + 800b52c: f7f4 fe26 bl 800017c <__adddf3> + 800b530: a381 add r3, pc, #516 ; (adr r3, 800b738 <__ieee754_rem_pio2+0x2f0>) + 800b532: e9d3 2300 ldrd r2, r3, [r3] + 800b536: 4606 mov r6, r0 + 800b538: 460f mov r7, r1 + 800b53a: f7f4 fe1f bl 800017c <__adddf3> + 800b53e: 4602 mov r2, r0 + 800b540: 460b mov r3, r1 + 800b542: 4630 mov r0, r6 + 800b544: e9c4 2300 strd r2, r3, [r4] + 800b548: 4639 mov r1, r7 + 800b54a: f7f4 fe15 bl 8000178 <__aeabi_dsub> + 800b54e: a37a add r3, pc, #488 ; (adr r3, 800b738 <__ieee754_rem_pio2+0x2f0>) + 800b550: e9d3 2300 ldrd r2, r3, [r3] + 800b554: e7e0 b.n 800b518 <__ieee754_rem_pio2+0xd0> + 800b556: 4a83 ldr r2, [pc, #524] ; (800b764 <__ieee754_rem_pio2+0x31c>) + 800b558: 4592 cmp sl, r2 + 800b55a: f300 80d2 bgt.w 800b702 <__ieee754_rem_pio2+0x2ba> + 800b55e: f7fe fbcf bl 8009d00 + 800b562: a377 add r3, pc, #476 ; (adr r3, 800b740 <__ieee754_rem_pio2+0x2f8>) + 800b564: e9d3 2300 ldrd r2, r3, [r3] + 800b568: 4606 mov r6, r0 + 800b56a: 460f mov r7, r1 + 800b56c: f7f4 ffbc bl 80004e8 <__aeabi_dmul> + 800b570: 2200 movs r2, #0 + 800b572: 4b7d ldr r3, [pc, #500] ; (800b768 <__ieee754_rem_pio2+0x320>) + 800b574: f7f4 fe02 bl 800017c <__adddf3> + 800b578: f7f5 fa66 bl 8000a48 <__aeabi_d2iz> + 800b57c: 4605 mov r5, r0 + 800b57e: f7f4 ff49 bl 8000414 <__aeabi_i2d> + 800b582: a367 add r3, pc, #412 ; (adr r3, 800b720 <__ieee754_rem_pio2+0x2d8>) + 800b584: e9d3 2300 ldrd r2, r3, [r3] + 800b588: e9cd 0102 strd r0, r1, [sp, #8] + 800b58c: f7f4 ffac bl 80004e8 <__aeabi_dmul> + 800b590: 4602 mov r2, r0 + 800b592: 460b mov r3, r1 + 800b594: 4630 mov r0, r6 + 800b596: 4639 mov r1, r7 + 800b598: f7f4 fdee bl 8000178 <__aeabi_dsub> + 800b59c: a362 add r3, pc, #392 ; (adr r3, 800b728 <__ieee754_rem_pio2+0x2e0>) + 800b59e: e9d3 2300 ldrd r2, r3, [r3] + 800b5a2: 4606 mov r6, r0 + 800b5a4: 460f mov r7, r1 + 800b5a6: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b5aa: f7f4 ff9d bl 80004e8 <__aeabi_dmul> + 800b5ae: 2d1f cmp r5, #31 + 800b5b0: 4680 mov r8, r0 + 800b5b2: 4689 mov r9, r1 + 800b5b4: dc0e bgt.n 800b5d4 <__ieee754_rem_pio2+0x18c> + 800b5b6: 4b6d ldr r3, [pc, #436] ; (800b76c <__ieee754_rem_pio2+0x324>) + 800b5b8: 1e6a subs r2, r5, #1 + 800b5ba: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800b5be: 4553 cmp r3, sl + 800b5c0: d008 beq.n 800b5d4 <__ieee754_rem_pio2+0x18c> + 800b5c2: 4642 mov r2, r8 + 800b5c4: 464b mov r3, r9 + 800b5c6: 4630 mov r0, r6 + 800b5c8: 4639 mov r1, r7 + 800b5ca: f7f4 fdd5 bl 8000178 <__aeabi_dsub> + 800b5ce: e9c4 0100 strd r0, r1, [r4] + 800b5d2: e011 b.n 800b5f8 <__ieee754_rem_pio2+0x1b0> + 800b5d4: 464b mov r3, r9 + 800b5d6: 4642 mov r2, r8 + 800b5d8: 4630 mov r0, r6 + 800b5da: 4639 mov r1, r7 + 800b5dc: f7f4 fdcc bl 8000178 <__aeabi_dsub> + 800b5e0: ea4f 5a2a mov.w sl, sl, asr #20 + 800b5e4: f3c1 530a ubfx r3, r1, #20, #11 + 800b5e8: ebaa 0303 sub.w r3, sl, r3 + 800b5ec: 2b10 cmp r3, #16 + 800b5ee: dc1f bgt.n 800b630 <__ieee754_rem_pio2+0x1e8> + 800b5f0: 4602 mov r2, r0 + 800b5f2: 460b mov r3, r1 + 800b5f4: e9c4 2300 strd r2, r3, [r4] + 800b5f8: e9d4 2a00 ldrd r2, sl, [r4] + 800b5fc: 4630 mov r0, r6 + 800b5fe: 4653 mov r3, sl + 800b600: 4639 mov r1, r7 + 800b602: f7f4 fdb9 bl 8000178 <__aeabi_dsub> + 800b606: 4642 mov r2, r8 + 800b608: 464b mov r3, r9 + 800b60a: f7f4 fdb5 bl 8000178 <__aeabi_dsub> + 800b60e: 4602 mov r2, r0 + 800b610: 460b mov r3, r1 + 800b612: f1bb 0f00 cmp.w fp, #0 + 800b616: e9c4 2302 strd r2, r3, [r4, #8] + 800b61a: f6bf af4b bge.w 800b4b4 <__ieee754_rem_pio2+0x6c> + 800b61e: f10a 4300 add.w r3, sl, #2147483648 ; 0x80000000 + 800b622: e9c4 3001 strd r3, r0, [r4, #4] + 800b626: f101 4100 add.w r1, r1, #2147483648 ; 0x80000000 + 800b62a: 60e1 str r1, [r4, #12] + 800b62c: 426d negs r5, r5 + 800b62e: e741 b.n 800b4b4 <__ieee754_rem_pio2+0x6c> + 800b630: a33f add r3, pc, #252 ; (adr r3, 800b730 <__ieee754_rem_pio2+0x2e8>) + 800b632: e9d3 2300 ldrd r2, r3, [r3] + 800b636: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b63a: f7f4 ff55 bl 80004e8 <__aeabi_dmul> + 800b63e: 4680 mov r8, r0 + 800b640: 4689 mov r9, r1 + 800b642: 4602 mov r2, r0 + 800b644: 460b mov r3, r1 + 800b646: 4630 mov r0, r6 + 800b648: 4639 mov r1, r7 + 800b64a: f7f4 fd95 bl 8000178 <__aeabi_dsub> + 800b64e: e9cd 0104 strd r0, r1, [sp, #16] + 800b652: 4602 mov r2, r0 + 800b654: 460b mov r3, r1 + 800b656: 4630 mov r0, r6 + 800b658: 4639 mov r1, r7 + 800b65a: f7f4 fd8d bl 8000178 <__aeabi_dsub> + 800b65e: 4642 mov r2, r8 + 800b660: 464b mov r3, r9 + 800b662: f7f4 fd89 bl 8000178 <__aeabi_dsub> + 800b666: a334 add r3, pc, #208 ; (adr r3, 800b738 <__ieee754_rem_pio2+0x2f0>) + 800b668: e9d3 2300 ldrd r2, r3, [r3] + 800b66c: 4606 mov r6, r0 + 800b66e: 460f mov r7, r1 + 800b670: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b674: f7f4 ff38 bl 80004e8 <__aeabi_dmul> + 800b678: 4632 mov r2, r6 + 800b67a: 463b mov r3, r7 + 800b67c: f7f4 fd7c bl 8000178 <__aeabi_dsub> + 800b680: 460b mov r3, r1 + 800b682: 4602 mov r2, r0 + 800b684: 4680 mov r8, r0 + 800b686: 4689 mov r9, r1 + 800b688: e9dd 0104 ldrd r0, r1, [sp, #16] + 800b68c: f7f4 fd74 bl 8000178 <__aeabi_dsub> + 800b690: f3c1 530a ubfx r3, r1, #20, #11 + 800b694: ebaa 0a03 sub.w sl, sl, r3 + 800b698: f1ba 0f31 cmp.w sl, #49 ; 0x31 + 800b69c: dc06 bgt.n 800b6ac <__ieee754_rem_pio2+0x264> + 800b69e: e9dd 6704 ldrd r6, r7, [sp, #16] + 800b6a2: 4602 mov r2, r0 + 800b6a4: 460b mov r3, r1 + 800b6a6: e9c4 2300 strd r2, r3, [r4] + 800b6aa: e7a5 b.n 800b5f8 <__ieee754_rem_pio2+0x1b0> + 800b6ac: a326 add r3, pc, #152 ; (adr r3, 800b748 <__ieee754_rem_pio2+0x300>) + 800b6ae: e9d3 2300 ldrd r2, r3, [r3] + 800b6b2: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b6b6: f7f4 ff17 bl 80004e8 <__aeabi_dmul> + 800b6ba: 4680 mov r8, r0 + 800b6bc: 4689 mov r9, r1 + 800b6be: 4602 mov r2, r0 + 800b6c0: 460b mov r3, r1 + 800b6c2: e9dd 0104 ldrd r0, r1, [sp, #16] + 800b6c6: f7f4 fd57 bl 8000178 <__aeabi_dsub> + 800b6ca: 4602 mov r2, r0 + 800b6cc: 460b mov r3, r1 + 800b6ce: 4606 mov r6, r0 + 800b6d0: 460f mov r7, r1 + 800b6d2: e9dd 0104 ldrd r0, r1, [sp, #16] + 800b6d6: f7f4 fd4f bl 8000178 <__aeabi_dsub> + 800b6da: 4642 mov r2, r8 + 800b6dc: 464b mov r3, r9 + 800b6de: f7f4 fd4b bl 8000178 <__aeabi_dsub> + 800b6e2: a31b add r3, pc, #108 ; (adr r3, 800b750 <__ieee754_rem_pio2+0x308>) + 800b6e4: e9d3 2300 ldrd r2, r3, [r3] + 800b6e8: 4680 mov r8, r0 + 800b6ea: 4689 mov r9, r1 + 800b6ec: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b6f0: f7f4 fefa bl 80004e8 <__aeabi_dmul> + 800b6f4: 4642 mov r2, r8 + 800b6f6: 464b mov r3, r9 + 800b6f8: f7f4 fd3e bl 8000178 <__aeabi_dsub> + 800b6fc: 4680 mov r8, r0 + 800b6fe: 4689 mov r9, r1 + 800b700: e75f b.n 800b5c2 <__ieee754_rem_pio2+0x17a> + 800b702: 4a1b ldr r2, [pc, #108] ; (800b770 <__ieee754_rem_pio2+0x328>) + 800b704: 4592 cmp sl, r2 + 800b706: dd35 ble.n 800b774 <__ieee754_rem_pio2+0x32c> + 800b708: 4602 mov r2, r0 + 800b70a: 460b mov r3, r1 + 800b70c: f7f4 fd34 bl 8000178 <__aeabi_dsub> + 800b710: e9c4 0102 strd r0, r1, [r4, #8] + 800b714: e9c4 0100 strd r0, r1, [r4] + 800b718: e6a6 b.n 800b468 <__ieee754_rem_pio2+0x20> + 800b71a: bf00 nop + 800b71c: f3af 8000 nop.w + 800b720: 54400000 .word 0x54400000 + 800b724: 3ff921fb .word 0x3ff921fb + 800b728: 1a626331 .word 0x1a626331 + 800b72c: 3dd0b461 .word 0x3dd0b461 + 800b730: 1a600000 .word 0x1a600000 + 800b734: 3dd0b461 .word 0x3dd0b461 + 800b738: 2e037073 .word 0x2e037073 + 800b73c: 3ba3198a .word 0x3ba3198a + 800b740: 6dc9c883 .word 0x6dc9c883 + 800b744: 3fe45f30 .word 0x3fe45f30 + 800b748: 2e000000 .word 0x2e000000 + 800b74c: 3ba3198a .word 0x3ba3198a + 800b750: 252049c1 .word 0x252049c1 + 800b754: 397b839a .word 0x397b839a + 800b758: 3fe921fb .word 0x3fe921fb + 800b75c: 4002d97b .word 0x4002d97b + 800b760: 3ff921fb .word 0x3ff921fb + 800b764: 413921fb .word 0x413921fb + 800b768: 3fe00000 .word 0x3fe00000 + 800b76c: 0800e5d0 .word 0x0800e5d0 + 800b770: 7fefffff .word 0x7fefffff + 800b774: ea4f 552a mov.w r5, sl, asr #20 + 800b778: f2a5 4516 subw r5, r5, #1046 ; 0x416 + 800b77c: ebaa 5105 sub.w r1, sl, r5, lsl #20 + 800b780: 460f mov r7, r1 + 800b782: 4606 mov r6, r0 + 800b784: f7f5 f960 bl 8000a48 <__aeabi_d2iz> + 800b788: f7f4 fe44 bl 8000414 <__aeabi_i2d> + 800b78c: 4602 mov r2, r0 + 800b78e: 460b mov r3, r1 + 800b790: 4630 mov r0, r6 + 800b792: 4639 mov r1, r7 + 800b794: e9cd 2306 strd r2, r3, [sp, #24] + 800b798: f7f4 fcee bl 8000178 <__aeabi_dsub> + 800b79c: 2200 movs r2, #0 + 800b79e: 4b20 ldr r3, [pc, #128] ; (800b820 <__ieee754_rem_pio2+0x3d8>) + 800b7a0: f7f4 fea2 bl 80004e8 <__aeabi_dmul> + 800b7a4: 460f mov r7, r1 + 800b7a6: 4606 mov r6, r0 + 800b7a8: f7f5 f94e bl 8000a48 <__aeabi_d2iz> + 800b7ac: f7f4 fe32 bl 8000414 <__aeabi_i2d> + 800b7b0: 4602 mov r2, r0 + 800b7b2: 460b mov r3, r1 + 800b7b4: 4630 mov r0, r6 + 800b7b6: 4639 mov r1, r7 + 800b7b8: e9cd 2308 strd r2, r3, [sp, #32] + 800b7bc: f7f4 fcdc bl 8000178 <__aeabi_dsub> + 800b7c0: 2200 movs r2, #0 + 800b7c2: 4b17 ldr r3, [pc, #92] ; (800b820 <__ieee754_rem_pio2+0x3d8>) + 800b7c4: f7f4 fe90 bl 80004e8 <__aeabi_dmul> + 800b7c8: f04f 0803 mov.w r8, #3 + 800b7cc: 2600 movs r6, #0 + 800b7ce: 2700 movs r7, #0 + 800b7d0: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 + 800b7d4: f10d 0930 add.w r9, sp, #48 ; 0x30 + 800b7d8: 4632 mov r2, r6 + 800b7da: e979 0102 ldrd r0, r1, [r9, #-8]! + 800b7de: 463b mov r3, r7 + 800b7e0: f108 3aff add.w sl, r8, #4294967295 + 800b7e4: f7f5 f8e8 bl 80009b8 <__aeabi_dcmpeq> + 800b7e8: b9b8 cbnz r0, 800b81a <__ieee754_rem_pio2+0x3d2> + 800b7ea: 4b0e ldr r3, [pc, #56] ; (800b824 <__ieee754_rem_pio2+0x3dc>) + 800b7ec: 462a mov r2, r5 + 800b7ee: 9301 str r3, [sp, #4] + 800b7f0: 2302 movs r3, #2 + 800b7f2: 4621 mov r1, r4 + 800b7f4: 9300 str r3, [sp, #0] + 800b7f6: a806 add r0, sp, #24 + 800b7f8: 4643 mov r3, r8 + 800b7fa: f000 f97f bl 800bafc <__kernel_rem_pio2> + 800b7fe: f1bb 0f00 cmp.w fp, #0 + 800b802: 4605 mov r5, r0 + 800b804: f6bf ae56 bge.w 800b4b4 <__ieee754_rem_pio2+0x6c> + 800b808: 6863 ldr r3, [r4, #4] + 800b80a: f103 4300 add.w r3, r3, #2147483648 ; 0x80000000 + 800b80e: 6063 str r3, [r4, #4] + 800b810: 68e3 ldr r3, [r4, #12] + 800b812: f103 4300 add.w r3, r3, #2147483648 ; 0x80000000 + 800b816: 60e3 str r3, [r4, #12] + 800b818: e708 b.n 800b62c <__ieee754_rem_pio2+0x1e4> + 800b81a: 46d0 mov r8, sl + 800b81c: e7dc b.n 800b7d8 <__ieee754_rem_pio2+0x390> + 800b81e: bf00 nop + 800b820: 41700000 .word 0x41700000 + 800b824: 0800e650 .word 0x0800e650 + +0800b828 <__ieee754_sqrt>: + 800b828: 4b54 ldr r3, [pc, #336] ; (800b97c <__ieee754_sqrt+0x154>) + 800b82a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800b82e: 438b bics r3, r1 + 800b830: 4606 mov r6, r0 + 800b832: 460d mov r5, r1 + 800b834: 460a mov r2, r1 + 800b836: 460c mov r4, r1 + 800b838: d10f bne.n 800b85a <__ieee754_sqrt+0x32> + 800b83a: 4602 mov r2, r0 + 800b83c: 460b mov r3, r1 + 800b83e: f7f4 fe53 bl 80004e8 <__aeabi_dmul> + 800b842: 4602 mov r2, r0 + 800b844: 460b mov r3, r1 + 800b846: 4630 mov r0, r6 + 800b848: 4629 mov r1, r5 + 800b84a: f7f4 fc97 bl 800017c <__adddf3> + 800b84e: 4606 mov r6, r0 + 800b850: 460d mov r5, r1 + 800b852: 4630 mov r0, r6 + 800b854: 4629 mov r1, r5 + 800b856: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 800b85a: 2900 cmp r1, #0 + 800b85c: 4607 mov r7, r0 + 800b85e: 4603 mov r3, r0 + 800b860: dc0e bgt.n 800b880 <__ieee754_sqrt+0x58> + 800b862: f021 4c00 bic.w ip, r1, #2147483648 ; 0x80000000 + 800b866: ea5c 0707 orrs.w r7, ip, r7 + 800b86a: d0f2 beq.n 800b852 <__ieee754_sqrt+0x2a> + 800b86c: b141 cbz r1, 800b880 <__ieee754_sqrt+0x58> + 800b86e: 4602 mov r2, r0 + 800b870: 460b mov r3, r1 + 800b872: f7f4 fc81 bl 8000178 <__aeabi_dsub> + 800b876: 4602 mov r2, r0 + 800b878: 460b mov r3, r1 + 800b87a: f7f4 ff5f bl 800073c <__aeabi_ddiv> + 800b87e: e7e6 b.n 800b84e <__ieee754_sqrt+0x26> + 800b880: 1512 asrs r2, r2, #20 + 800b882: d074 beq.n 800b96e <__ieee754_sqrt+0x146> + 800b884: f2a2 32ff subw r2, r2, #1023 ; 0x3ff + 800b888: 07d5 lsls r5, r2, #31 + 800b88a: f04f 0500 mov.w r5, #0 + 800b88e: f3c4 0413 ubfx r4, r4, #0, #20 + 800b892: bf48 it mi + 800b894: 0fd9 lsrmi r1, r3, #31 + 800b896: f444 1480 orr.w r4, r4, #1048576 ; 0x100000 + 800b89a: bf44 itt mi + 800b89c: 005b lslmi r3, r3, #1 + 800b89e: eb01 0444 addmi.w r4, r1, r4, lsl #1 + 800b8a2: 1051 asrs r1, r2, #1 + 800b8a4: 0fda lsrs r2, r3, #31 + 800b8a6: eb02 0444 add.w r4, r2, r4, lsl #1 + 800b8aa: 4628 mov r0, r5 + 800b8ac: 2216 movs r2, #22 + 800b8ae: f44f 1600 mov.w r6, #2097152 ; 0x200000 + 800b8b2: 005b lsls r3, r3, #1 + 800b8b4: 1987 adds r7, r0, r6 + 800b8b6: 42a7 cmp r7, r4 + 800b8b8: bfde ittt le + 800b8ba: 19b8 addle r0, r7, r6 + 800b8bc: 1be4 suble r4, r4, r7 + 800b8be: 19ad addle r5, r5, r6 + 800b8c0: 0fdf lsrs r7, r3, #31 + 800b8c2: 3a01 subs r2, #1 + 800b8c4: eb07 0444 add.w r4, r7, r4, lsl #1 + 800b8c8: ea4f 0343 mov.w r3, r3, lsl #1 + 800b8cc: ea4f 0656 mov.w r6, r6, lsr #1 + 800b8d0: d1f0 bne.n 800b8b4 <__ieee754_sqrt+0x8c> + 800b8d2: f04f 0c20 mov.w ip, #32 + 800b8d6: 4696 mov lr, r2 + 800b8d8: f04f 4600 mov.w r6, #2147483648 ; 0x80000000 + 800b8dc: 4284 cmp r4, r0 + 800b8de: eb06 070e add.w r7, r6, lr + 800b8e2: dc02 bgt.n 800b8ea <__ieee754_sqrt+0xc2> + 800b8e4: d112 bne.n 800b90c <__ieee754_sqrt+0xe4> + 800b8e6: 429f cmp r7, r3 + 800b8e8: d810 bhi.n 800b90c <__ieee754_sqrt+0xe4> + 800b8ea: 2f00 cmp r7, #0 + 800b8ec: eb07 0e06 add.w lr, r7, r6 + 800b8f0: da42 bge.n 800b978 <__ieee754_sqrt+0x150> + 800b8f2: f1be 0f00 cmp.w lr, #0 + 800b8f6: db3f blt.n 800b978 <__ieee754_sqrt+0x150> + 800b8f8: f100 0801 add.w r8, r0, #1 + 800b8fc: 1a24 subs r4, r4, r0 + 800b8fe: 4640 mov r0, r8 + 800b900: 429f cmp r7, r3 + 800b902: bf88 it hi + 800b904: f104 34ff addhi.w r4, r4, #4294967295 + 800b908: 1bdb subs r3, r3, r7 + 800b90a: 4432 add r2, r6 + 800b90c: 0064 lsls r4, r4, #1 + 800b90e: f1bc 0c01 subs.w ip, ip, #1 + 800b912: eb04 74d3 add.w r4, r4, r3, lsr #31 + 800b916: ea4f 0656 mov.w r6, r6, lsr #1 + 800b91a: ea4f 0343 mov.w r3, r3, lsl #1 + 800b91e: d1dd bne.n 800b8dc <__ieee754_sqrt+0xb4> + 800b920: 4323 orrs r3, r4 + 800b922: d006 beq.n 800b932 <__ieee754_sqrt+0x10a> + 800b924: 1c54 adds r4, r2, #1 + 800b926: bf0b itete eq + 800b928: 4662 moveq r2, ip + 800b92a: 3201 addne r2, #1 + 800b92c: 3501 addeq r5, #1 + 800b92e: f022 0201 bicne.w r2, r2, #1 + 800b932: 106b asrs r3, r5, #1 + 800b934: 0852 lsrs r2, r2, #1 + 800b936: 07e8 lsls r0, r5, #31 + 800b938: f103 537f add.w r3, r3, #1069547520 ; 0x3fc00000 + 800b93c: f503 1300 add.w r3, r3, #2097152 ; 0x200000 + 800b940: bf48 it mi + 800b942: f042 4200 orrmi.w r2, r2, #2147483648 ; 0x80000000 + 800b946: eb03 5501 add.w r5, r3, r1, lsl #20 + 800b94a: 4616 mov r6, r2 + 800b94c: e781 b.n 800b852 <__ieee754_sqrt+0x2a> + 800b94e: 0adc lsrs r4, r3, #11 + 800b950: 3915 subs r1, #21 + 800b952: 055b lsls r3, r3, #21 + 800b954: 2c00 cmp r4, #0 + 800b956: d0fa beq.n 800b94e <__ieee754_sqrt+0x126> + 800b958: 02e6 lsls r6, r4, #11 + 800b95a: d50a bpl.n 800b972 <__ieee754_sqrt+0x14a> + 800b95c: f1c2 0020 rsb r0, r2, #32 + 800b960: fa23 f000 lsr.w r0, r3, r0 + 800b964: 1e55 subs r5, r2, #1 + 800b966: 4093 lsls r3, r2 + 800b968: 4304 orrs r4, r0 + 800b96a: 1b4a subs r2, r1, r5 + 800b96c: e78a b.n 800b884 <__ieee754_sqrt+0x5c> + 800b96e: 4611 mov r1, r2 + 800b970: e7f0 b.n 800b954 <__ieee754_sqrt+0x12c> + 800b972: 0064 lsls r4, r4, #1 + 800b974: 3201 adds r2, #1 + 800b976: e7ef b.n 800b958 <__ieee754_sqrt+0x130> + 800b978: 4680 mov r8, r0 + 800b97a: e7bf b.n 800b8fc <__ieee754_sqrt+0xd4> + 800b97c: 7ff00000 .word 0x7ff00000 + +0800b980 <__kernel_cos>: + 800b980: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800b984: f021 4600 bic.w r6, r1, #2147483648 ; 0x80000000 + 800b988: f1b6 5f79 cmp.w r6, #1044381696 ; 0x3e400000 + 800b98c: 4680 mov r8, r0 + 800b98e: 460f mov r7, r1 + 800b990: e9cd 2300 strd r2, r3, [sp] + 800b994: da04 bge.n 800b9a0 <__kernel_cos+0x20> + 800b996: f7f5 f857 bl 8000a48 <__aeabi_d2iz> + 800b99a: 2800 cmp r0, #0 + 800b99c: f000 8086 beq.w 800baac <__kernel_cos+0x12c> + 800b9a0: 4642 mov r2, r8 + 800b9a2: 463b mov r3, r7 + 800b9a4: 4640 mov r0, r8 + 800b9a6: 4639 mov r1, r7 + 800b9a8: f7f4 fd9e bl 80004e8 <__aeabi_dmul> + 800b9ac: 2200 movs r2, #0 + 800b9ae: 4b4e ldr r3, [pc, #312] ; (800bae8 <__kernel_cos+0x168>) + 800b9b0: 4604 mov r4, r0 + 800b9b2: 460d mov r5, r1 + 800b9b4: f7f4 fd98 bl 80004e8 <__aeabi_dmul> + 800b9b8: a33f add r3, pc, #252 ; (adr r3, 800bab8 <__kernel_cos+0x138>) + 800b9ba: e9d3 2300 ldrd r2, r3, [r3] + 800b9be: 4682 mov sl, r0 + 800b9c0: 468b mov fp, r1 + 800b9c2: 4620 mov r0, r4 + 800b9c4: 4629 mov r1, r5 + 800b9c6: f7f4 fd8f bl 80004e8 <__aeabi_dmul> + 800b9ca: a33d add r3, pc, #244 ; (adr r3, 800bac0 <__kernel_cos+0x140>) + 800b9cc: e9d3 2300 ldrd r2, r3, [r3] + 800b9d0: f7f4 fbd4 bl 800017c <__adddf3> + 800b9d4: 4622 mov r2, r4 + 800b9d6: 462b mov r3, r5 + 800b9d8: f7f4 fd86 bl 80004e8 <__aeabi_dmul> + 800b9dc: a33a add r3, pc, #232 ; (adr r3, 800bac8 <__kernel_cos+0x148>) + 800b9de: e9d3 2300 ldrd r2, r3, [r3] + 800b9e2: f7f4 fbc9 bl 8000178 <__aeabi_dsub> + 800b9e6: 4622 mov r2, r4 + 800b9e8: 462b mov r3, r5 + 800b9ea: f7f4 fd7d bl 80004e8 <__aeabi_dmul> + 800b9ee: a338 add r3, pc, #224 ; (adr r3, 800bad0 <__kernel_cos+0x150>) + 800b9f0: e9d3 2300 ldrd r2, r3, [r3] + 800b9f4: f7f4 fbc2 bl 800017c <__adddf3> + 800b9f8: 4622 mov r2, r4 + 800b9fa: 462b mov r3, r5 + 800b9fc: f7f4 fd74 bl 80004e8 <__aeabi_dmul> + 800ba00: a335 add r3, pc, #212 ; (adr r3, 800bad8 <__kernel_cos+0x158>) + 800ba02: e9d3 2300 ldrd r2, r3, [r3] + 800ba06: f7f4 fbb7 bl 8000178 <__aeabi_dsub> + 800ba0a: 4622 mov r2, r4 + 800ba0c: 462b mov r3, r5 + 800ba0e: f7f4 fd6b bl 80004e8 <__aeabi_dmul> + 800ba12: a333 add r3, pc, #204 ; (adr r3, 800bae0 <__kernel_cos+0x160>) + 800ba14: e9d3 2300 ldrd r2, r3, [r3] + 800ba18: f7f4 fbb0 bl 800017c <__adddf3> + 800ba1c: 4622 mov r2, r4 + 800ba1e: 462b mov r3, r5 + 800ba20: f7f4 fd62 bl 80004e8 <__aeabi_dmul> + 800ba24: 4622 mov r2, r4 + 800ba26: 462b mov r3, r5 + 800ba28: f7f4 fd5e bl 80004e8 <__aeabi_dmul> + 800ba2c: e9dd 2300 ldrd r2, r3, [sp] + 800ba30: 4604 mov r4, r0 + 800ba32: 460d mov r5, r1 + 800ba34: 4640 mov r0, r8 + 800ba36: 4639 mov r1, r7 + 800ba38: f7f4 fd56 bl 80004e8 <__aeabi_dmul> + 800ba3c: 460b mov r3, r1 + 800ba3e: 4602 mov r2, r0 + 800ba40: 4629 mov r1, r5 + 800ba42: 4620 mov r0, r4 + 800ba44: f7f4 fb98 bl 8000178 <__aeabi_dsub> + 800ba48: 4b28 ldr r3, [pc, #160] ; (800baec <__kernel_cos+0x16c>) + 800ba4a: 4680 mov r8, r0 + 800ba4c: 429e cmp r6, r3 + 800ba4e: 4689 mov r9, r1 + 800ba50: dc0e bgt.n 800ba70 <__kernel_cos+0xf0> + 800ba52: 4602 mov r2, r0 + 800ba54: 460b mov r3, r1 + 800ba56: 4650 mov r0, sl + 800ba58: 4659 mov r1, fp + 800ba5a: f7f4 fb8d bl 8000178 <__aeabi_dsub> + 800ba5e: 4602 mov r2, r0 + 800ba60: 2000 movs r0, #0 + 800ba62: 460b mov r3, r1 + 800ba64: 4922 ldr r1, [pc, #136] ; (800baf0 <__kernel_cos+0x170>) + 800ba66: f7f4 fb87 bl 8000178 <__aeabi_dsub> + 800ba6a: b003 add sp, #12 + 800ba6c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800ba70: 2400 movs r4, #0 + 800ba72: 4b20 ldr r3, [pc, #128] ; (800baf4 <__kernel_cos+0x174>) + 800ba74: 4622 mov r2, r4 + 800ba76: 429e cmp r6, r3 + 800ba78: bfcc ite gt + 800ba7a: 4d1f ldrgt r5, [pc, #124] ; (800baf8 <__kernel_cos+0x178>) + 800ba7c: f5a6 1500 suble.w r5, r6, #2097152 ; 0x200000 + 800ba80: 462b mov r3, r5 + 800ba82: 2000 movs r0, #0 + 800ba84: 491a ldr r1, [pc, #104] ; (800baf0 <__kernel_cos+0x170>) + 800ba86: f7f4 fb77 bl 8000178 <__aeabi_dsub> + 800ba8a: 4622 mov r2, r4 + 800ba8c: 4606 mov r6, r0 + 800ba8e: 460f mov r7, r1 + 800ba90: 462b mov r3, r5 + 800ba92: 4650 mov r0, sl + 800ba94: 4659 mov r1, fp + 800ba96: f7f4 fb6f bl 8000178 <__aeabi_dsub> + 800ba9a: 4642 mov r2, r8 + 800ba9c: 464b mov r3, r9 + 800ba9e: f7f4 fb6b bl 8000178 <__aeabi_dsub> + 800baa2: 4602 mov r2, r0 + 800baa4: 460b mov r3, r1 + 800baa6: 4630 mov r0, r6 + 800baa8: 4639 mov r1, r7 + 800baaa: e7dc b.n 800ba66 <__kernel_cos+0xe6> + 800baac: 2000 movs r0, #0 + 800baae: 4910 ldr r1, [pc, #64] ; (800baf0 <__kernel_cos+0x170>) + 800bab0: e7db b.n 800ba6a <__kernel_cos+0xea> + 800bab2: bf00 nop + 800bab4: f3af 8000 nop.w + 800bab8: be8838d4 .word 0xbe8838d4 + 800babc: bda8fae9 .word 0xbda8fae9 + 800bac0: bdb4b1c4 .word 0xbdb4b1c4 + 800bac4: 3e21ee9e .word 0x3e21ee9e + 800bac8: 809c52ad .word 0x809c52ad + 800bacc: 3e927e4f .word 0x3e927e4f + 800bad0: 19cb1590 .word 0x19cb1590 + 800bad4: 3efa01a0 .word 0x3efa01a0 + 800bad8: 16c15177 .word 0x16c15177 + 800badc: 3f56c16c .word 0x3f56c16c + 800bae0: 5555554c .word 0x5555554c + 800bae4: 3fa55555 .word 0x3fa55555 + 800bae8: 3fe00000 .word 0x3fe00000 + 800baec: 3fd33332 .word 0x3fd33332 + 800baf0: 3ff00000 .word 0x3ff00000 + 800baf4: 3fe90000 .word 0x3fe90000 + 800baf8: 3fd20000 .word 0x3fd20000 + +0800bafc <__kernel_rem_pio2>: + 800bafc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800bb00: f5ad 7d19 sub.w sp, sp, #612 ; 0x264 + 800bb04: 9307 str r3, [sp, #28] + 800bb06: 9104 str r1, [sp, #16] + 800bb08: 4bbf ldr r3, [pc, #764] ; (800be08 <__kernel_rem_pio2+0x30c>) + 800bb0a: 99a2 ldr r1, [sp, #648] ; 0x288 + 800bb0c: 1ed4 subs r4, r2, #3 + 800bb0e: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 800bb12: 2500 movs r5, #0 + 800bb14: 9302 str r3, [sp, #8] + 800bb16: 9b07 ldr r3, [sp, #28] + 800bb18: 9008 str r0, [sp, #32] + 800bb1a: 3b01 subs r3, #1 + 800bb1c: 9306 str r3, [sp, #24] + 800bb1e: 2318 movs r3, #24 + 800bb20: fb94 f4f3 sdiv r4, r4, r3 + 800bb24: f06f 0317 mvn.w r3, #23 + 800bb28: ea24 74e4 bic.w r4, r4, r4, asr #31 + 800bb2c: fb04 3303 mla r3, r4, r3, r3 + 800bb30: eb03 0a02 add.w sl, r3, r2 + 800bb34: 9a06 ldr r2, [sp, #24] + 800bb36: 9b02 ldr r3, [sp, #8] + 800bb38: 1aa7 subs r7, r4, r2 + 800bb3a: eb03 0802 add.w r8, r3, r2 + 800bb3e: 9ba3 ldr r3, [sp, #652] ; 0x28c + 800bb40: 2200 movs r2, #0 + 800bb42: eb03 0987 add.w r9, r3, r7, lsl #2 + 800bb46: 2300 movs r3, #0 + 800bb48: ae1e add r6, sp, #120 ; 0x78 + 800bb4a: 4545 cmp r5, r8 + 800bb4c: dd14 ble.n 800bb78 <__kernel_rem_pio2+0x7c> + 800bb4e: 2600 movs r6, #0 + 800bb50: f50d 7bdc add.w fp, sp, #440 ; 0x1b8 + 800bb54: 9b02 ldr r3, [sp, #8] + 800bb56: 429e cmp r6, r3 + 800bb58: dc39 bgt.n 800bbce <__kernel_rem_pio2+0xd2> + 800bb5a: 9b08 ldr r3, [sp, #32] + 800bb5c: f04f 0800 mov.w r8, #0 + 800bb60: 3b08 subs r3, #8 + 800bb62: 9300 str r3, [sp, #0] + 800bb64: 9b07 ldr r3, [sp, #28] + 800bb66: f04f 0900 mov.w r9, #0 + 800bb6a: 199d adds r5, r3, r6 + 800bb6c: ab20 add r3, sp, #128 ; 0x80 + 800bb6e: eb03 03c5 add.w r3, r3, r5, lsl #3 + 800bb72: 9305 str r3, [sp, #20] + 800bb74: 2700 movs r7, #0 + 800bb76: e023 b.n 800bbc0 <__kernel_rem_pio2+0xc4> + 800bb78: 42ef cmn r7, r5 + 800bb7a: d40b bmi.n 800bb94 <__kernel_rem_pio2+0x98> + 800bb7c: f859 0025 ldr.w r0, [r9, r5, lsl #2] + 800bb80: e9cd 2300 strd r2, r3, [sp] + 800bb84: f7f4 fc46 bl 8000414 <__aeabi_i2d> + 800bb88: e9dd 2300 ldrd r2, r3, [sp] + 800bb8c: e9e6 0102 strd r0, r1, [r6, #8]! + 800bb90: 3501 adds r5, #1 + 800bb92: e7da b.n 800bb4a <__kernel_rem_pio2+0x4e> + 800bb94: 4610 mov r0, r2 + 800bb96: 4619 mov r1, r3 + 800bb98: e7f8 b.n 800bb8c <__kernel_rem_pio2+0x90> + 800bb9a: 9905 ldr r1, [sp, #20] + 800bb9c: 9d00 ldr r5, [sp, #0] + 800bb9e: e971 2302 ldrd r2, r3, [r1, #-8]! + 800bba2: 9105 str r1, [sp, #20] + 800bba4: e9f5 0102 ldrd r0, r1, [r5, #8]! + 800bba8: 9500 str r5, [sp, #0] + 800bbaa: f7f4 fc9d bl 80004e8 <__aeabi_dmul> + 800bbae: 4602 mov r2, r0 + 800bbb0: 460b mov r3, r1 + 800bbb2: 4640 mov r0, r8 + 800bbb4: 4649 mov r1, r9 + 800bbb6: f7f4 fae1 bl 800017c <__adddf3> + 800bbba: 4680 mov r8, r0 + 800bbbc: 4689 mov r9, r1 + 800bbbe: 3701 adds r7, #1 + 800bbc0: 9b06 ldr r3, [sp, #24] + 800bbc2: 429f cmp r7, r3 + 800bbc4: dde9 ble.n 800bb9a <__kernel_rem_pio2+0x9e> + 800bbc6: e9eb 8902 strd r8, r9, [fp, #8]! + 800bbca: 3601 adds r6, #1 + 800bbcc: e7c2 b.n 800bb54 <__kernel_rem_pio2+0x58> + 800bbce: 9b02 ldr r3, [sp, #8] + 800bbd0: aa0c add r2, sp, #48 ; 0x30 + 800bbd2: eb02 0383 add.w r3, r2, r3, lsl #2 + 800bbd6: 930b str r3, [sp, #44] ; 0x2c + 800bbd8: 9ba3 ldr r3, [sp, #652] ; 0x28c + 800bbda: 9f02 ldr r7, [sp, #8] + 800bbdc: eb03 0384 add.w r3, r3, r4, lsl #2 + 800bbe0: 930a str r3, [sp, #40] ; 0x28 + 800bbe2: 2600 movs r6, #0 + 800bbe4: ab98 add r3, sp, #608 ; 0x260 + 800bbe6: f107 5b00 add.w fp, r7, #536870912 ; 0x20000000 + 800bbea: eb03 03c7 add.w r3, r3, r7, lsl #3 + 800bbee: f10b 3bff add.w fp, fp, #4294967295 + 800bbf2: e953 8928 ldrd r8, r9, [r3, #-160] ; 0xa0 + 800bbf6: ea4f 0bcb mov.w fp, fp, lsl #3 + 800bbfa: ab98 add r3, sp, #608 ; 0x260 + 800bbfc: 445b add r3, fp + 800bbfe: f1a3 0498 sub.w r4, r3, #152 ; 0x98 + 800bc02: 1bbb subs r3, r7, r6 + 800bc04: 2b00 cmp r3, #0 + 800bc06: dc71 bgt.n 800bcec <__kernel_rem_pio2+0x1f0> + 800bc08: 4652 mov r2, sl + 800bc0a: 4640 mov r0, r8 + 800bc0c: 4649 mov r1, r9 + 800bc0e: f000 fe57 bl 800c8c0 + 800bc12: 2200 movs r2, #0 + 800bc14: f04f 537f mov.w r3, #1069547520 ; 0x3fc00000 + 800bc18: 4604 mov r4, r0 + 800bc1a: 460d mov r5, r1 + 800bc1c: f7f4 fc64 bl 80004e8 <__aeabi_dmul> + 800bc20: f000 fd36 bl 800c690 + 800bc24: 2200 movs r2, #0 + 800bc26: 4b79 ldr r3, [pc, #484] ; (800be0c <__kernel_rem_pio2+0x310>) + 800bc28: f7f4 fc5e bl 80004e8 <__aeabi_dmul> + 800bc2c: 4602 mov r2, r0 + 800bc2e: 460b mov r3, r1 + 800bc30: 4620 mov r0, r4 + 800bc32: 4629 mov r1, r5 + 800bc34: f7f4 faa0 bl 8000178 <__aeabi_dsub> + 800bc38: 460d mov r5, r1 + 800bc3a: 4604 mov r4, r0 + 800bc3c: f7f4 ff04 bl 8000a48 <__aeabi_d2iz> + 800bc40: 9005 str r0, [sp, #20] + 800bc42: f7f4 fbe7 bl 8000414 <__aeabi_i2d> + 800bc46: 4602 mov r2, r0 + 800bc48: 460b mov r3, r1 + 800bc4a: 4620 mov r0, r4 + 800bc4c: 4629 mov r1, r5 + 800bc4e: f7f4 fa93 bl 8000178 <__aeabi_dsub> + 800bc52: f1ba 0f00 cmp.w sl, #0 + 800bc56: 4680 mov r8, r0 + 800bc58: 4689 mov r9, r1 + 800bc5a: dd6c ble.n 800bd36 <__kernel_rem_pio2+0x23a> + 800bc5c: 1e7a subs r2, r7, #1 + 800bc5e: ab0c add r3, sp, #48 ; 0x30 + 800bc60: f853 0022 ldr.w r0, [r3, r2, lsl #2] + 800bc64: f1ca 0118 rsb r1, sl, #24 + 800bc68: 9c05 ldr r4, [sp, #20] + 800bc6a: fa40 f301 asr.w r3, r0, r1 + 800bc6e: 441c add r4, r3 + 800bc70: 408b lsls r3, r1 + 800bc72: 1ac0 subs r0, r0, r3 + 800bc74: ab0c add r3, sp, #48 ; 0x30 + 800bc76: f843 0022 str.w r0, [r3, r2, lsl #2] + 800bc7a: f1ca 0317 rsb r3, sl, #23 + 800bc7e: 9405 str r4, [sp, #20] + 800bc80: fa40 f303 asr.w r3, r0, r3 + 800bc84: 9300 str r3, [sp, #0] + 800bc86: 9b00 ldr r3, [sp, #0] + 800bc88: 2b00 cmp r3, #0 + 800bc8a: dd62 ble.n 800bd52 <__kernel_rem_pio2+0x256> + 800bc8c: 2200 movs r2, #0 + 800bc8e: f06f 417f mvn.w r1, #4278190080 ; 0xff000000 + 800bc92: 4614 mov r4, r2 + 800bc94: 9b05 ldr r3, [sp, #20] + 800bc96: 3301 adds r3, #1 + 800bc98: 9305 str r3, [sp, #20] + 800bc9a: 4297 cmp r7, r2 + 800bc9c: f300 809f bgt.w 800bdde <__kernel_rem_pio2+0x2e2> + 800bca0: f1ba 0f00 cmp.w sl, #0 + 800bca4: dd07 ble.n 800bcb6 <__kernel_rem_pio2+0x1ba> + 800bca6: f1ba 0f01 cmp.w sl, #1 + 800bcaa: f000 80bb beq.w 800be24 <__kernel_rem_pio2+0x328> + 800bcae: f1ba 0f02 cmp.w sl, #2 + 800bcb2: f000 80c1 beq.w 800be38 <__kernel_rem_pio2+0x33c> + 800bcb6: 9b00 ldr r3, [sp, #0] + 800bcb8: 2b02 cmp r3, #2 + 800bcba: d14a bne.n 800bd52 <__kernel_rem_pio2+0x256> + 800bcbc: 4642 mov r2, r8 + 800bcbe: 464b mov r3, r9 + 800bcc0: 2000 movs r0, #0 + 800bcc2: 4953 ldr r1, [pc, #332] ; (800be10 <__kernel_rem_pio2+0x314>) + 800bcc4: f7f4 fa58 bl 8000178 <__aeabi_dsub> + 800bcc8: 4680 mov r8, r0 + 800bcca: 4689 mov r9, r1 + 800bccc: 2c00 cmp r4, #0 + 800bcce: d040 beq.n 800bd52 <__kernel_rem_pio2+0x256> + 800bcd0: 4652 mov r2, sl + 800bcd2: 2000 movs r0, #0 + 800bcd4: 494e ldr r1, [pc, #312] ; (800be10 <__kernel_rem_pio2+0x314>) + 800bcd6: f000 fdf3 bl 800c8c0 + 800bcda: 4602 mov r2, r0 + 800bcdc: 460b mov r3, r1 + 800bcde: 4640 mov r0, r8 + 800bce0: 4649 mov r1, r9 + 800bce2: f7f4 fa49 bl 8000178 <__aeabi_dsub> + 800bce6: 4680 mov r8, r0 + 800bce8: 4689 mov r9, r1 + 800bcea: e032 b.n 800bd52 <__kernel_rem_pio2+0x256> + 800bcec: 2200 movs r2, #0 + 800bcee: 4b49 ldr r3, [pc, #292] ; (800be14 <__kernel_rem_pio2+0x318>) + 800bcf0: 4640 mov r0, r8 + 800bcf2: 4649 mov r1, r9 + 800bcf4: f7f4 fbf8 bl 80004e8 <__aeabi_dmul> + 800bcf8: f7f4 fea6 bl 8000a48 <__aeabi_d2iz> + 800bcfc: f7f4 fb8a bl 8000414 <__aeabi_i2d> + 800bd00: 2200 movs r2, #0 + 800bd02: 4b45 ldr r3, [pc, #276] ; (800be18 <__kernel_rem_pio2+0x31c>) + 800bd04: e9cd 0100 strd r0, r1, [sp] + 800bd08: f7f4 fbee bl 80004e8 <__aeabi_dmul> + 800bd0c: 4602 mov r2, r0 + 800bd0e: 460b mov r3, r1 + 800bd10: 4640 mov r0, r8 + 800bd12: 4649 mov r1, r9 + 800bd14: f7f4 fa30 bl 8000178 <__aeabi_dsub> + 800bd18: f7f4 fe96 bl 8000a48 <__aeabi_d2iz> + 800bd1c: ab0c add r3, sp, #48 ; 0x30 + 800bd1e: f843 0026 str.w r0, [r3, r6, lsl #2] + 800bd22: e974 2302 ldrd r2, r3, [r4, #-8]! + 800bd26: e9dd 0100 ldrd r0, r1, [sp] + 800bd2a: f7f4 fa27 bl 800017c <__adddf3> + 800bd2e: 3601 adds r6, #1 + 800bd30: 4680 mov r8, r0 + 800bd32: 4689 mov r9, r1 + 800bd34: e765 b.n 800bc02 <__kernel_rem_pio2+0x106> + 800bd36: d105 bne.n 800bd44 <__kernel_rem_pio2+0x248> + 800bd38: 1e7b subs r3, r7, #1 + 800bd3a: aa0c add r2, sp, #48 ; 0x30 + 800bd3c: f852 0023 ldr.w r0, [r2, r3, lsl #2] + 800bd40: 15c3 asrs r3, r0, #23 + 800bd42: e79f b.n 800bc84 <__kernel_rem_pio2+0x188> + 800bd44: 2200 movs r2, #0 + 800bd46: 4b35 ldr r3, [pc, #212] ; (800be1c <__kernel_rem_pio2+0x320>) + 800bd48: f7f4 fe54 bl 80009f4 <__aeabi_dcmpge> + 800bd4c: 2800 cmp r0, #0 + 800bd4e: d143 bne.n 800bdd8 <__kernel_rem_pio2+0x2dc> + 800bd50: 9000 str r0, [sp, #0] + 800bd52: 2200 movs r2, #0 + 800bd54: 2300 movs r3, #0 + 800bd56: 4640 mov r0, r8 + 800bd58: 4649 mov r1, r9 + 800bd5a: f7f4 fe2d bl 80009b8 <__aeabi_dcmpeq> + 800bd5e: 2800 cmp r0, #0 + 800bd60: f000 80c3 beq.w 800beea <__kernel_rem_pio2+0x3ee> + 800bd64: 1e7c subs r4, r7, #1 + 800bd66: 4623 mov r3, r4 + 800bd68: 2200 movs r2, #0 + 800bd6a: 9902 ldr r1, [sp, #8] + 800bd6c: 428b cmp r3, r1 + 800bd6e: da6a bge.n 800be46 <__kernel_rem_pio2+0x34a> + 800bd70: 2a00 cmp r2, #0 + 800bd72: f000 8084 beq.w 800be7e <__kernel_rem_pio2+0x382> + 800bd76: ab0c add r3, sp, #48 ; 0x30 + 800bd78: f853 3024 ldr.w r3, [r3, r4, lsl #2] + 800bd7c: f1aa 0a18 sub.w sl, sl, #24 + 800bd80: 2b00 cmp r3, #0 + 800bd82: f000 80b0 beq.w 800bee6 <__kernel_rem_pio2+0x3ea> + 800bd86: 4652 mov r2, sl + 800bd88: 2000 movs r0, #0 + 800bd8a: 4921 ldr r1, [pc, #132] ; (800be10 <__kernel_rem_pio2+0x314>) + 800bd8c: f000 fd98 bl 800c8c0 + 800bd90: 4625 mov r5, r4 + 800bd92: 4606 mov r6, r0 + 800bd94: 460f mov r7, r1 + 800bd96: f04f 0a00 mov.w sl, #0 + 800bd9a: 00e3 lsls r3, r4, #3 + 800bd9c: aa98 add r2, sp, #608 ; 0x260 + 800bd9e: eb02 0803 add.w r8, r2, r3 + 800bda2: f8df b070 ldr.w fp, [pc, #112] ; 800be14 <__kernel_rem_pio2+0x318> + 800bda6: 9306 str r3, [sp, #24] + 800bda8: f1a8 0898 sub.w r8, r8, #152 ; 0x98 + 800bdac: 2d00 cmp r5, #0 + 800bdae: f280 80d2 bge.w 800bf56 <__kernel_rem_pio2+0x45a> + 800bdb2: 2500 movs r5, #0 + 800bdb4: 9a06 ldr r2, [sp, #24] + 800bdb6: ab98 add r3, sp, #608 ; 0x260 + 800bdb8: 189e adds r6, r3, r2 + 800bdba: 3ea8 subs r6, #168 ; 0xa8 + 800bdbc: 1b63 subs r3, r4, r5 + 800bdbe: 2b00 cmp r3, #0 + 800bdc0: f2c0 80f9 blt.w 800bfb6 <__kernel_rem_pio2+0x4ba> + 800bdc4: f8df 9058 ldr.w r9, [pc, #88] ; 800be20 <__kernel_rem_pio2+0x324> + 800bdc8: eba6 08c5 sub.w r8, r6, r5, lsl #3 + 800bdcc: f04f 0a00 mov.w sl, #0 + 800bdd0: f04f 0b00 mov.w fp, #0 + 800bdd4: 2700 movs r7, #0 + 800bdd6: e0e2 b.n 800bf9e <__kernel_rem_pio2+0x4a2> + 800bdd8: 2302 movs r3, #2 + 800bdda: 9300 str r3, [sp, #0] + 800bddc: e756 b.n 800bc8c <__kernel_rem_pio2+0x190> + 800bdde: ab0c add r3, sp, #48 ; 0x30 + 800bde0: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800bde4: b94c cbnz r4, 800bdfa <__kernel_rem_pio2+0x2fe> + 800bde6: b12b cbz r3, 800bdf4 <__kernel_rem_pio2+0x2f8> + 800bde8: f1c3 7380 rsb r3, r3, #16777216 ; 0x1000000 + 800bdec: a80c add r0, sp, #48 ; 0x30 + 800bdee: f840 3022 str.w r3, [r0, r2, lsl #2] + 800bdf2: 2301 movs r3, #1 + 800bdf4: 3201 adds r2, #1 + 800bdf6: 461c mov r4, r3 + 800bdf8: e74f b.n 800bc9a <__kernel_rem_pio2+0x19e> + 800bdfa: 1acb subs r3, r1, r3 + 800bdfc: a80c add r0, sp, #48 ; 0x30 + 800bdfe: f840 3022 str.w r3, [r0, r2, lsl #2] + 800be02: 4623 mov r3, r4 + 800be04: e7f6 b.n 800bdf4 <__kernel_rem_pio2+0x2f8> + 800be06: bf00 nop + 800be08: 0800e798 .word 0x0800e798 + 800be0c: 40200000 .word 0x40200000 + 800be10: 3ff00000 .word 0x3ff00000 + 800be14: 3e700000 .word 0x3e700000 + 800be18: 41700000 .word 0x41700000 + 800be1c: 3fe00000 .word 0x3fe00000 + 800be20: 0800e750 .word 0x0800e750 + 800be24: 1e7a subs r2, r7, #1 + 800be26: ab0c add r3, sp, #48 ; 0x30 + 800be28: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800be2c: f3c3 0316 ubfx r3, r3, #0, #23 + 800be30: a90c add r1, sp, #48 ; 0x30 + 800be32: f841 3022 str.w r3, [r1, r2, lsl #2] + 800be36: e73e b.n 800bcb6 <__kernel_rem_pio2+0x1ba> + 800be38: 1e7a subs r2, r7, #1 + 800be3a: ab0c add r3, sp, #48 ; 0x30 + 800be3c: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800be40: f3c3 0315 ubfx r3, r3, #0, #22 + 800be44: e7f4 b.n 800be30 <__kernel_rem_pio2+0x334> + 800be46: a90c add r1, sp, #48 ; 0x30 + 800be48: f851 1023 ldr.w r1, [r1, r3, lsl #2] + 800be4c: 3b01 subs r3, #1 + 800be4e: 430a orrs r2, r1 + 800be50: e78b b.n 800bd6a <__kernel_rem_pio2+0x26e> + 800be52: 3401 adds r4, #1 + 800be54: f853 2d04 ldr.w r2, [r3, #-4]! + 800be58: 2a00 cmp r2, #0 + 800be5a: d0fa beq.n 800be52 <__kernel_rem_pio2+0x356> + 800be5c: ab98 add r3, sp, #608 ; 0x260 + 800be5e: 449b add fp, r3 + 800be60: 9b07 ldr r3, [sp, #28] + 800be62: 1c7e adds r6, r7, #1 + 800be64: 19dd adds r5, r3, r7 + 800be66: ab98 add r3, sp, #608 ; 0x260 + 800be68: eb03 05c5 add.w r5, r3, r5, lsl #3 + 800be6c: f1ab 0b98 sub.w fp, fp, #152 ; 0x98 + 800be70: f5a5 75f4 sub.w r5, r5, #488 ; 0x1e8 + 800be74: 443c add r4, r7 + 800be76: 42b4 cmp r4, r6 + 800be78: da04 bge.n 800be84 <__kernel_rem_pio2+0x388> + 800be7a: 4627 mov r7, r4 + 800be7c: e6b1 b.n 800bbe2 <__kernel_rem_pio2+0xe6> + 800be7e: 9b0b ldr r3, [sp, #44] ; 0x2c + 800be80: 2401 movs r4, #1 + 800be82: e7e7 b.n 800be54 <__kernel_rem_pio2+0x358> + 800be84: f105 0308 add.w r3, r5, #8 + 800be88: 9309 str r3, [sp, #36] ; 0x24 + 800be8a: 9b0a ldr r3, [sp, #40] ; 0x28 + 800be8c: 2700 movs r7, #0 + 800be8e: f853 0026 ldr.w r0, [r3, r6, lsl #2] + 800be92: f7f4 fabf bl 8000414 <__aeabi_i2d> + 800be96: f04f 0800 mov.w r8, #0 + 800be9a: f04f 0900 mov.w r9, #0 + 800be9e: 9b08 ldr r3, [sp, #32] + 800bea0: e9c5 0102 strd r0, r1, [r5, #8] + 800bea4: 3b08 subs r3, #8 + 800bea6: 9300 str r3, [sp, #0] + 800bea8: f105 0310 add.w r3, r5, #16 + 800beac: 9305 str r3, [sp, #20] + 800beae: 9b06 ldr r3, [sp, #24] + 800beb0: 429f cmp r7, r3 + 800beb2: dd04 ble.n 800bebe <__kernel_rem_pio2+0x3c2> + 800beb4: e9eb 8902 strd r8, r9, [fp, #8]! + 800beb8: 3601 adds r6, #1 + 800beba: 9d09 ldr r5, [sp, #36] ; 0x24 + 800bebc: e7db b.n 800be76 <__kernel_rem_pio2+0x37a> + 800bebe: 9905 ldr r1, [sp, #20] + 800bec0: 9d00 ldr r5, [sp, #0] + 800bec2: e971 2302 ldrd r2, r3, [r1, #-8]! + 800bec6: 9105 str r1, [sp, #20] + 800bec8: e9f5 0102 ldrd r0, r1, [r5, #8]! + 800becc: 9500 str r5, [sp, #0] + 800bece: f7f4 fb0b bl 80004e8 <__aeabi_dmul> + 800bed2: 4602 mov r2, r0 + 800bed4: 460b mov r3, r1 + 800bed6: 4640 mov r0, r8 + 800bed8: 4649 mov r1, r9 + 800beda: f7f4 f94f bl 800017c <__adddf3> + 800bede: 3701 adds r7, #1 + 800bee0: 4680 mov r8, r0 + 800bee2: 4689 mov r9, r1 + 800bee4: e7e3 b.n 800beae <__kernel_rem_pio2+0x3b2> + 800bee6: 3c01 subs r4, #1 + 800bee8: e745 b.n 800bd76 <__kernel_rem_pio2+0x27a> + 800beea: f1ca 0200 rsb r2, sl, #0 + 800beee: 4640 mov r0, r8 + 800bef0: 4649 mov r1, r9 + 800bef2: f000 fce5 bl 800c8c0 + 800bef6: 2200 movs r2, #0 + 800bef8: 4ba3 ldr r3, [pc, #652] ; (800c188 <__kernel_rem_pio2+0x68c>) + 800befa: 4604 mov r4, r0 + 800befc: 460d mov r5, r1 + 800befe: f7f4 fd79 bl 80009f4 <__aeabi_dcmpge> + 800bf02: b1f8 cbz r0, 800bf44 <__kernel_rem_pio2+0x448> + 800bf04: 2200 movs r2, #0 + 800bf06: 4ba1 ldr r3, [pc, #644] ; (800c18c <__kernel_rem_pio2+0x690>) + 800bf08: 4620 mov r0, r4 + 800bf0a: 4629 mov r1, r5 + 800bf0c: f7f4 faec bl 80004e8 <__aeabi_dmul> + 800bf10: f7f4 fd9a bl 8000a48 <__aeabi_d2iz> + 800bf14: 4606 mov r6, r0 + 800bf16: f7f4 fa7d bl 8000414 <__aeabi_i2d> + 800bf1a: 2200 movs r2, #0 + 800bf1c: 4b9a ldr r3, [pc, #616] ; (800c188 <__kernel_rem_pio2+0x68c>) + 800bf1e: f7f4 fae3 bl 80004e8 <__aeabi_dmul> + 800bf22: 460b mov r3, r1 + 800bf24: 4602 mov r2, r0 + 800bf26: 4629 mov r1, r5 + 800bf28: 4620 mov r0, r4 + 800bf2a: f7f4 f925 bl 8000178 <__aeabi_dsub> + 800bf2e: f7f4 fd8b bl 8000a48 <__aeabi_d2iz> + 800bf32: 1c7c adds r4, r7, #1 + 800bf34: ab0c add r3, sp, #48 ; 0x30 + 800bf36: f843 0027 str.w r0, [r3, r7, lsl #2] + 800bf3a: f10a 0a18 add.w sl, sl, #24 + 800bf3e: f843 6024 str.w r6, [r3, r4, lsl #2] + 800bf42: e720 b.n 800bd86 <__kernel_rem_pio2+0x28a> + 800bf44: 4620 mov r0, r4 + 800bf46: 4629 mov r1, r5 + 800bf48: f7f4 fd7e bl 8000a48 <__aeabi_d2iz> + 800bf4c: ab0c add r3, sp, #48 ; 0x30 + 800bf4e: f843 0027 str.w r0, [r3, r7, lsl #2] + 800bf52: 463c mov r4, r7 + 800bf54: e717 b.n 800bd86 <__kernel_rem_pio2+0x28a> + 800bf56: ab0c add r3, sp, #48 ; 0x30 + 800bf58: f853 0025 ldr.w r0, [r3, r5, lsl #2] + 800bf5c: f7f4 fa5a bl 8000414 <__aeabi_i2d> + 800bf60: 4632 mov r2, r6 + 800bf62: 463b mov r3, r7 + 800bf64: f7f4 fac0 bl 80004e8 <__aeabi_dmul> + 800bf68: 4652 mov r2, sl + 800bf6a: e968 0102 strd r0, r1, [r8, #-8]! + 800bf6e: 465b mov r3, fp + 800bf70: 4630 mov r0, r6 + 800bf72: 4639 mov r1, r7 + 800bf74: f7f4 fab8 bl 80004e8 <__aeabi_dmul> + 800bf78: 3d01 subs r5, #1 + 800bf7a: 4606 mov r6, r0 + 800bf7c: 460f mov r7, r1 + 800bf7e: e715 b.n 800bdac <__kernel_rem_pio2+0x2b0> + 800bf80: e9f8 2302 ldrd r2, r3, [r8, #8]! + 800bf84: e9f9 0102 ldrd r0, r1, [r9, #8]! + 800bf88: f7f4 faae bl 80004e8 <__aeabi_dmul> + 800bf8c: 4602 mov r2, r0 + 800bf8e: 460b mov r3, r1 + 800bf90: 4650 mov r0, sl + 800bf92: 4659 mov r1, fp + 800bf94: f7f4 f8f2 bl 800017c <__adddf3> + 800bf98: 4682 mov sl, r0 + 800bf9a: 468b mov fp, r1 + 800bf9c: 3701 adds r7, #1 + 800bf9e: 9b02 ldr r3, [sp, #8] + 800bfa0: 429f cmp r7, r3 + 800bfa2: dc01 bgt.n 800bfa8 <__kernel_rem_pio2+0x4ac> + 800bfa4: 42bd cmp r5, r7 + 800bfa6: daeb bge.n 800bf80 <__kernel_rem_pio2+0x484> + 800bfa8: ab48 add r3, sp, #288 ; 0x120 + 800bfaa: eb03 03c5 add.w r3, r3, r5, lsl #3 + 800bfae: e9c3 ab00 strd sl, fp, [r3] + 800bfb2: 3501 adds r5, #1 + 800bfb4: e702 b.n 800bdbc <__kernel_rem_pio2+0x2c0> + 800bfb6: 9ba2 ldr r3, [sp, #648] ; 0x288 + 800bfb8: 2b03 cmp r3, #3 + 800bfba: d86c bhi.n 800c096 <__kernel_rem_pio2+0x59a> + 800bfbc: e8df f003 tbb [pc, r3] + 800bfc0: 022f2f59 .word 0x022f2f59 + 800bfc4: 9a06 ldr r2, [sp, #24] + 800bfc6: ab48 add r3, sp, #288 ; 0x120 + 800bfc8: 189d adds r5, r3, r2 + 800bfca: 46aa mov sl, r5 + 800bfcc: 46a3 mov fp, r4 + 800bfce: f1bb 0f00 cmp.w fp, #0 + 800bfd2: f300 8087 bgt.w 800c0e4 <__kernel_rem_pio2+0x5e8> + 800bfd6: 46a2 mov sl, r4 + 800bfd8: f1ba 0f01 cmp.w sl, #1 + 800bfdc: f300 809f bgt.w 800c11e <__kernel_rem_pio2+0x622> + 800bfe0: 2700 movs r7, #0 + 800bfe2: 463e mov r6, r7 + 800bfe4: 9d06 ldr r5, [sp, #24] + 800bfe6: ab48 add r3, sp, #288 ; 0x120 + 800bfe8: 3508 adds r5, #8 + 800bfea: 441d add r5, r3 + 800bfec: 2c01 cmp r4, #1 + 800bfee: f300 80b3 bgt.w 800c158 <__kernel_rem_pio2+0x65c> + 800bff2: 9b00 ldr r3, [sp, #0] + 800bff4: 9d48 ldr r5, [sp, #288] ; 0x120 + 800bff6: 9849 ldr r0, [sp, #292] ; 0x124 + 800bff8: 9c4a ldr r4, [sp, #296] ; 0x128 + 800bffa: 994b ldr r1, [sp, #300] ; 0x12c + 800bffc: 2b00 cmp r3, #0 + 800bffe: f040 80b5 bne.w 800c16c <__kernel_rem_pio2+0x670> + 800c002: 4603 mov r3, r0 + 800c004: 462a mov r2, r5 + 800c006: 9804 ldr r0, [sp, #16] + 800c008: e9c0 2300 strd r2, r3, [r0] + 800c00c: 4622 mov r2, r4 + 800c00e: 460b mov r3, r1 + 800c010: e9c0 2302 strd r2, r3, [r0, #8] + 800c014: 463a mov r2, r7 + 800c016: 4633 mov r3, r6 + 800c018: e9c0 2304 strd r2, r3, [r0, #16] + 800c01c: e03b b.n 800c096 <__kernel_rem_pio2+0x59a> + 800c01e: f04f 0c00 mov.w ip, #0 + 800c022: 4626 mov r6, r4 + 800c024: 4667 mov r7, ip + 800c026: 9d06 ldr r5, [sp, #24] + 800c028: ab48 add r3, sp, #288 ; 0x120 + 800c02a: 3508 adds r5, #8 + 800c02c: 441d add r5, r3 + 800c02e: 2e00 cmp r6, #0 + 800c030: da42 bge.n 800c0b8 <__kernel_rem_pio2+0x5bc> + 800c032: 9b00 ldr r3, [sp, #0] + 800c034: 2b00 cmp r3, #0 + 800c036: d049 beq.n 800c0cc <__kernel_rem_pio2+0x5d0> + 800c038: f107 4100 add.w r1, r7, #2147483648 ; 0x80000000 + 800c03c: 4662 mov r2, ip + 800c03e: 460b mov r3, r1 + 800c040: 9904 ldr r1, [sp, #16] + 800c042: 2601 movs r6, #1 + 800c044: e9c1 2300 strd r2, r3, [r1] + 800c048: a948 add r1, sp, #288 ; 0x120 + 800c04a: 463b mov r3, r7 + 800c04c: e9d1 0100 ldrd r0, r1, [r1] + 800c050: f7f4 f892 bl 8000178 <__aeabi_dsub> + 800c054: 4684 mov ip, r0 + 800c056: 460f mov r7, r1 + 800c058: ad48 add r5, sp, #288 ; 0x120 + 800c05a: 42b4 cmp r4, r6 + 800c05c: da38 bge.n 800c0d0 <__kernel_rem_pio2+0x5d4> + 800c05e: 9b00 ldr r3, [sp, #0] + 800c060: b10b cbz r3, 800c066 <__kernel_rem_pio2+0x56a> + 800c062: f107 4700 add.w r7, r7, #2147483648 ; 0x80000000 + 800c066: 4662 mov r2, ip + 800c068: 463b mov r3, r7 + 800c06a: 9904 ldr r1, [sp, #16] + 800c06c: e9c1 2302 strd r2, r3, [r1, #8] + 800c070: e011 b.n 800c096 <__kernel_rem_pio2+0x59a> + 800c072: 2700 movs r7, #0 + 800c074: 463d mov r5, r7 + 800c076: 9b06 ldr r3, [sp, #24] + 800c078: aa98 add r2, sp, #608 ; 0x260 + 800c07a: 4413 add r3, r2 + 800c07c: f5a3 769c sub.w r6, r3, #312 ; 0x138 + 800c080: 2c00 cmp r4, #0 + 800c082: da0f bge.n 800c0a4 <__kernel_rem_pio2+0x5a8> + 800c084: 9b00 ldr r3, [sp, #0] + 800c086: b10b cbz r3, 800c08c <__kernel_rem_pio2+0x590> + 800c088: f105 4500 add.w r5, r5, #2147483648 ; 0x80000000 + 800c08c: 463a mov r2, r7 + 800c08e: 462b mov r3, r5 + 800c090: 9904 ldr r1, [sp, #16] + 800c092: e9c1 2300 strd r2, r3, [r1] + 800c096: 9b05 ldr r3, [sp, #20] + 800c098: f003 0007 and.w r0, r3, #7 + 800c09c: f50d 7d19 add.w sp, sp, #612 ; 0x264 + 800c0a0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800c0a4: 4638 mov r0, r7 + 800c0a6: e976 2302 ldrd r2, r3, [r6, #-8]! + 800c0aa: 4629 mov r1, r5 + 800c0ac: f7f4 f866 bl 800017c <__adddf3> + 800c0b0: 3c01 subs r4, #1 + 800c0b2: 4607 mov r7, r0 + 800c0b4: 460d mov r5, r1 + 800c0b6: e7e3 b.n 800c080 <__kernel_rem_pio2+0x584> + 800c0b8: 4660 mov r0, ip + 800c0ba: e975 2302 ldrd r2, r3, [r5, #-8]! + 800c0be: 4639 mov r1, r7 + 800c0c0: f7f4 f85c bl 800017c <__adddf3> + 800c0c4: 3e01 subs r6, #1 + 800c0c6: 4684 mov ip, r0 + 800c0c8: 460f mov r7, r1 + 800c0ca: e7b0 b.n 800c02e <__kernel_rem_pio2+0x532> + 800c0cc: 4639 mov r1, r7 + 800c0ce: e7b5 b.n 800c03c <__kernel_rem_pio2+0x540> + 800c0d0: 4660 mov r0, ip + 800c0d2: e9f5 2302 ldrd r2, r3, [r5, #8]! + 800c0d6: 4639 mov r1, r7 + 800c0d8: f7f4 f850 bl 800017c <__adddf3> + 800c0dc: 3601 adds r6, #1 + 800c0de: 4684 mov ip, r0 + 800c0e0: 460f mov r7, r1 + 800c0e2: e7ba b.n 800c05a <__kernel_rem_pio2+0x55e> + 800c0e4: e97a 8902 ldrd r8, r9, [sl, #-8]! + 800c0e8: e9da 2302 ldrd r2, r3, [sl, #8] + 800c0ec: 4640 mov r0, r8 + 800c0ee: 4649 mov r1, r9 + 800c0f0: e9cd 2302 strd r2, r3, [sp, #8] + 800c0f4: f7f4 f842 bl 800017c <__adddf3> + 800c0f8: 4602 mov r2, r0 + 800c0fa: 460b mov r3, r1 + 800c0fc: 4606 mov r6, r0 + 800c0fe: 460f mov r7, r1 + 800c100: 4640 mov r0, r8 + 800c102: 4649 mov r1, r9 + 800c104: f7f4 f838 bl 8000178 <__aeabi_dsub> + 800c108: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c10c: f7f4 f836 bl 800017c <__adddf3> + 800c110: f10b 3bff add.w fp, fp, #4294967295 + 800c114: e9ca 0102 strd r0, r1, [sl, #8] + 800c118: e9ca 6700 strd r6, r7, [sl] + 800c11c: e757 b.n 800bfce <__kernel_rem_pio2+0x4d2> + 800c11e: e975 6702 ldrd r6, r7, [r5, #-8]! + 800c122: e9d5 2302 ldrd r2, r3, [r5, #8] + 800c126: 4630 mov r0, r6 + 800c128: 4639 mov r1, r7 + 800c12a: e9cd 2302 strd r2, r3, [sp, #8] + 800c12e: f7f4 f825 bl 800017c <__adddf3> + 800c132: 4602 mov r2, r0 + 800c134: 460b mov r3, r1 + 800c136: 4680 mov r8, r0 + 800c138: 4689 mov r9, r1 + 800c13a: 4630 mov r0, r6 + 800c13c: 4639 mov r1, r7 + 800c13e: f7f4 f81b bl 8000178 <__aeabi_dsub> + 800c142: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c146: f7f4 f819 bl 800017c <__adddf3> + 800c14a: f10a 3aff add.w sl, sl, #4294967295 + 800c14e: e9c5 0102 strd r0, r1, [r5, #8] + 800c152: e9c5 8900 strd r8, r9, [r5] + 800c156: e73f b.n 800bfd8 <__kernel_rem_pio2+0x4dc> + 800c158: 4638 mov r0, r7 + 800c15a: e975 2302 ldrd r2, r3, [r5, #-8]! + 800c15e: 4631 mov r1, r6 + 800c160: f7f4 f80c bl 800017c <__adddf3> + 800c164: 3c01 subs r4, #1 + 800c166: 4607 mov r7, r0 + 800c168: 460e mov r6, r1 + 800c16a: e73f b.n 800bfec <__kernel_rem_pio2+0x4f0> + 800c16c: 9b04 ldr r3, [sp, #16] + 800c16e: f100 4000 add.w r0, r0, #2147483648 ; 0x80000000 + 800c172: f101 4100 add.w r1, r1, #2147483648 ; 0x80000000 + 800c176: f106 4600 add.w r6, r6, #2147483648 ; 0x80000000 + 800c17a: 601d str r5, [r3, #0] + 800c17c: e9c3 0401 strd r0, r4, [r3, #4] + 800c180: e9c3 1703 strd r1, r7, [r3, #12] + 800c184: 615e str r6, [r3, #20] + 800c186: e786 b.n 800c096 <__kernel_rem_pio2+0x59a> + 800c188: 41700000 .word 0x41700000 + 800c18c: 3e700000 .word 0x3e700000 + +0800c190 <__kernel_sin>: + 800c190: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800c194: b086 sub sp, #24 + 800c196: e9cd 2300 strd r2, r3, [sp] + 800c19a: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800c19e: f1b3 5f79 cmp.w r3, #1044381696 ; 0x3e400000 + 800c1a2: 4682 mov sl, r0 + 800c1a4: 460c mov r4, r1 + 800c1a6: 9d0e ldr r5, [sp, #56] ; 0x38 + 800c1a8: da03 bge.n 800c1b2 <__kernel_sin+0x22> + 800c1aa: f7f4 fc4d bl 8000a48 <__aeabi_d2iz> + 800c1ae: 2800 cmp r0, #0 + 800c1b0: d050 beq.n 800c254 <__kernel_sin+0xc4> + 800c1b2: 4652 mov r2, sl + 800c1b4: 4623 mov r3, r4 + 800c1b6: 4650 mov r0, sl + 800c1b8: 4621 mov r1, r4 + 800c1ba: f7f4 f995 bl 80004e8 <__aeabi_dmul> + 800c1be: 4606 mov r6, r0 + 800c1c0: 460f mov r7, r1 + 800c1c2: 4602 mov r2, r0 + 800c1c4: 460b mov r3, r1 + 800c1c6: 4650 mov r0, sl + 800c1c8: 4621 mov r1, r4 + 800c1ca: f7f4 f98d bl 80004e8 <__aeabi_dmul> + 800c1ce: a33e add r3, pc, #248 ; (adr r3, 800c2c8 <__kernel_sin+0x138>) + 800c1d0: e9d3 2300 ldrd r2, r3, [r3] + 800c1d4: 4680 mov r8, r0 + 800c1d6: 4689 mov r9, r1 + 800c1d8: 4630 mov r0, r6 + 800c1da: 4639 mov r1, r7 + 800c1dc: f7f4 f984 bl 80004e8 <__aeabi_dmul> + 800c1e0: a33b add r3, pc, #236 ; (adr r3, 800c2d0 <__kernel_sin+0x140>) + 800c1e2: e9d3 2300 ldrd r2, r3, [r3] + 800c1e6: f7f3 ffc7 bl 8000178 <__aeabi_dsub> + 800c1ea: 4632 mov r2, r6 + 800c1ec: 463b mov r3, r7 + 800c1ee: f7f4 f97b bl 80004e8 <__aeabi_dmul> + 800c1f2: a339 add r3, pc, #228 ; (adr r3, 800c2d8 <__kernel_sin+0x148>) + 800c1f4: e9d3 2300 ldrd r2, r3, [r3] + 800c1f8: f7f3 ffc0 bl 800017c <__adddf3> + 800c1fc: 4632 mov r2, r6 + 800c1fe: 463b mov r3, r7 + 800c200: f7f4 f972 bl 80004e8 <__aeabi_dmul> + 800c204: a336 add r3, pc, #216 ; (adr r3, 800c2e0 <__kernel_sin+0x150>) + 800c206: e9d3 2300 ldrd r2, r3, [r3] + 800c20a: f7f3 ffb5 bl 8000178 <__aeabi_dsub> + 800c20e: 4632 mov r2, r6 + 800c210: 463b mov r3, r7 + 800c212: f7f4 f969 bl 80004e8 <__aeabi_dmul> + 800c216: a334 add r3, pc, #208 ; (adr r3, 800c2e8 <__kernel_sin+0x158>) + 800c218: e9d3 2300 ldrd r2, r3, [r3] + 800c21c: f7f3 ffae bl 800017c <__adddf3> + 800c220: e9cd 0102 strd r0, r1, [sp, #8] + 800c224: b9dd cbnz r5, 800c25e <__kernel_sin+0xce> + 800c226: 4602 mov r2, r0 + 800c228: 460b mov r3, r1 + 800c22a: 4630 mov r0, r6 + 800c22c: 4639 mov r1, r7 + 800c22e: f7f4 f95b bl 80004e8 <__aeabi_dmul> + 800c232: a32f add r3, pc, #188 ; (adr r3, 800c2f0 <__kernel_sin+0x160>) + 800c234: e9d3 2300 ldrd r2, r3, [r3] + 800c238: f7f3 ff9e bl 8000178 <__aeabi_dsub> + 800c23c: 4642 mov r2, r8 + 800c23e: 464b mov r3, r9 + 800c240: f7f4 f952 bl 80004e8 <__aeabi_dmul> + 800c244: 4602 mov r2, r0 + 800c246: 460b mov r3, r1 + 800c248: 4650 mov r0, sl + 800c24a: 4621 mov r1, r4 + 800c24c: f7f3 ff96 bl 800017c <__adddf3> + 800c250: 4682 mov sl, r0 + 800c252: 460c mov r4, r1 + 800c254: 4650 mov r0, sl + 800c256: 4621 mov r1, r4 + 800c258: b006 add sp, #24 + 800c25a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800c25e: 2200 movs r2, #0 + 800c260: e9dd 0100 ldrd r0, r1, [sp] + 800c264: 4b24 ldr r3, [pc, #144] ; (800c2f8 <__kernel_sin+0x168>) + 800c266: f7f4 f93f bl 80004e8 <__aeabi_dmul> + 800c26a: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c26e: e9cd 0104 strd r0, r1, [sp, #16] + 800c272: 4640 mov r0, r8 + 800c274: 4649 mov r1, r9 + 800c276: f7f4 f937 bl 80004e8 <__aeabi_dmul> + 800c27a: 4602 mov r2, r0 + 800c27c: 460b mov r3, r1 + 800c27e: e9dd 0104 ldrd r0, r1, [sp, #16] + 800c282: f7f3 ff79 bl 8000178 <__aeabi_dsub> + 800c286: 4632 mov r2, r6 + 800c288: 463b mov r3, r7 + 800c28a: f7f4 f92d bl 80004e8 <__aeabi_dmul> + 800c28e: e9dd 2300 ldrd r2, r3, [sp] + 800c292: f7f3 ff71 bl 8000178 <__aeabi_dsub> + 800c296: a316 add r3, pc, #88 ; (adr r3, 800c2f0 <__kernel_sin+0x160>) + 800c298: e9d3 2300 ldrd r2, r3, [r3] + 800c29c: 4606 mov r6, r0 + 800c29e: 460f mov r7, r1 + 800c2a0: 4640 mov r0, r8 + 800c2a2: 4649 mov r1, r9 + 800c2a4: f7f4 f920 bl 80004e8 <__aeabi_dmul> + 800c2a8: 4602 mov r2, r0 + 800c2aa: 460b mov r3, r1 + 800c2ac: 4630 mov r0, r6 + 800c2ae: 4639 mov r1, r7 + 800c2b0: f7f3 ff64 bl 800017c <__adddf3> + 800c2b4: 4602 mov r2, r0 + 800c2b6: 460b mov r3, r1 + 800c2b8: 4650 mov r0, sl + 800c2ba: 4621 mov r1, r4 + 800c2bc: f7f3 ff5c bl 8000178 <__aeabi_dsub> + 800c2c0: e7c6 b.n 800c250 <__kernel_sin+0xc0> + 800c2c2: bf00 nop + 800c2c4: f3af 8000 nop.w + 800c2c8: 5acfd57c .word 0x5acfd57c + 800c2cc: 3de5d93a .word 0x3de5d93a + 800c2d0: 8a2b9ceb .word 0x8a2b9ceb + 800c2d4: 3e5ae5e6 .word 0x3e5ae5e6 + 800c2d8: 57b1fe7d .word 0x57b1fe7d + 800c2dc: 3ec71de3 .word 0x3ec71de3 + 800c2e0: 19c161d5 .word 0x19c161d5 + 800c2e4: 3f2a01a0 .word 0x3f2a01a0 + 800c2e8: 1110f8a6 .word 0x1110f8a6 + 800c2ec: 3f811111 .word 0x3f811111 + 800c2f0: 55555549 .word 0x55555549 + 800c2f4: 3fc55555 .word 0x3fc55555 + 800c2f8: 3fe00000 .word 0x3fe00000 + 800c2fc: 00000000 .word 0x00000000 + +0800c300 <__kernel_tan>: + 800c300: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800c304: 461f mov r7, r3 + 800c306: 4bda ldr r3, [pc, #872] ; (800c670 <__kernel_tan+0x370>) + 800c308: f021 4600 bic.w r6, r1, #2147483648 ; 0x80000000 + 800c30c: b089 sub sp, #36 ; 0x24 + 800c30e: 429e cmp r6, r3 + 800c310: 4682 mov sl, r0 + 800c312: 468b mov fp, r1 + 800c314: 4690 mov r8, r2 + 800c316: f8dd 9048 ldr.w r9, [sp, #72] ; 0x48 + 800c31a: 9105 str r1, [sp, #20] + 800c31c: dc21 bgt.n 800c362 <__kernel_tan+0x62> + 800c31e: f7f4 fb93 bl 8000a48 <__aeabi_d2iz> + 800c322: 2800 cmp r0, #0 + 800c324: d140 bne.n 800c3a8 <__kernel_tan+0xa8> + 800c326: 4652 mov r2, sl + 800c328: f109 0301 add.w r3, r9, #1 + 800c32c: 4313 orrs r3, r2 + 800c32e: 4333 orrs r3, r6 + 800c330: d110 bne.n 800c354 <__kernel_tan+0x54> + 800c332: 4650 mov r0, sl + 800c334: 4659 mov r1, fp + 800c336: f7fd fce3 bl 8009d00 + 800c33a: 4602 mov r2, r0 + 800c33c: 2000 movs r0, #0 + 800c33e: 460b mov r3, r1 + 800c340: 49cc ldr r1, [pc, #816] ; (800c674 <__kernel_tan+0x374>) + 800c342: f7f4 f9fb bl 800073c <__aeabi_ddiv> + 800c346: 4682 mov sl, r0 + 800c348: 468b mov fp, r1 + 800c34a: 4650 mov r0, sl + 800c34c: 4659 mov r1, fp + 800c34e: b009 add sp, #36 ; 0x24 + 800c350: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800c354: f1b9 0f01 cmp.w r9, #1 + 800c358: d0f7 beq.n 800c34a <__kernel_tan+0x4a> + 800c35a: 465b mov r3, fp + 800c35c: 2000 movs r0, #0 + 800c35e: 49c6 ldr r1, [pc, #792] ; (800c678 <__kernel_tan+0x378>) + 800c360: e7ef b.n 800c342 <__kernel_tan+0x42> + 800c362: 4bc6 ldr r3, [pc, #792] ; (800c67c <__kernel_tan+0x37c>) + 800c364: 429e cmp r6, r3 + 800c366: dd1f ble.n 800c3a8 <__kernel_tan+0xa8> + 800c368: 2900 cmp r1, #0 + 800c36a: da04 bge.n 800c376 <__kernel_tan+0x76> + 800c36c: f10b 4300 add.w r3, fp, #2147483648 ; 0x80000000 + 800c370: 469b mov fp, r3 + 800c372: f107 4700 add.w r7, r7, #2147483648 ; 0x80000000 + 800c376: 4652 mov r2, sl + 800c378: a19f add r1, pc, #636 ; (adr r1, 800c5f8 <__kernel_tan+0x2f8>) + 800c37a: e9d1 0100 ldrd r0, r1, [r1] + 800c37e: 465b mov r3, fp + 800c380: f7f3 fefa bl 8000178 <__aeabi_dsub> + 800c384: 4604 mov r4, r0 + 800c386: 460d mov r5, r1 + 800c388: a19d add r1, pc, #628 ; (adr r1, 800c600 <__kernel_tan+0x300>) + 800c38a: e9d1 0100 ldrd r0, r1, [r1] + 800c38e: 4642 mov r2, r8 + 800c390: 463b mov r3, r7 + 800c392: f7f3 fef1 bl 8000178 <__aeabi_dsub> + 800c396: 4622 mov r2, r4 + 800c398: 462b mov r3, r5 + 800c39a: f7f3 feef bl 800017c <__adddf3> + 800c39e: f04f 0800 mov.w r8, #0 + 800c3a2: 4682 mov sl, r0 + 800c3a4: 468b mov fp, r1 + 800c3a6: 4647 mov r7, r8 + 800c3a8: 4652 mov r2, sl + 800c3aa: 465b mov r3, fp + 800c3ac: 4650 mov r0, sl + 800c3ae: 4659 mov r1, fp + 800c3b0: f7f4 f89a bl 80004e8 <__aeabi_dmul> + 800c3b4: 4602 mov r2, r0 + 800c3b6: 460b mov r3, r1 + 800c3b8: e9cd 0100 strd r0, r1, [sp] + 800c3bc: f7f4 f894 bl 80004e8 <__aeabi_dmul> + 800c3c0: e9dd 2300 ldrd r2, r3, [sp] + 800c3c4: 4604 mov r4, r0 + 800c3c6: 460d mov r5, r1 + 800c3c8: 4650 mov r0, sl + 800c3ca: 4659 mov r1, fp + 800c3cc: f7f4 f88c bl 80004e8 <__aeabi_dmul> + 800c3d0: a38d add r3, pc, #564 ; (adr r3, 800c608 <__kernel_tan+0x308>) + 800c3d2: e9d3 2300 ldrd r2, r3, [r3] + 800c3d6: e9cd 0102 strd r0, r1, [sp, #8] + 800c3da: 4620 mov r0, r4 + 800c3dc: 4629 mov r1, r5 + 800c3de: f7f4 f883 bl 80004e8 <__aeabi_dmul> + 800c3e2: a38b add r3, pc, #556 ; (adr r3, 800c610 <__kernel_tan+0x310>) + 800c3e4: e9d3 2300 ldrd r2, r3, [r3] + 800c3e8: f7f3 fec8 bl 800017c <__adddf3> + 800c3ec: 4622 mov r2, r4 + 800c3ee: 462b mov r3, r5 + 800c3f0: f7f4 f87a bl 80004e8 <__aeabi_dmul> + 800c3f4: a388 add r3, pc, #544 ; (adr r3, 800c618 <__kernel_tan+0x318>) + 800c3f6: e9d3 2300 ldrd r2, r3, [r3] + 800c3fa: f7f3 febf bl 800017c <__adddf3> + 800c3fe: 4622 mov r2, r4 + 800c400: 462b mov r3, r5 + 800c402: f7f4 f871 bl 80004e8 <__aeabi_dmul> + 800c406: a386 add r3, pc, #536 ; (adr r3, 800c620 <__kernel_tan+0x320>) + 800c408: e9d3 2300 ldrd r2, r3, [r3] + 800c40c: f7f3 feb6 bl 800017c <__adddf3> + 800c410: 4622 mov r2, r4 + 800c412: 462b mov r3, r5 + 800c414: f7f4 f868 bl 80004e8 <__aeabi_dmul> + 800c418: a383 add r3, pc, #524 ; (adr r3, 800c628 <__kernel_tan+0x328>) + 800c41a: e9d3 2300 ldrd r2, r3, [r3] + 800c41e: f7f3 fead bl 800017c <__adddf3> + 800c422: 4622 mov r2, r4 + 800c424: 462b mov r3, r5 + 800c426: f7f4 f85f bl 80004e8 <__aeabi_dmul> + 800c42a: a381 add r3, pc, #516 ; (adr r3, 800c630 <__kernel_tan+0x330>) + 800c42c: e9d3 2300 ldrd r2, r3, [r3] + 800c430: f7f3 fea4 bl 800017c <__adddf3> + 800c434: e9dd 2300 ldrd r2, r3, [sp] + 800c438: f7f4 f856 bl 80004e8 <__aeabi_dmul> + 800c43c: a37e add r3, pc, #504 ; (adr r3, 800c638 <__kernel_tan+0x338>) + 800c43e: e9d3 2300 ldrd r2, r3, [r3] + 800c442: e9cd 0106 strd r0, r1, [sp, #24] + 800c446: 4620 mov r0, r4 + 800c448: 4629 mov r1, r5 + 800c44a: f7f4 f84d bl 80004e8 <__aeabi_dmul> + 800c44e: a37c add r3, pc, #496 ; (adr r3, 800c640 <__kernel_tan+0x340>) + 800c450: e9d3 2300 ldrd r2, r3, [r3] + 800c454: f7f3 fe92 bl 800017c <__adddf3> + 800c458: 4622 mov r2, r4 + 800c45a: 462b mov r3, r5 + 800c45c: f7f4 f844 bl 80004e8 <__aeabi_dmul> + 800c460: a379 add r3, pc, #484 ; (adr r3, 800c648 <__kernel_tan+0x348>) + 800c462: e9d3 2300 ldrd r2, r3, [r3] + 800c466: f7f3 fe89 bl 800017c <__adddf3> + 800c46a: 4622 mov r2, r4 + 800c46c: 462b mov r3, r5 + 800c46e: f7f4 f83b bl 80004e8 <__aeabi_dmul> + 800c472: a377 add r3, pc, #476 ; (adr r3, 800c650 <__kernel_tan+0x350>) + 800c474: e9d3 2300 ldrd r2, r3, [r3] + 800c478: f7f3 fe80 bl 800017c <__adddf3> + 800c47c: 4622 mov r2, r4 + 800c47e: 462b mov r3, r5 + 800c480: f7f4 f832 bl 80004e8 <__aeabi_dmul> + 800c484: a374 add r3, pc, #464 ; (adr r3, 800c658 <__kernel_tan+0x358>) + 800c486: e9d3 2300 ldrd r2, r3, [r3] + 800c48a: f7f3 fe77 bl 800017c <__adddf3> + 800c48e: 4622 mov r2, r4 + 800c490: 462b mov r3, r5 + 800c492: f7f4 f829 bl 80004e8 <__aeabi_dmul> + 800c496: a372 add r3, pc, #456 ; (adr r3, 800c660 <__kernel_tan+0x360>) + 800c498: e9d3 2300 ldrd r2, r3, [r3] + 800c49c: f7f3 fe6e bl 800017c <__adddf3> + 800c4a0: 4602 mov r2, r0 + 800c4a2: 460b mov r3, r1 + 800c4a4: e9dd 0106 ldrd r0, r1, [sp, #24] + 800c4a8: f7f3 fe68 bl 800017c <__adddf3> + 800c4ac: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c4b0: f7f4 f81a bl 80004e8 <__aeabi_dmul> + 800c4b4: 4642 mov r2, r8 + 800c4b6: 463b mov r3, r7 + 800c4b8: f7f3 fe60 bl 800017c <__adddf3> + 800c4bc: e9dd 2300 ldrd r2, r3, [sp] + 800c4c0: f7f4 f812 bl 80004e8 <__aeabi_dmul> + 800c4c4: 4642 mov r2, r8 + 800c4c6: 463b mov r3, r7 + 800c4c8: f7f3 fe58 bl 800017c <__adddf3> + 800c4cc: a366 add r3, pc, #408 ; (adr r3, 800c668 <__kernel_tan+0x368>) + 800c4ce: e9d3 2300 ldrd r2, r3, [r3] + 800c4d2: 4604 mov r4, r0 + 800c4d4: 460d mov r5, r1 + 800c4d6: e9dd 0102 ldrd r0, r1, [sp, #8] + 800c4da: f7f4 f805 bl 80004e8 <__aeabi_dmul> + 800c4de: 4622 mov r2, r4 + 800c4e0: 462b mov r3, r5 + 800c4e2: f7f3 fe4b bl 800017c <__adddf3> + 800c4e6: e9cd 0100 strd r0, r1, [sp] + 800c4ea: 460b mov r3, r1 + 800c4ec: 4602 mov r2, r0 + 800c4ee: 4659 mov r1, fp + 800c4f0: 4650 mov r0, sl + 800c4f2: f7f3 fe43 bl 800017c <__adddf3> + 800c4f6: 4b61 ldr r3, [pc, #388] ; (800c67c <__kernel_tan+0x37c>) + 800c4f8: 4604 mov r4, r0 + 800c4fa: 429e cmp r6, r3 + 800c4fc: 460d mov r5, r1 + 800c4fe: dd3d ble.n 800c57c <__kernel_tan+0x27c> + 800c500: 4648 mov r0, r9 + 800c502: f7f3 ff87 bl 8000414 <__aeabi_i2d> + 800c506: 4622 mov r2, r4 + 800c508: 4680 mov r8, r0 + 800c50a: 4689 mov r9, r1 + 800c50c: 462b mov r3, r5 + 800c50e: 4620 mov r0, r4 + 800c510: 4629 mov r1, r5 + 800c512: f7f3 ffe9 bl 80004e8 <__aeabi_dmul> + 800c516: 4642 mov r2, r8 + 800c518: 4606 mov r6, r0 + 800c51a: 460f mov r7, r1 + 800c51c: 464b mov r3, r9 + 800c51e: 4620 mov r0, r4 + 800c520: 4629 mov r1, r5 + 800c522: f7f3 fe2b bl 800017c <__adddf3> + 800c526: 4602 mov r2, r0 + 800c528: 460b mov r3, r1 + 800c52a: 4630 mov r0, r6 + 800c52c: 4639 mov r1, r7 + 800c52e: f7f4 f905 bl 800073c <__aeabi_ddiv> + 800c532: e9dd 2300 ldrd r2, r3, [sp] + 800c536: f7f3 fe1f bl 8000178 <__aeabi_dsub> + 800c53a: 4602 mov r2, r0 + 800c53c: 460b mov r3, r1 + 800c53e: 4650 mov r0, sl + 800c540: 4659 mov r1, fp + 800c542: f7f3 fe19 bl 8000178 <__aeabi_dsub> + 800c546: 4602 mov r2, r0 + 800c548: 460b mov r3, r1 + 800c54a: f7f3 fe17 bl 800017c <__adddf3> + 800c54e: 4602 mov r2, r0 + 800c550: 460b mov r3, r1 + 800c552: 4640 mov r0, r8 + 800c554: 4649 mov r1, r9 + 800c556: f7f3 fe0f bl 8000178 <__aeabi_dsub> + 800c55a: 9b05 ldr r3, [sp, #20] + 800c55c: 4604 mov r4, r0 + 800c55e: 1798 asrs r0, r3, #30 + 800c560: f000 0002 and.w r0, r0, #2 + 800c564: f1c0 0001 rsb r0, r0, #1 + 800c568: 460d mov r5, r1 + 800c56a: f7f3 ff53 bl 8000414 <__aeabi_i2d> + 800c56e: 4602 mov r2, r0 + 800c570: 460b mov r3, r1 + 800c572: 4620 mov r0, r4 + 800c574: 4629 mov r1, r5 + 800c576: f7f3 ffb7 bl 80004e8 <__aeabi_dmul> + 800c57a: e6e4 b.n 800c346 <__kernel_tan+0x46> + 800c57c: f1b9 0f01 cmp.w r9, #1 + 800c580: d036 beq.n 800c5f0 <__kernel_tan+0x2f0> + 800c582: 460f mov r7, r1 + 800c584: 4602 mov r2, r0 + 800c586: 460b mov r3, r1 + 800c588: 2000 movs r0, #0 + 800c58a: 493b ldr r1, [pc, #236] ; (800c678 <__kernel_tan+0x378>) + 800c58c: f7f4 f8d6 bl 800073c <__aeabi_ddiv> + 800c590: 2600 movs r6, #0 + 800c592: e9cd 0102 strd r0, r1, [sp, #8] + 800c596: e9dd 4502 ldrd r4, r5, [sp, #8] + 800c59a: 4652 mov r2, sl + 800c59c: 465b mov r3, fp + 800c59e: 4630 mov r0, r6 + 800c5a0: 4639 mov r1, r7 + 800c5a2: f7f3 fde9 bl 8000178 <__aeabi_dsub> + 800c5a6: 4602 mov r2, r0 + 800c5a8: 460b mov r3, r1 + 800c5aa: e9dd 0100 ldrd r0, r1, [sp] + 800c5ae: f7f3 fde3 bl 8000178 <__aeabi_dsub> + 800c5b2: 4632 mov r2, r6 + 800c5b4: 462b mov r3, r5 + 800c5b6: f7f3 ff97 bl 80004e8 <__aeabi_dmul> + 800c5ba: 4632 mov r2, r6 + 800c5bc: 4682 mov sl, r0 + 800c5be: 468b mov fp, r1 + 800c5c0: 462b mov r3, r5 + 800c5c2: 4630 mov r0, r6 + 800c5c4: 4639 mov r1, r7 + 800c5c6: f7f3 ff8f bl 80004e8 <__aeabi_dmul> + 800c5ca: 2200 movs r2, #0 + 800c5cc: 4b29 ldr r3, [pc, #164] ; (800c674 <__kernel_tan+0x374>) + 800c5ce: f7f3 fdd5 bl 800017c <__adddf3> + 800c5d2: 4602 mov r2, r0 + 800c5d4: 460b mov r3, r1 + 800c5d6: 4650 mov r0, sl + 800c5d8: 4659 mov r1, fp + 800c5da: f7f3 fdcf bl 800017c <__adddf3> + 800c5de: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c5e2: f7f3 ff81 bl 80004e8 <__aeabi_dmul> + 800c5e6: 4632 mov r2, r6 + 800c5e8: 462b mov r3, r5 + 800c5ea: f7f3 fdc7 bl 800017c <__adddf3> + 800c5ee: e6aa b.n 800c346 <__kernel_tan+0x46> + 800c5f0: 4682 mov sl, r0 + 800c5f2: 468b mov fp, r1 + 800c5f4: e6a9 b.n 800c34a <__kernel_tan+0x4a> + 800c5f6: bf00 nop + 800c5f8: 54442d18 .word 0x54442d18 + 800c5fc: 3fe921fb .word 0x3fe921fb + 800c600: 33145c07 .word 0x33145c07 + 800c604: 3c81a626 .word 0x3c81a626 + 800c608: 74bf7ad4 .word 0x74bf7ad4 + 800c60c: 3efb2a70 .word 0x3efb2a70 + 800c610: 32f0a7e9 .word 0x32f0a7e9 + 800c614: 3f12b80f .word 0x3f12b80f + 800c618: 1a8d1068 .word 0x1a8d1068 + 800c61c: 3f3026f7 .word 0x3f3026f7 + 800c620: fee08315 .word 0xfee08315 + 800c624: 3f57dbc8 .word 0x3f57dbc8 + 800c628: e96e8493 .word 0xe96e8493 + 800c62c: 3f8226e3 .word 0x3f8226e3 + 800c630: 1bb341fe .word 0x1bb341fe + 800c634: 3faba1ba .word 0x3faba1ba + 800c638: db605373 .word 0xdb605373 + 800c63c: bef375cb .word 0xbef375cb + 800c640: a03792a6 .word 0xa03792a6 + 800c644: 3f147e88 .word 0x3f147e88 + 800c648: f2f26501 .word 0xf2f26501 + 800c64c: 3f4344d8 .word 0x3f4344d8 + 800c650: c9560328 .word 0xc9560328 + 800c654: 3f6d6d22 .word 0x3f6d6d22 + 800c658: 8406d637 .word 0x8406d637 + 800c65c: 3f9664f4 .word 0x3f9664f4 + 800c660: 1110fe7a .word 0x1110fe7a + 800c664: 3fc11111 .word 0x3fc11111 + 800c668: 55555563 .word 0x55555563 + 800c66c: 3fd55555 .word 0x3fd55555 + 800c670: 3e2fffff .word 0x3e2fffff + 800c674: 3ff00000 .word 0x3ff00000 + 800c678: bff00000 .word 0xbff00000 + 800c67c: 3fe59427 .word 0x3fe59427 + +0800c680 : + 800c680: f041 4100 orr.w r1, r1, #2147483648 ; 0x80000000 + 800c684: f501 1080 add.w r0, r1, #1048576 ; 0x100000 + 800c688: 0fc0 lsrs r0, r0, #31 + 800c68a: 4770 bx lr + 800c68c: 0000 movs r0, r0 + ... + +0800c690 : + 800c690: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 800c694: f3c1 580a ubfx r8, r1, #20, #11 + 800c698: f2a8 36ff subw r6, r8, #1023 ; 0x3ff + 800c69c: 2e13 cmp r6, #19 + 800c69e: 4607 mov r7, r0 + 800c6a0: 460b mov r3, r1 + 800c6a2: 460c mov r4, r1 + 800c6a4: 4605 mov r5, r0 + 800c6a6: dc35 bgt.n 800c714 + 800c6a8: 2e00 cmp r6, #0 + 800c6aa: da16 bge.n 800c6da + 800c6ac: a336 add r3, pc, #216 ; (adr r3, 800c788 ) + 800c6ae: e9d3 2300 ldrd r2, r3, [r3] + 800c6b2: f7f3 fd63 bl 800017c <__adddf3> + 800c6b6: 2200 movs r2, #0 + 800c6b8: 2300 movs r3, #0 + 800c6ba: f7f4 f9a5 bl 8000a08 <__aeabi_dcmpgt> + 800c6be: b148 cbz r0, 800c6d4 + 800c6c0: 2c00 cmp r4, #0 + 800c6c2: da5b bge.n 800c77c + 800c6c4: 2500 movs r5, #0 + 800c6c6: f024 4300 bic.w r3, r4, #2147483648 ; 0x80000000 + 800c6ca: 4a31 ldr r2, [pc, #196] ; (800c790 ) + 800c6cc: 433b orrs r3, r7 + 800c6ce: 42ab cmp r3, r5 + 800c6d0: bf18 it ne + 800c6d2: 4614 movne r4, r2 + 800c6d4: 4623 mov r3, r4 + 800c6d6: 462f mov r7, r5 + 800c6d8: e026 b.n 800c728 + 800c6da: 4a2e ldr r2, [pc, #184] ; (800c794 ) + 800c6dc: fa42 f806 asr.w r8, r2, r6 + 800c6e0: ea01 0208 and.w r2, r1, r8 + 800c6e4: 4302 orrs r2, r0 + 800c6e6: d01f beq.n 800c728 + 800c6e8: a327 add r3, pc, #156 ; (adr r3, 800c788 ) + 800c6ea: e9d3 2300 ldrd r2, r3, [r3] + 800c6ee: f7f3 fd45 bl 800017c <__adddf3> + 800c6f2: 2200 movs r2, #0 + 800c6f4: 2300 movs r3, #0 + 800c6f6: f7f4 f987 bl 8000a08 <__aeabi_dcmpgt> + 800c6fa: 2800 cmp r0, #0 + 800c6fc: d0ea beq.n 800c6d4 + 800c6fe: 2c00 cmp r4, #0 + 800c700: bfbe ittt lt + 800c702: f44f 1380 movlt.w r3, #1048576 ; 0x100000 + 800c706: fa43 f606 asrlt.w r6, r3, r6 + 800c70a: 19a4 addlt r4, r4, r6 + 800c70c: ea24 0408 bic.w r4, r4, r8 + 800c710: 2500 movs r5, #0 + 800c712: e7df b.n 800c6d4 + 800c714: 2e33 cmp r6, #51 ; 0x33 + 800c716: dd0b ble.n 800c730 + 800c718: f5b6 6f80 cmp.w r6, #1024 ; 0x400 + 800c71c: d104 bne.n 800c728 + 800c71e: 4602 mov r2, r0 + 800c720: f7f3 fd2c bl 800017c <__adddf3> + 800c724: 4607 mov r7, r0 + 800c726: 460b mov r3, r1 + 800c728: 4638 mov r0, r7 + 800c72a: 4619 mov r1, r3 + 800c72c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 800c730: f04f 32ff mov.w r2, #4294967295 + 800c734: f2a8 4813 subw r8, r8, #1043 ; 0x413 + 800c738: fa22 f808 lsr.w r8, r2, r8 + 800c73c: ea18 0f00 tst.w r8, r0 + 800c740: d0f2 beq.n 800c728 + 800c742: a311 add r3, pc, #68 ; (adr r3, 800c788 ) + 800c744: e9d3 2300 ldrd r2, r3, [r3] + 800c748: f7f3 fd18 bl 800017c <__adddf3> + 800c74c: 2200 movs r2, #0 + 800c74e: 2300 movs r3, #0 + 800c750: f7f4 f95a bl 8000a08 <__aeabi_dcmpgt> + 800c754: 2800 cmp r0, #0 + 800c756: d0bd beq.n 800c6d4 + 800c758: 2c00 cmp r4, #0 + 800c75a: da02 bge.n 800c762 + 800c75c: 2e14 cmp r6, #20 + 800c75e: d103 bne.n 800c768 + 800c760: 3401 adds r4, #1 + 800c762: ea25 0508 bic.w r5, r5, r8 + 800c766: e7b5 b.n 800c6d4 + 800c768: 2301 movs r3, #1 + 800c76a: f1c6 0634 rsb r6, r6, #52 ; 0x34 + 800c76e: fa03 f606 lsl.w r6, r3, r6 + 800c772: 4435 add r5, r6 + 800c774: 42bd cmp r5, r7 + 800c776: bf38 it cc + 800c778: 18e4 addcc r4, r4, r3 + 800c77a: e7f2 b.n 800c762 + 800c77c: 2500 movs r5, #0 + 800c77e: 462c mov r4, r5 + 800c780: e7a8 b.n 800c6d4 + 800c782: bf00 nop + 800c784: f3af 8000 nop.w + 800c788: 8800759c .word 0x8800759c + 800c78c: 7e37e43c .word 0x7e37e43c + 800c790: bff00000 .word 0xbff00000 + 800c794: 000fffff .word 0x000fffff + +0800c798 : + 800c798: 2000 movs r0, #0 + 800c79a: 4770 bx lr + +0800c79c : + 800c79c: 2000 movs r0, #0 + 800c79e: 4901 ldr r1, [pc, #4] ; (800c7a4 ) + 800c7a0: 4770 bx lr + 800c7a2: bf00 nop + 800c7a4: 7ff80000 .word 0x7ff80000 + +0800c7a8 : + 800c7a8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 800c7aa: f3c1 520a ubfx r2, r1, #20, #11 + 800c7ae: f2a2 3cff subw ip, r2, #1023 ; 0x3ff + 800c7b2: f1bc 0f13 cmp.w ip, #19 + 800c7b6: 4604 mov r4, r0 + 800c7b8: 460d mov r5, r1 + 800c7ba: 460b mov r3, r1 + 800c7bc: 4606 mov r6, r0 + 800c7be: ea4f 77d1 mov.w r7, r1, lsr #31 + 800c7c2: dc5a bgt.n 800c87a + 800c7c4: f1bc 0f00 cmp.w ip, #0 + 800c7c8: da2b bge.n 800c822 + 800c7ca: f021 4200 bic.w r2, r1, #2147483648 ; 0x80000000 + 800c7ce: 4302 orrs r2, r0 + 800c7d0: d023 beq.n 800c81a + 800c7d2: f3c1 0213 ubfx r2, r1, #0, #20 + 800c7d6: 4302 orrs r2, r0 + 800c7d8: 4256 negs r6, r2 + 800c7da: 4316 orrs r6, r2 + 800c7dc: 0c4b lsrs r3, r1, #17 + 800c7de: 0b36 lsrs r6, r6, #12 + 800c7e0: 4934 ldr r1, [pc, #208] ; (800c8b4 ) + 800c7e2: 045b lsls r3, r3, #17 + 800c7e4: f406 2600 and.w r6, r6, #524288 ; 0x80000 + 800c7e8: ea46 0503 orr.w r5, r6, r3 + 800c7ec: eb01 01c7 add.w r1, r1, r7, lsl #3 + 800c7f0: 4602 mov r2, r0 + 800c7f2: 462b mov r3, r5 + 800c7f4: e9d1 4500 ldrd r4, r5, [r1] + 800c7f8: 4620 mov r0, r4 + 800c7fa: 4629 mov r1, r5 + 800c7fc: f7f3 fcbe bl 800017c <__adddf3> + 800c800: e9cd 0100 strd r0, r1, [sp] + 800c804: e9dd 0100 ldrd r0, r1, [sp] + 800c808: 462b mov r3, r5 + 800c80a: 4622 mov r2, r4 + 800c80c: f7f3 fcb4 bl 8000178 <__aeabi_dsub> + 800c810: 4604 mov r4, r0 + 800c812: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800c816: ea43 75c7 orr.w r5, r3, r7, lsl #31 + 800c81a: 4620 mov r0, r4 + 800c81c: 4629 mov r1, r5 + 800c81e: b003 add sp, #12 + 800c820: bdf0 pop {r4, r5, r6, r7, pc} + 800c822: 4a25 ldr r2, [pc, #148] ; (800c8b8 ) + 800c824: fa42 f20c asr.w r2, r2, ip + 800c828: 4011 ands r1, r2 + 800c82a: 4301 orrs r1, r0 + 800c82c: d0f5 beq.n 800c81a + 800c82e: 0852 lsrs r2, r2, #1 + 800c830: ea05 0102 and.w r1, r5, r2 + 800c834: ea50 0601 orrs.w r6, r0, r1 + 800c838: d00c beq.n 800c854 + 800c83a: f44f 2380 mov.w r3, #262144 ; 0x40000 + 800c83e: f1bc 0f13 cmp.w ip, #19 + 800c842: bf0c ite eq + 800c844: f04f 4600 moveq.w r6, #2147483648 ; 0x80000000 + 800c848: 2600 movne r6, #0 + 800c84a: ea25 0202 bic.w r2, r5, r2 + 800c84e: fa43 f30c asr.w r3, r3, ip + 800c852: 4313 orrs r3, r2 + 800c854: 4917 ldr r1, [pc, #92] ; (800c8b4 ) + 800c856: 4632 mov r2, r6 + 800c858: eb01 07c7 add.w r7, r1, r7, lsl #3 + 800c85c: e9d7 4500 ldrd r4, r5, [r7] + 800c860: 4620 mov r0, r4 + 800c862: 4629 mov r1, r5 + 800c864: f7f3 fc8a bl 800017c <__adddf3> + 800c868: e9cd 0100 strd r0, r1, [sp] + 800c86c: e9dd 0100 ldrd r0, r1, [sp] + 800c870: 4622 mov r2, r4 + 800c872: 462b mov r3, r5 + 800c874: f7f3 fc80 bl 8000178 <__aeabi_dsub> + 800c878: e008 b.n 800c88c + 800c87a: f1bc 0f33 cmp.w ip, #51 ; 0x33 + 800c87e: dd08 ble.n 800c892 + 800c880: f5bc 6f80 cmp.w ip, #1024 ; 0x400 + 800c884: d1c9 bne.n 800c81a + 800c886: 4602 mov r2, r0 + 800c888: f7f3 fc78 bl 800017c <__adddf3> + 800c88c: 4604 mov r4, r0 + 800c88e: 460d mov r5, r1 + 800c890: e7c3 b.n 800c81a + 800c892: f2a2 4113 subw r1, r2, #1043 ; 0x413 + 800c896: f04f 32ff mov.w r2, #4294967295 + 800c89a: 40ca lsrs r2, r1 + 800c89c: 4210 tst r0, r2 + 800c89e: d0bc beq.n 800c81a + 800c8a0: 0852 lsrs r2, r2, #1 + 800c8a2: 4210 tst r0, r2 + 800c8a4: bf1f itttt ne + 800c8a6: f04f 4680 movne.w r6, #1073741824 ; 0x40000000 + 800c8aa: ea20 0202 bicne.w r2, r0, r2 + 800c8ae: 410e asrne r6, r1 + 800c8b0: 4316 orrne r6, r2 + 800c8b2: e7cf b.n 800c854 + 800c8b4: 0800e7a8 .word 0x0800e7a8 + 800c8b8: 000fffff .word 0x000fffff + 800c8bc: 00000000 .word 0x00000000 + +0800c8c0 : + 800c8c0: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c8c2: 4616 mov r6, r2 + 800c8c4: f3c1 520a ubfx r2, r1, #20, #11 + 800c8c8: 4604 mov r4, r0 + 800c8ca: 460d mov r5, r1 + 800c8cc: 460b mov r3, r1 + 800c8ce: b982 cbnz r2, 800c8f2 + 800c8d0: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800c8d4: 4303 orrs r3, r0 + 800c8d6: d034 beq.n 800c942 + 800c8d8: 4b2d ldr r3, [pc, #180] ; (800c990 ) + 800c8da: 2200 movs r2, #0 + 800c8dc: f7f3 fe04 bl 80004e8 <__aeabi_dmul> + 800c8e0: 4b2c ldr r3, [pc, #176] ; (800c994 ) + 800c8e2: 4604 mov r4, r0 + 800c8e4: 429e cmp r6, r3 + 800c8e6: 460d mov r5, r1 + 800c8e8: da0d bge.n 800c906 + 800c8ea: a325 add r3, pc, #148 ; (adr r3, 800c980 ) + 800c8ec: e9d3 2300 ldrd r2, r3, [r3] + 800c8f0: e01c b.n 800c92c + 800c8f2: f240 77ff movw r7, #2047 ; 0x7ff + 800c8f6: 42ba cmp r2, r7 + 800c8f8: d109 bne.n 800c90e + 800c8fa: 4602 mov r2, r0 + 800c8fc: f7f3 fc3e bl 800017c <__adddf3> + 800c900: 4604 mov r4, r0 + 800c902: 460d mov r5, r1 + 800c904: e01d b.n 800c942 + 800c906: 460b mov r3, r1 + 800c908: f3c1 520a ubfx r2, r1, #20, #11 + 800c90c: 3a36 subs r2, #54 ; 0x36 + 800c90e: f240 71fe movw r1, #2046 ; 0x7fe + 800c912: 4432 add r2, r6 + 800c914: 428a cmp r2, r1 + 800c916: dd0c ble.n 800c932 + 800c918: 4622 mov r2, r4 + 800c91a: 462b mov r3, r5 + 800c91c: a11a add r1, pc, #104 ; (adr r1, 800c988 ) + 800c91e: e9d1 0100 ldrd r0, r1, [r1] + 800c922: f000 f83b bl 800c99c + 800c926: a318 add r3, pc, #96 ; (adr r3, 800c988 ) + 800c928: e9d3 2300 ldrd r2, r3, [r3] + 800c92c: f7f3 fddc bl 80004e8 <__aeabi_dmul> + 800c930: e7e6 b.n 800c900 + 800c932: 2a00 cmp r2, #0 + 800c934: dd08 ble.n 800c948 + 800c936: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 800c93a: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 800c93e: ea43 5502 orr.w r5, r3, r2, lsl #20 + 800c942: 4620 mov r0, r4 + 800c944: 4629 mov r1, r5 + 800c946: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800c948: f112 0f35 cmn.w r2, #53 ; 0x35 + 800c94c: da0b bge.n 800c966 + 800c94e: f24c 3350 movw r3, #50000 ; 0xc350 + 800c952: 429e cmp r6, r3 + 800c954: 4622 mov r2, r4 + 800c956: 462b mov r3, r5 + 800c958: dce0 bgt.n 800c91c + 800c95a: a109 add r1, pc, #36 ; (adr r1, 800c980 ) + 800c95c: e9d1 0100 ldrd r0, r1, [r1] + 800c960: f000 f81c bl 800c99c + 800c964: e7c1 b.n 800c8ea + 800c966: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 800c96a: 3236 adds r2, #54 ; 0x36 + 800c96c: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 800c970: ea43 5502 orr.w r5, r3, r2, lsl #20 + 800c974: 4620 mov r0, r4 + 800c976: 4629 mov r1, r5 + 800c978: 2200 movs r2, #0 + 800c97a: 4b07 ldr r3, [pc, #28] ; (800c998 ) + 800c97c: e7d6 b.n 800c92c + 800c97e: bf00 nop + 800c980: c2f8f359 .word 0xc2f8f359 + 800c984: 01a56e1f .word 0x01a56e1f + 800c988: 8800759c .word 0x8800759c + 800c98c: 7e37e43c .word 0x7e37e43c + 800c990: 43500000 .word 0x43500000 + 800c994: ffff3cb0 .word 0xffff3cb0 + 800c998: 3c900000 .word 0x3c900000 + +0800c99c : + 800c99c: b530 push {r4, r5, lr} + 800c99e: f021 4200 bic.w r2, r1, #2147483648 ; 0x80000000 + 800c9a2: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 800c9a6: ea42 0503 orr.w r5, r2, r3 + 800c9aa: 4629 mov r1, r5 + 800c9ac: bd30 pop {r4, r5, pc} + ... + +0800c9b0 <__errno>: + 800c9b0: 4b01 ldr r3, [pc, #4] ; (800c9b8 <__errno+0x8>) + 800c9b2: 6818 ldr r0, [r3, #0] + 800c9b4: 4770 bx lr + 800c9b6: bf00 nop + 800c9b8: 20000060 .word 0x20000060 + +0800c9bc <_init>: + 800c9bc: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c9be: bf00 nop + 800c9c0: bcf8 pop {r3, r4, r5, r6, r7} + 800c9c2: bc08 pop {r3} + 800c9c4: 469e mov lr, r3 + 800c9c6: 4770 bx lr + +0800c9c8 <_fini>: + 800c9c8: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c9ca: bf00 nop + 800c9cc: bcf8 pop {r3, r4, r5, r6, r7} + 800c9ce: bc08 pop {r3} + 800c9d0: 469e mov lr, r3 + 800c9d2: 4770 bx lr diff --git a/Firmware/CubeIDE/Debug/Eleph.map b/Firmware/CubeIDE/Debug/Eleph.map new file mode 100644 index 0000000..d20b3eb --- /dev/null +++ b/Firmware/CubeIDE/Debug/Eleph.map @@ -0,0 +1,2893 @@ +Archive member included to satisfy reference by file (symbol) + +c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-exit.o) + c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o (exit) 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0x0000000000005000 xrw +FLASH 0x0000000008000000 0x0000000000010000 xr +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crti.o +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o +LOAD CMSIS/src/core_cm3.o +LOAD CMSIS/src/system_stm32f10x.o +LOAD Code/src/adc.o +LOAD Code/src/buttons.o +LOAD Code/src/gpio.o +LOAD Code/src/gps.o +LOAD Code/src/i2c.o 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c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a +END GROUP +START GROUP +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libnosys.a +END GROUP +START GROUP +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a +LOAD c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libnosys.a +END GROUP +LOAD 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c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_arm_cmpsf2.o) + .debug_frame 0x0000000000002954 0x24 c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_arm_fixsfsi.o) + .debug_frame 0x0000000000002978 0x24 c:/st/stm32cubeide_1.5.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_arm_fixunssfsi.o) diff --git a/Firmware/CubeIDE/Debug/Startup/startup_stm32f103c8tx.d b/Firmware/CubeIDE/Debug/Startup/startup_stm32f103c8tx.d new file mode 100644 index 0000000..0fd4101 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Startup/startup_stm32f103c8tx.d @@ -0,0 +1 @@ +Startup/startup_stm32f103c8tx.o: ../Startup/startup_stm32f103c8tx.s diff --git a/Firmware/CubeIDE/Debug/Startup/startup_stm32f103c8tx.o b/Firmware/CubeIDE/Debug/Startup/startup_stm32f103c8tx.o new file mode 100644 index 0000000..7a290e3 Binary files /dev/null and b/Firmware/CubeIDE/Debug/Startup/startup_stm32f103c8tx.o differ diff --git a/Firmware/CubeIDE/Debug/Startup/subdir.mk b/Firmware/CubeIDE/Debug/Startup/subdir.mk new file mode 100644 index 0000000..134a000 --- /dev/null +++ b/Firmware/CubeIDE/Debug/Startup/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Startup/startup_stm32f103c8tx.s + +OBJS += \ +./Startup/startup_stm32f103c8tx.o + +S_DEPS += \ +./Startup/startup_stm32f103c8tx.d + + +# Each subdirectory must supply rules for building sources it contributes +Startup/startup_stm32f103c8tx.o: ../Startup/startup_stm32f103c8tx.s + arm-none-eabi-gcc -mcpu=cortex-m3 -g3 -c -x assembler-with-cpp -MMD -MP -MF"Startup/startup_stm32f103c8tx.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + diff --git a/Firmware/CubeIDE/Debug/makefile b/Firmware/CubeIDE/Debug/makefile new file mode 100644 index 0000000..efa746d --- /dev/null +++ b/Firmware/CubeIDE/Debug/makefile @@ -0,0 +1,102 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Startup/subdir.mk +-include Code/src/subdir.mk +-include CMSIS/src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +BUILD_ARTIFACT_NAME := Eleph +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME).$(BUILD_ARTIFACT_EXTENSION) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +Eleph.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +Eleph.list \ + +OBJCOPY_HEX += \ +Eleph.hex \ + +OBJCOPY_BIN += \ +Eleph.bin \ + + +# All Target +all: main-build + +# Main-build Target +main-build: Eleph.elf secondary-outputs + +# Tool invocations +Eleph.elf: $(OBJS) $(USER_OBJS) D:\Projects\ARM\!ELEPH\eleph\Firmware\CubeIDE\STM32F103C8TX_FLASH.ld + arm-none-eabi-gcc -o "Eleph.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m3 -T"D:\Projects\ARM\!ELEPH\eleph\Firmware\CubeIDE\STM32F103C8TX_FLASH.ld" --specs=nosys.specs -Wl,-Map="Eleph.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +Eleph.list: $(EXECUTABLES) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "Eleph.list" + @echo 'Finished building: $@' + @echo ' ' + +Eleph.hex: $(EXECUTABLES) + arm-none-eabi-objcopy -O ihex $(EXECUTABLES) "Eleph.hex" + @echo 'Finished building: $@' + @echo ' ' + +Eleph.bin: $(EXECUTABLES) + arm-none-eabi-objcopy -O binary $(EXECUTABLES) "Eleph.bin" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_HEX) $(OBJCOPY_BIN) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified +.SECONDARY: + +-include ../makefile.targets diff --git a/Firmware/CubeIDE/Debug/objects.list b/Firmware/CubeIDE/Debug/objects.list new file mode 100644 index 0000000..b9b8695 --- /dev/null +++ b/Firmware/CubeIDE/Debug/objects.list @@ -0,0 +1,21 @@ +"CMSIS/src/core_cm3.o" +"CMSIS/src/system_stm32f10x.o" +"Code/src/adc.o" +"Code/src/buttons.o" +"Code/src/gpio.o" +"Code/src/gps.o" +"Code/src/i2c.o" +"Code/src/lrns.o" +"Code/src/m24c64.o" +"Code/src/main.o" +"Code/src/menu.o" +"Code/src/points.o" +"Code/src/service.o" +"Code/src/settings.o" +"Code/src/si4463.o" +"Code/src/spi.o" +"Code/src/ssd1306.o" +"Code/src/ssd1306_bitmaps.o" +"Code/src/timer.o" +"Code/src/uart.o" +"Startup/startup_stm32f103c8tx.o" diff --git a/Firmware/CubeIDE/Debug/objects.mk b/Firmware/CubeIDE/Debug/objects.mk new file mode 100644 index 0000000..dc31e16 --- /dev/null +++ b/Firmware/CubeIDE/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Firmware/CubeIDE/Debug/sources.mk b/Firmware/CubeIDE/Debug/sources.mk new file mode 100644 index 0000000..07b3d91 --- /dev/null +++ b/Firmware/CubeIDE/Debug/sources.mk @@ -0,0 +1,26 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +OBJCOPY_HEX := +SIZE_OUTPUT := +OBJDUMP_LIST := +EXECUTABLES := +OBJS := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := +OBJCOPY_BIN := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +CMSIS/src \ +Code/src \ +Startup \ + diff --git a/Firmware/CubeIDE/STM32F103C8TX_FLASH.ld b/Firmware/CubeIDE/STM32F103C8TX_FLASH.ld new file mode 100644 index 0000000..2db47b2 --- /dev/null +++ b/Firmware/CubeIDE/STM32F103C8TX_FLASH.ld @@ -0,0 +1,177 @@ +/** + ****************************************************************************** + * @file LinkerScript.ld + * @author Auto-generated by STM32CubeIDE + * @brief Linker script for STM32F103C8Tx Device from STM32F1 series + * 64Kbytes FLASH + * 20Kbytes RAM + * + * Set heap size, stack size and stack location according + * to application requirements. + * + * Set memory bank area and size if external memory is used + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Firmware/CubeIDE/Startup/startup_stm32f103c8tx.s b/Firmware/CubeIDE/Startup/startup_stm32f103c8tx.s new file mode 100644 index 0000000..3eb3ad2 --- /dev/null +++ b/Firmware/CubeIDE/Startup/startup_stm32f103c8tx.s @@ -0,0 +1,422 @@ +/** + ****************************************************************************** + * @file startup_stm32f103c8tx.s + * @author Auto-generated by STM32CubeIDE + * @brief STM32F103C8Tx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m3 +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32F103C8Tx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window Watchdog interrupt */ + .word PVD_IRQHandler /* PVD through EXTI line detection interrupt */ + .word TAMPER_IRQHandler /* Tamper interrupt */ + .word RTC_IRQHandler /* RTC global interrupt */ + .word FLASH_IRQHandler /* Flash global interrupt */ + .word RCC_IRQHandler /* RCC global interrupt */ + .word EXTI0_IRQHandler /* EXTI Line0 interrupt */ + .word EXTI1_IRQHandler /* EXTI Line1 interrupt */ + .word EXTI2_IRQHandler /* EXTI Line2 interrupt */ + .word EXTI3_IRQHandler /* EXTI Line3 interrupt */ + .word EXTI4_IRQHandler /* EXTI Line4 interrupt */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel1 global interrupt */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel2 global interrupt */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel3 global interrupt */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel4 global interrupt */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel5 global interrupt */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel6 global interrupt */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel7 global interrupt */ + .word ADC1_2_IRQHandler /* ADC1 and ADC2 global interrupt */ + .word USB_HP_CAN_TX_IRQHandler /* USB High Priority or CAN TX interrupts */ + .word USB_LP_CAN_RX0_IRQHandler /* USB Low Priority or CAN RX0 interrupts */ + .word CAN_RX1_IRQHandler /* CAN RX1 interrupt */ + .word CAN_SCE_IRQHandler /* CAN SCE interrupt */ + .word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupts */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM3_IRQHandler /* TIM3 global interrupt */ + .word TIM4_IRQHandler /* TIM4 global interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 error interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 event interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_IRQHandler /* SPI2 global interrupt */ + .word USART1_IRQHandler /* USART1 global interrupt */ + .word USART2_IRQHandler /* USART2 global interrupt */ + .word USART3_IRQHandler /* USART3 global interrupt */ + .word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */ + .word RTCAlarm_IRQHandler /* RTC Alarms through EXTI line interrupt */ + .word 0 /* Reserved */ + .word TIM8_BRK_IRQHandler /* TIM8 Break interrupt */ + .word TIM8_UP_IRQHandler /* TIM8 Update interrupt */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation interrupts */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare interrupt */ + .word ADC3_IRQHandler /* ADC3 global interrupt */ + .word FSMC_IRQHandler /* FSMC global interrupt */ + .word SDIO_IRQHandler /* SDIO global interrupt */ + .word TIM5_IRQHandler /* TIM5 global interrupt */ + .word SPI3_IRQHandler /* SPI3 global interrupt */ + .word UART4_IRQHandler /* UART4 global interrupt */ + .word UART5_IRQHandler /* UART5 global interrupt */ + .word TIM6_IRQHandler /* TIM6 global interrupt */ + .word TIM7_IRQHandler /* TIM7 global interrupt */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 global interrupt */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 global interrupt */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 global interrupt */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 and DMA2 Channel5 global interrupt */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN_TX_IRQHandler + .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN_RX0_IRQHandler + .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak SystemInit + +/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/ diff --git a/Firmware/README.md b/Firmware/README.md new file mode 100644 index 0000000..c0f817d --- /dev/null +++ b/Firmware/README.md @@ -0,0 +1,31 @@ +# Eleph Firmware +This folder contains firmware of the ELEPH + +## Source code +In the "**CubeIDE**" folder you can find project with the source code. As you can see it is created in CubeIDE and compiled using built-in **arm-none-eabi-gcc**. + +The project is configured that way it should compile on your computer without problems. Follow the next steps: + +* Open "**.project**" in [CubeIDE](https://www.st.com/en/development-tools/stm32cubeide.html) (tested on Version: 1.5.0) +* Current configuration should be **Debug**, otherwise "_Project -> Build Configurations -> Set Active -> Debug_" +* Clean current configuration "_Project -> Clean... -> Clean_" +* Build "_Project -> Build Project_" +* Enshure that you got "**Build Finished. 0 errors, 0 warnings.**" console message +* Flash the firmware directly from CubeIDE "_Run -> Run_", or use "**Eleph.hex**" or "**Eleph.bin**" from "_/CubeIDE/Debug_" folder to flash any of them using classic way via [ST-LINK Utility](https://www.st.com/en/development-tools/stsw-link004.html) + +## Different frequency programming + +Eleph uses [SI4463](https://www.silabs.com/wireless/proprietary/ezradiopro-sub-ghz-ics/device.si4463) transceiver, therefore everything that is related to the SI4463 registers programming was pre-configured using WDS3 software from Silicon Labs. You could download it from Silabs web-site: http://www.silabs.com/Support%20Documents/Software/WDS3-Setup.exe + +Since you have installed the WDS3, you could open ***.xml** file provided in _"/Supplementary/WDS/"_ directory, make changes and then click _"Generate source"_ button and select _"Save custom radio configuration header file"_. This file should have "**radio_config_Si4463.h**" name. Being placed in _"/Code/inc/"_ directory, it will incorporate changes to your build after compilation. + +Tested on WDS3 version 3.2.11.0 + +## LCD images preparation + +If you was curious enough, you may found that Eleph's "devices" and "radar" screens use predefined bitmap templates that appear on LCD before printing other strings. You could find them in _"/Supplementary/ScreenTemplates/"_ directory. + +In case if you want to change those templates, you cold use: +* FastLCD (by Bojan I. - MICRODESIGN, v1.2.0) in order to change it (currently available here http://avrproject.ru/nokia3310/FastLCD.exe). Also any graphical editor could be used. +* Image Generate (by Alex_EXE, v2.104) in order to convert bitmap into HEX array (available here https://alex-exe.ru/programm/image-generate/). +* Also i recommend to use DotMatrixTool (http://dotmatrixtool.com/) to generate separate symbols. \ No newline at end of file diff --git a/Hardware/Pictures/PCB_bottom_isometric.jpg b/Hardware/Pictures/PCB_bottom_isometric.jpg new file mode 100644 index 0000000..10ff040 Binary files /dev/null and b/Hardware/Pictures/PCB_bottom_isometric.jpg differ diff --git a/Hardware/Pictures/PCB_top.jpg b/Hardware/Pictures/PCB_top.jpg new file mode 100644 index 0000000..37d173b Binary files /dev/null and b/Hardware/Pictures/PCB_top.jpg differ diff --git a/Hardware/Pictures/PCB_top_isometric.jpg b/Hardware/Pictures/PCB_top_isometric.jpg new file mode 100644 index 0000000..f3c6d65 Binary files /dev/null and b/Hardware/Pictures/PCB_top_isometric.jpg differ diff --git a/Hardware/README.md b/Hardware/README.md new file mode 100644 index 0000000..87fb6ca --- /dev/null +++ b/Hardware/README.md @@ -0,0 +1,24 @@ +# Eleph Hardware +This folder contains hardware of the ELEPH + +## Schematic +In the "**Schematic**" folder you can find PDF file with the schematic diagram. + +* Please note that the schematic is **just for illustrative purposes** + +In other words the schematic only shows the correct way to make connections. The reason is that Eleph is based on a cheap modular hardware, instead of discrete components. That is why i see no value in designing PCB, because there are a dozen of different modules available on the market, and the same amount of different PCB variations for each modules combinations. I am pretty shure that the schematic is simple enough to assemble it on breadboard, or to create your own PCB based on your modules. + +## PCB +Due to the reasons mentioned above there is no PCB design for the project. Currently Eleph looks like shown below: + +Overview | Top | Bottom +------- | ------- | ------- +![Overview](Pictures/PCB_top.jpg) | ![Top](Pictures/PCB_top_isometric.jpg) | ![Bottom](Pictures/PCB_bottom_isometric.jpg) + +## Hardware +As you can see from the schematic, supply voltage VCC is 3.3V. Please make shure that all your modules have the same supply voltage and appropriate IO logic levels. +> For example, GPS module **Ublox Neo6M** used in the project, originally requires 5V supply voltage and uses onboard 3.3V LDO. That is why you have to depopulate LDO and solder a jumper between LDO's Vin and Vout pads to make GPS directly powered by your 3.3V source. + +Also you may have noticed a strange GPS antenna. From the "GPS" point of view it is not correct to use linearly polarized dipole antenna, because GPS requires an antenna with Right Hand Circular Polarization. I was forced to make DIY GPS dipole due to the sh**ty ceramic patch antenna i got with the module was not able to pick up satellites even under the clear sky. + +Couple of words about power supply. My supply chain is **_Single 18650 -> DC-DC Step-Up 5V -> LDO 3.3V_**. Such approach gives stable 3.3V output while 18650 changes it's state from charged (4.2V) to discharged (3.0V). BTW, i also use 18650 charging module with protection. diff --git a/Hardware/Schematic/LRNS_Eleph_Schematic_HW_V1.pdf b/Hardware/Schematic/LRNS_Eleph_Schematic_HW_V1.pdf new file mode 100644 index 0000000..39f6c28 Binary files /dev/null and b/Hardware/Schematic/LRNS_Eleph_Schematic_HW_V1.pdf differ diff --git a/README.md b/README.md index 2d5198c..6981abd 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,311 @@ -# eleph -GPS-based Local Relative Navigation System (LRNS) for group of up to 6 members +# **ELEPH** - _Never Get Lost!_ + +

+ +

+ +

+ Dedicated to my friend Alexander Sadaev, rock climber. +

+ +Eleph is a GPS-based Local Relative Navigation System (LRNS) for group of up to 6 members. It allows you to share your positional data in **real-time** among other Eleph-devices and navigate to each of them in a relative manner by providing **Distance** and **Azimuth** information - like RADAR does. + + + + + +## Demonstration + +Before diving into the details, watch the demo on YouTube: + +![YouTube Video!](Supplementary/Pictures/Two_Elephs_on_the_snow.jpg) + + + + + + +## Problem & Solution + +As long as you stay under cell-coverage a navigation, either absolute or relative, is not a problem at all. You just use your phone with maps and messengers to find or share locations. Things change when you go off-grid. Hiking, skiing, sailing or whatever outdoor activity are a potential place to lose sight of your teammates. How to navigate in the group? Hopefully, there are couple of solutions available on the market: + +* [LynQ](https://lynqme.com/pages/dev-consumer) +* [XQUAD](https://www.indiegogo.com/projects/xquad-smart-location-tracking-without-phones#/) +* [GoFindMe](https://www.indiegogo.com/projects/gofindme-a-gps-tracker-works-without-cell-service/#/) +* [GoTenna](https://gotennamesh.com/products/mesh) +* Also [GARMIN Dog collar](https://buy.garmin.com/en-US/US/c12522-p1.html) +* Also any [AIS](https://en.wikipedia.org/wiki/Automatic_identification_system) system + +unfortunately all of them are commercial. But not the **Eleph**! + +**Eleph** is _open-source/open-hardware_ device which contains all major features needed for group navigation, such as: + +* Detailed absolute positional information about each device in group +* RADAR-like interface with relative positional information about each device in group +* Memory slots to hold the position of any device and navigate it later +* GeoFence feature +* Timeout feature +* Alarm button + +Due to open-source and simple and cheap hardware, Eleph is highly flexible solution that could be adapted to any use case you want: + +* Hiking +* Climbing +* Sailing +* Hunting with the dogs +* Assets tracking +* and more... + + + + + + + +## Technology + +Eleph is written in pure C and runs on STM32 microcontroller. It has GPS module to receive positional data and synchronization signal, radio transceiver to exchange with radio packets between other devices, graphical display to show information on it, EEPROM memory IC to store coordinates, tactile buttons to control the device, buzzer to notify about events and couple of LEDs. + +![Packet structure](Supplementary/Pictures/Main_parts.png) + +GPS module provides NMEA-0183 stream at 9600 baud. Microcontroller process the stream using DMA and parse it. Fields being extracted are RMC, GGA, GSA, GSV. Those give us information about time, date, latitude, longitude, speed, course, altitude, satellites in view and in use, navigation mode and validness of data. + +GPS module also provides time synchronization signal - PPS. It is used as a time reference for the transmitting and receiving radio packets inside a current group of devices. Each group operates at the specific frequency channel, the way like regular radios. Each device in a group has unique predefined number from 1 to 6, so there are 6 members in a group maximum. Eleph uses TDMA technique to give channel access for each group member, so the device number corresponds to the time-slot occupied by device. There are 100 ms timer which starts counting from the rise of the PPS pulse. First 100 ms time-slot is used to parse and prepare positional data of the device. Next six time-slots are used to exchange with the positional data between devices via radio. A device is in TX state when time-slot number is equal to the device number, and in RX state otherwise. Remaining time before next PPS is reserved for relative positions calculation and displaying the results. + +Eleph uses GFSK transceiver and operates in LPD 433 MHz band (please make sure you are allowed to use those frequencies in your region, change otherwise). Data rate is 3000 bps, deviation is 6000 Hz (mod index = 4), channel spacing is 25 kHz. Packet structure is shown below. It consist of 29 bytes total and takes ~78 ms to be transmitted over-the-air. + +![Packet structure](Supplementary/Pictures/Radio_packet_structure.png) + +In order to calculate relative positions of other devices, Eleph uses two formulas. First one is [Haversine formula](https://en.wikipedia.org/wiki/Haversine_formula) which determines the distance between two points on a sphere. The second one is [Loxodrome formula](https://en.wikipedia.org/wiki/Rhumb_line) which determines bearing to a point on a sphere relative to true north. All calculations are performed with a highest possible, double precision, so the results are in a great agreement with my simulations on PC. Precision of the formulas is another matter. It is known that haversine formula is numerically better-conditioned for small distances, but on the other side it doesn't take into account ellipsoidness of the Earth and uses it's mean radius. Also it is known that loxodrome (or rhumb line) shows not-the-shortest way to reach point of interest (the shortest way is provided by orthodrome, or great circle route), but the constant bearing, which is more useful in practice. Anyway, my simulations using Google Earth Pro ruler leave me no concerns about accuracy of used formulas. According to them the error for both is less than 1% as long as the distance is smaller than 300 km (!). + +![Mercator](Supplementary/Pictures/Mercator_projection.png) + +

+ (courtesy of ESRI) +

+ + + + + + + +## User Manual + +There are only 5 buttons: UP and DOWN to scroll, OK to select, ESC to go back. The last one called PWR, but actually it switches alarm on and off. There are two actions with a button - short click or press & hold. Navigation through menu is intuitive, otherwise you will be notified about possible actions. + +![Buttons](Supplementary/Pictures/UserManual/Buttons.png) + +--- + +#### Main Menu + +After power up you start with main menu. Note the 'note' icon at the top right corner. It shows sound indication status. Press & hold ESC button in any menu to switch mute - '!' symbol will appear if sound is muted. + +

+ +

+ +--- + +#### Main Menu -> Devices + +"Devices" is the first of main screens. Here you can see the list of all devices online. First two rows describes "this" device (device that you hold in hand). They contain: +* **#** - This device number +* **ID** - Two characters ID of this device, only letters in capital +* **SOG** - Speed over Ground of this device, in kilometers per hour +* **COG** - Course over Ground of this device, in degrees related to the true North +* **AALT** - Absolute altitude of this device above mean sea level, in meters +* **Up and down arrows** - indicates that this device is on-air, i.e. synchronized with PPS and transmits & receives radio packets +* **Satellites signal indicator** - Has three bars: 1 bar - only GPS time is fixed; 2 bars - 2D fix (shown); 3 bars - 3D fix; shows 'X' otherwise +* **Battery indicator** - This device battery level; has 5 levels; empty is shown + +

+ +

+ +Other rows show other devices online. They contain: +* **#** - Other device number +* **ID** - Two characters ID of other device. If a device ID is something from "S1" to "S6" that means the row contains a GPS point loaded from the memory slot â„–1 to â„–6 respectively +* **DST** - Distance to that device/point, in meters +> (!) Values representation note: if any quantity doesn't contain decimal point in the value, that means the value is in _units_, otherwise the value is in _kilounits_. Example: DST = "35" means 35 meters; DST = "3.5" means 3.5 kilometers; DST = "35." means 35 kilometers. +* **BRG** - Bearing (azimuth) to that device/point, in degrees related to the true North +* **DALT** - Delta of altitudes to that device/point, in meters, signed. Positive values means that a device/point is above you, under otherwise +* **Bell** - Alarm indicator; that device has enabled alarm; buzzer will beep each time an alarm is received from any device +* **Sandglass** - Timeout occur for that device/point; buzzer will beep if timeout feature is enabled +* **Battery indicator** - Battery level of that device +* **Fence indicator** - That device/point is out of the virtual geo fence; work only in horizontal plane, i.e. fence for DST, excluding DALT; buzzer will beep if fence feature is enabled + +--- + +#### Main Menu -> Devices -> Each Device (in case of "this" device) + +When you press OK in "Devices" menu you will go to the menu called "Each Device". In that menu you could scroll up and down through all online devices. In case of this device is shown you get screen like shown below: + +

+ +

+ +* **# ID (me)** - Indicates the number of this device, it's ID and _(me)_ prompt +* **DD.MM.YY HH.MM.SS GMT** - Date and time in the described format +* **LAT** and **LON** - Latitude and Longitude in decimal degrees, signed; in addition to the sign a northing and easting indicators are shown +* **ALT** - Absolute altitude of this device above mean sea level, in meters +* **COG** - Course over Ground of this device, in degrees related to the true North +* **SOG** - Speed over Ground of this device, in kilometers per hour +* **FIX** - GPS fix status; V - invalid data; A - valid data; NO/2D/3D - fix type +* **DOP** - Positional Dilution of Precision; it is good when DOP < 6 +* **SAT** - Number of satellites in-view/in-use +* **BAT** - This device battery voltage +* **TOC** - Timeout counter; counts time since last GPS fix + +--- + +#### Main Menu -> Devices -> Each Device (in case of another device) + +When another device is displayed, the "Each Device" menu looks slightly different. Besides already described LAT, LON, ALT, DLT (delta altitude), BRG, SOG, COG, DST and BAT there are additional info: + +* **FIX** - 2D/3D fix type and LO/HI indicator; HI when DOP < 6, LO otherwise +* **TOC** - Counts time since last radio packet received from that device +* **FNC** - Fence alarm indicator +* **ALR** - Alarm indicator (main alarm, which is controlled manually by PWR button) + +

+ +

+ +When any kind of alarm is triggered, an alarm indicator is printed in negative: + +

+ +

+ +--- + +#### Main Menu -> Devices -> Each Device (in case of memory point) + +When a memory is selected during scroll, you will get: + +

+ +

+ +Since a memory point holds only LAT, LOT and ALT, the parameters you get are delta in altitudes, bearing and distance. The only type of alarm for a memory point is a fence alarm. TOC counts since you have loaded memory point to the list of devices online. + +--- + +#### Main Menu -> Devices -> Each Device -> Options + +By pressing OK in "Each Device" menu you could open options menu: + +

+ +

+ +When you choose "Save", you will be asked which memory slot you want to use to save a device. There are 5 memory slots total and only empty are shown. During the saving you should input 5-characters point name; current date will be automatically saved too. + +

+ +

+ +Also you could delete any device from the list of active devices by pressing "Delete". This works with both memory points and other devices. If you delete any other device which is online, it will disappear for a while and then appear again at the next packet reception. + +

+ +

+ +--- + +#### Main Menu -> Radar + +"Radar" is the second of main screens. It is a quintessence of the Eleph. The radar itself is a rectangle on the left. Top, right, bottom and left sides of the radar are North, East, South and West respectively. Single center dot is you, other devices or points are crosshairs with solid or void center - depends on selected or not respectively. Selection indicator in the list is a ">" cursor. There is your COG above radar, and radar range indicator **RNG** below. RNG shows the radius of the radar in meters; it changes with 20 meters increment. + +

+ +

+ +When you scroll through devices, the bottom bar shows you flags of the currently selected device. In case of memory point it also shows a point name: + +

+ +

+ +Also note the "!" sign ant the end of the row - that meant that this device has at least one of the alarm flags set (timeout, fence or alarm). + +You have the ability to hide any device on the radar screen, just press OK on selected device - its number will appear in negative and it will disappear from the radar (but not from the list): + +

+ +

+ +Note that when you hide any devices, the radar range RNG will be automatically adjusted to the farest unhided device: + +

+ +

+ +--- + +#### Main Menu -> Points + +When you access "Points" menu, you will see the list of all 5 memory slots. Here are a slot name, point name and date of save: + +

+ +

+ +Select any of them to open options: + +

+ +

+ +If you want to load a point to the list of online devices, just specify the device number to load in; only vacant devices are shown: + +

+ +

+ +--- + +#### Main Menu -> Settings + +The last but not the least is the "Settings" menu: + +

+ +

+ +Here you can edit them, restore the default settings or erase all EEPROM including memory points. When selecting "Edit" you will see the page with all Eleph's parameters: + +

+ +

+ +* **Device number** - This device number, 1 to 6 +* **Device ID** - This device ID +* **Freq channel** - LPD frequency channel, #1 corresponds to 433.075 MHz, #2 to 433.100 MHz, etc +* **TX power** - Radio output power; 10, 25, 40, 100 mW. Make sure you are allowed to use higher powers. Also note that some SI4463 modules don't have an antenna switch, if so do not use powers higher than 25 mW +* **Send interval** - Send radio packets each: 1, 5, 10, 30, 60 seconds. Be careful when select values other than 1 s because sometimes a GPS did not receive Leap Second correction yet and gives GPS time instead of UTC time. GPS and UTC time are not the same, so this will break synchronization between devices until all devices will receive Leap Second correction frame (transmitted by the GPS every 12.5 minutes) +* **Timeout thr** - Timeout alarm threshold in seconds with 10 s increment; timeout alarm is disabled if 0 +* **Fence thr** - Fence alarm threshold in meters with 10 m increment; fence alarm is disabled if 0 + +--- + +#### Main Menu -> Info + +Here you can get info about hardware/firmware revision and build date: + +

+ +

+ +--- + +## FAQ + +* _**Why is it called Eleph?**_ -Eleph stands for elephant. Elephants are a social animals, they form close bonds and stay in-touch - that is the main aim of the Eleph device. +* _**Why not LoRa?**_ -Believe or not, but i see no reason to use LoRa in the Eleph now. Mainly due to high price. Also the benefit in longer range is an object to investigate - i have doubts about it. But if the project will be further developed, i am not ruling out a switching to the LoRa modem, because most of the LoRa modems support FSK too - that is a good opportunity to try. +* _**Why there is no compass?**_ -When i started the project i thought that COG (Course over Ground) information from the GPS would be enough, and that the COG relates to the true north, while compass gives magnetic north. Obviously information about true north is more valuable. To my dismay i found such approach not working satisfyingly - my very old GPS module is too inaccurate in COG estimation... So better use newer GPS chips or your mechanical compass, or learn how to navigate using the Sun. +* _**Why there is no PCB designed?**_ -~~Partly due to my laziness,~~ but i would say: due to the hardware is fully modular, and some modules like GPS or radio you are able to get may differ from my. That is a headache to find certain modules - that is why i give you a freedom in building your own Eleph from a garbage of modules that lying on the shelf since ArDuInO times. Have another GPS? Use it! Have different radio? Modify the code and use it! +* _**Any plans to resume the project?**_ -Hope so. But more likely there will be a new generation of Eleph, with modern hardware, different interface and feature-set. Anyway i will try my best to support any enthusiast who wants to build the Eleph or participate in the project. +* _**How can i support the project?**_ -Eleph really needs your support. Main functionality is tested, but full and comprehensive outdoor tests are nor performed yet. You could build it, test it on your side and report an issue if so - that is the best way to support. diff --git a/Supplementary/Pictures/Eleph_logo.png b/Supplementary/Pictures/Eleph_logo.png new file mode 100644 index 0000000..4fdb531 Binary files /dev/null and b/Supplementary/Pictures/Eleph_logo.png differ diff --git a/Supplementary/Pictures/Main_parts.png b/Supplementary/Pictures/Main_parts.png new file mode 100644 index 0000000..dc520d2 Binary files /dev/null and b/Supplementary/Pictures/Main_parts.png differ diff --git a/Supplementary/Pictures/Mercator_projection.png b/Supplementary/Pictures/Mercator_projection.png new file mode 100644 index 0000000..8458e7d Binary files /dev/null and b/Supplementary/Pictures/Mercator_projection.png differ diff --git a/Supplementary/Pictures/Radio_packet_structure.png b/Supplementary/Pictures/Radio_packet_structure.png new file mode 100644 index 0000000..38414c2 Binary files /dev/null and b/Supplementary/Pictures/Radio_packet_structure.png differ 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a/Supplementary/Pictures/UserManual/Info.png b/Supplementary/Pictures/UserManual/Info.png new file mode 100644 index 0000000..f4d1e5d Binary files /dev/null and b/Supplementary/Pictures/UserManual/Info.png differ diff --git a/Supplementary/Pictures/UserManual/Main.png b/Supplementary/Pictures/UserManual/Main.png new file mode 100644 index 0000000..51002ea Binary files /dev/null and b/Supplementary/Pictures/UserManual/Main.png differ diff --git a/Supplementary/Pictures/UserManual/MemoryPoint.png b/Supplementary/Pictures/UserManual/MemoryPoint.png new file mode 100644 index 0000000..945f170 Binary files /dev/null and b/Supplementary/Pictures/UserManual/MemoryPoint.png differ diff --git a/Supplementary/Pictures/UserManual/PointLoad.png b/Supplementary/Pictures/UserManual/PointLoad.png new file mode 100644 index 0000000..7e53626 Binary files /dev/null and b/Supplementary/Pictures/UserManual/PointLoad.png differ diff --git a/Supplementary/Pictures/UserManual/PointOptions.png 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file mode 100644 index 0000000..1453393 Binary files /dev/null and b/Supplementary/Pictures/UserManual/RadarHide2.png differ diff --git a/Supplementary/Pictures/UserManual/RadarMemoryPoint.png b/Supplementary/Pictures/UserManual/RadarMemoryPoint.png new file mode 100644 index 0000000..a2ef8fc Binary files /dev/null and b/Supplementary/Pictures/UserManual/RadarMemoryPoint.png differ diff --git a/Supplementary/Pictures/UserManual/SaveDevice.png b/Supplementary/Pictures/UserManual/SaveDevice.png new file mode 100644 index 0000000..ed9b1ef Binary files /dev/null and b/Supplementary/Pictures/UserManual/SaveDevice.png differ diff --git a/Supplementary/Pictures/UserManual/Settings.png b/Supplementary/Pictures/UserManual/Settings.png new file mode 100644 index 0000000..2bf1bb4 Binary files /dev/null and b/Supplementary/Pictures/UserManual/Settings.png differ diff --git a/Supplementary/Pictures/UserManual/ThisDevice.png b/Supplementary/Pictures/UserManual/ThisDevice.png new file mode 100644 index 0000000..094b6cb Binary files /dev/null and b/Supplementary/Pictures/UserManual/ThisDevice.png differ diff --git a/Supplementary/README.md b/Supplementary/README.md new file mode 100644 index 0000000..3469015 --- /dev/null +++ b/Supplementary/README.md @@ -0,0 +1,6 @@ +# Eleph Supplementary +This folder contains supplementary materials for the ELEPH: + +* **Pictures** - graphical material for the front page +* **WDS** - Radio configuration software project file for si4463 (see _"/Firmware/README.md"_) +* **ScreenTemplates** - Template bitmaps for Eleph's menu (see _"/Firmware/README.md"_) \ No newline at end of file diff --git a/Supplementary/ScreenTemplates/DevicesTemplate.BMP b/Supplementary/ScreenTemplates/DevicesTemplate.BMP new file mode 100644 index 0000000..ab7edd9 Binary files /dev/null and b/Supplementary/ScreenTemplates/DevicesTemplate.BMP differ diff --git a/Supplementary/ScreenTemplates/Logo.BMP b/Supplementary/ScreenTemplates/Logo.BMP new file mode 100644 index 0000000..cab8d1c Binary files /dev/null and b/Supplementary/ScreenTemplates/Logo.BMP differ diff --git a/Supplementary/ScreenTemplates/RadarTemplate.BMP b/Supplementary/ScreenTemplates/RadarTemplate.BMP new file mode 100644 index 0000000..9503dc1 Binary files /dev/null and b/Supplementary/ScreenTemplates/RadarTemplate.BMP differ diff --git a/Supplementary/WDS/radio_config_Si4463.h b/Supplementary/WDS/radio_config_Si4463.h new file mode 100644 index 0000000..62d0eae --- /dev/null +++ b/Supplementary/WDS/radio_config_Si4463.h @@ -0,0 +1,633 @@ +/*! @file radio_config.h + * @brief This file contains the automatically generated + * configurations. + * + * @n WDS GUI Version: 3.2.11.0 + * @n Device: Si4463 Rev.: B1 + * + * @b COPYRIGHT + * @n Silicon Laboratories Confidential + * @n Copyright 2017 Silicon Laboratories, Inc. + * @n http://www.silabs.com + */ + +#ifndef RADIO_CONFIG_H_ +#define RADIO_CONFIG_H_ + +// USER DEFINED PARAMETERS +// Define your own parameters here + +// INPUT DATA +/* +// Crys_freq(Hz): 26000000 Crys_tol(ppm): 50 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 1 ANT_DIV: 0 PM_pattern: 0 +// MOD_type: 3 Rsymb(sps): 3000 Fdev(Hz): 6000 RXBW(Hz): 100000 Manchester: 0 AFC_en: 1 Rsymb_error: 0.0 Chip-Version: 2 +// RF Freq.(MHz): 433.05 API_TC: 29 fhst: 25000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1 +// +// # RX IF frequency is -406250 Hz +// # WB filter 1 (BW = 99.20 kHz); NB-filter 15 (BW = 22.48 kHz) +// +// Modulation index: 4 +*/ + + +// CONFIGURATION PARAMETERS +#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 26000000L +#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x01 +#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07 +#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03 +#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000 + + +// CONFIGURATION COMMANDS + +/* +// Command: RF_POWER_UP +// Description: Command to power-up the device and select the operational mode and functionality. +*/ +#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0x8C, 0xBA, 0x80 + +/* +// Command: RF_GPIO_PIN_CFG +// Description: Configures the GPIO pins. +*/ +#define RF_GPIO_PIN_CFG 0x13, 0x44, 0x08, 0x21, 0x20, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_GLOBAL_XO_TUNE_2 +// Number of properties: 2 +// Group ID: 0x00 +// Start ID: 0x00 +// Default values: 0x40, 0x00, +// Descriptions: +// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator. +// GLOBAL_CLK_CFG - Clock configuration options. +*/ +#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x46, 0x00 + +/* +// Set properties: RF_GLOBAL_CONFIG_1 +// Number of properties: 1 +// Group ID: 0x00 +// Start ID: 0x03 +// Default values: 0x20, +// Descriptions: +// GLOBAL_CONFIG - Global configuration settings. +*/ +#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60 + +/* +// Set properties: RF_INT_CTL_ENABLE_2 +// Number of properties: 2 +// Group ID: 0x01 +// Start ID: 0x00 +// Default values: 0x04, 0x00, +// Descriptions: +// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin. +// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin. +*/ +#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x18 + +/* +// Set properties: RF_FRR_CTL_A_MODE_4 +// Number of properties: 4 +// Group ID: 0x02 +// Start ID: 0x00 +// Default values: 0x01, 0x02, 0x09, 0x00, +// Descriptions: +// FRR_CTL_A_MODE - Fast Response Register A Configuration. +// FRR_CTL_B_MODE - Fast Response Register B Configuration. +// FRR_CTL_C_MODE - Fast Response Register C Configuration. +// FRR_CTL_D_MODE - Fast Response Register D Configuration. +*/ +#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x0A, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PREAMBLE_TX_LENGTH_9 +// Number of properties: 9 +// Group ID: 0x10 +// Start ID: 0x00 +// Default values: 0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PREAMBLE_TX_LENGTH - Configure length of TX Preamble. +// PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. +// PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern. +// PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern. +// PREAMBLE_CONFIG - General configuration bits for the Preamble field. +// PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern. +// PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern. +// PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern. +// PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern. +*/ +#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x08, 0x14, 0x00, 0x0F, 0x31, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_SYNC_CONFIG_5 +// Number of properties: 5 +// Group ID: 0x11 +// Start ID: 0x00 +// Default values: 0x01, 0x2D, 0xD4, 0x2D, 0xD4, +// Descriptions: +// SYNC_CONFIG - Sync Word configuration bits. +// SYNC_BITS_31_24 - Sync word. +// SYNC_BITS_23_16 - Sync word. +// SYNC_BITS_15_8 - Sync word. +// SYNC_BITS_7_0 - Sync word. +*/ +#define RF_SYNC_CONFIG_5 0x11, 0x11, 0x05, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00 + +/* +// Set properties: RF_PKT_CRC_CONFIG_7 +// Number of properties: 7 +// Group ID: 0x12 +// Start ID: 0x00 +// Default values: 0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, +// Descriptions: +// PKT_CRC_CONFIG - Select a CRC polynomial and seed. +// PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening) +// PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening) +// PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening) +// PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening) +// PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling. +// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet. +*/ +#define RF_PKT_CRC_CONFIG_7 0x11, 0x12, 0x07, 0x00, 0x84, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x02 + +/* +// Set properties: RF_PKT_LEN_12 +// Number of properties: 12 +// Group ID: 0x12 +// Start ID: 0x08 +// Default values: 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PKT_LEN - Configuration bits for reception of a variable length packet. +// PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s). +// PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length). +// PKT_TX_THRESHOLD - TX FIFO almost empty threshold. +// PKT_RX_THRESHOLD - RX FIFO Almost Full threshold. +// PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value. +// PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value. +// PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1. +// PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1. +// PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value. +// PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value. +// PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2. +*/ +#define RF_PKT_LEN_12 0x11, 0x12, 0x0C, 0x08, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x11, 0x04, 0xAA, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PKT_FIELD_2_CRC_CONFIG_12 +// Number of properties: 12 +// Group ID: 0x12 +// Start ID: 0x14 +// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2. +// PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value. +// PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value. +// PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3. +// PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3. +// PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value. +// PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value. +// PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4. +// PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4. +// PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value. +// PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value. +// PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5. +*/ +#define RF_PKT_FIELD_2_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PKT_FIELD_5_CRC_CONFIG_12 +// Number of properties: 12 +// Group ID: 0x12 +// Start ID: 0x20 +// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5. +// PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value. +// PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value. +// PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1. +// PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1. +// PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value. +// PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value. +// PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2. +// PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2. +// PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value. +// PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value. +// PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3. +*/ +#define RF_PKT_FIELD_5_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PKT_RX_FIELD_3_CRC_CONFIG_9 +// Number of properties: 9 +// Group ID: 0x12 +// Start ID: 0x2C +// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3. +// PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value. +// PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value. +// PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4. +// PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4. +// PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value. +// PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value. +// PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5. +// PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5. +*/ +#define RF_PKT_RX_FIELD_3_CRC_CONFIG_9 0x11, 0x12, 0x09, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_MODEM_MOD_TYPE_12 +// Number of properties: 12 +// Group ID: 0x20 +// Start ID: 0x00 +// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, +// Descriptions: +// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation. +// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits. +// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer. +// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate +// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate +// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate +// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. +// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. +// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. +// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. +// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. +// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. +*/ +#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x01, 0xD4, 0xC0, 0x05, 0x8C, 0xBA, 0x80, 0x00, 0x01 + +/* +// Set properties: RF_MODEM_FREQ_DEV_0_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x0C +// Default values: 0xD3, +// Descriptions: +// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. +*/ +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xE4 + +/* +// Set properties: RF_MODEM_TX_RAMP_DELAY_8 +// Number of properties: 8 +// Group ID: 0x20 +// Start ID: 0x18 +// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, +// Descriptions: +// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting. +// MODEM_MDM_CTRL - MDM control. +// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation. +// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number). +// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number). +// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number). +// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter. +// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter. +*/ +#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20 + +/* +// Set properties: RF_MODEM_BCR_OSR_1_9 +// Number of properties: 9 +// Group ID: 0x20 +// Start ID: 0x22 +// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, +// Descriptions: +// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). +// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). +// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number). +// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number). +// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number). +// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value. +// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value. +// MODEM_BCR_GEAR - RX BCR loop gear control. +// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop. +*/ +#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x04, 0x3B, 0x00, 0x78, 0xFD, 0x00, 0x3D, 0x02, 0xC2 + +/* +// Set properties: RF_MODEM_AFC_GEAR_7 +// Number of properties: 7 +// Group ID: 0x20 +// Start ID: 0x2C +// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0, +// Descriptions: +// MODEM_AFC_GEAR - RX AFC loop gear control. +// MODEM_AFC_WAIT - RX AFC loop wait time control. +// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. +// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. +// MODEM_AFC_LIMITER_1 - Set the AFC limiter value. +// MODEM_AFC_LIMITER_0 - Set the AFC limiter value. +// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. +*/ +#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0xC0, 0x0A, 0x48, 0x18, 0xC0 + +/* +// Set properties: RF_MODEM_AGC_CONTROL_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x35 +// Default values: 0xE0, +// Descriptions: +// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. +*/ +#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2 + +/* +// Set properties: RF_MODEM_AGC_WINDOW_SIZE_9 +// Number of properties: 9 +// Group ID: 0x20 +// Start ID: 0x38 +// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, +// Descriptions: +// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm. +// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors. +// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors. +// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression. +// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression. +// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold. +// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold. +// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code. +// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector. +*/ +#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0xED, 0xED, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x2B + +/* +// Set properties: RF_MODEM_OOK_CNT1_9 +// Number of properties: 9 +// Group ID: 0x20 +// Start ID: 0x42 +// Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, +// Descriptions: +// MODEM_OOK_CNT1 - OOK control. +// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. +// MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors. +// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode. +// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold. +// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold. +// MODEM_ANT_DIV_MODE - Antenna diversity mode settings. +// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. +// MODEM_RSSI_THRESH - Configures the RSSI threshold. +*/ +#define RF_MODEM_OOK_CNT1_9 0x11, 0x20, 0x09, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x00, 0x3C, 0x01, 0x80, 0xFF + +/* +// Set properties: RF_MODEM_RSSI_CONTROL_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x4C +// Default values: 0x01, +// Descriptions: +// MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s). +*/ +#define RF_MODEM_RSSI_CONTROL_1 0x11, 0x20, 0x01, 0x4C, 0x02 + +/* +// Set properties: RF_MODEM_RSSI_COMP_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x4E +// Default values: 0x32, +// Descriptions: +// MODEM_RSSI_COMP - RSSI compensation value. +*/ +#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40 + +/* +// Set properties: RF_MODEM_CLKGEN_BAND_1 +// Number of properties: 1 +// Group ID: 0x20 +// Start ID: 0x51 +// Default values: 0x08, +// Descriptions: +// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. +*/ +#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A + +/* +// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 +// Number of properties: 12 +// Group ID: 0x21 +// Start ID: 0x00 +// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, +// Descriptions: +// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. +*/ +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01 + +/* +// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 +// Number of properties: 12 +// Group ID: 0x21 +// Start ID: 0x0C +// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, +// Descriptions: +// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. +*/ +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66 + +/* +// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 +// Number of properties: 12 +// Group ID: 0x21 +// Start ID: 0x18 +// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, +// Descriptions: +// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. +// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. +*/ +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_PA_MODE_4 +// Number of properties: 4 +// Group ID: 0x22 +// Start ID: 0x00 +// Default values: 0x08, 0x7F, 0x00, 0x5D, +// Descriptions: +// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size). +// PA_PWR_LVL - Configuration of PA output power level. +// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source. +// PA_TC - Configuration of PA ramping parameters. +*/ +#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x05, 0x00, 0x3D + +/* +// Set properties: RF_SYNTH_PFDCP_CPFF_7 +// Number of properties: 7 +// Group ID: 0x23 +// Start ID: 0x00 +// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, +// Descriptions: +// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection. +// SYNTH_PFDCP_CPINT - Integration charge pump current selection. +// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path. +// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter. +// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter. +// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. +// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. +*/ +#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 + +/* +// Set properties: RF_MATCH_VALUE_1_12 +// Number of properties: 12 +// Group ID: 0x30 +// Start ID: 0x00 +// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// Descriptions: +// MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte. +// MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte. +// MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1. +// MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte. +// MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte. +// MATCH_CTRL_2 - Configuration of Match Byte 2. +// MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte. +// MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte. +// MATCH_CTRL_3 - Configuration of Match Byte 3. +// MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte. +// MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte. +// MATCH_CTRL_4 - Configuration of Match Byte 4. +*/ +#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +/* +// Set properties: RF_FREQ_CONTROL_INTE_8 +// Number of properties: 8 +// Group ID: 0x40 +// Start ID: 0x00 +// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, +// Descriptions: +// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number. +// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number. +// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number. +// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number. +// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size. +// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size. +// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. +// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. +*/ +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x0C, 0xFC, 0x0F, 0x07, 0xE0, 0x20, 0xFE + + +// AUTOMATICALLY GENERATED CODE! +// DO NOT EDIT/MODIFY BELOW THIS LINE! +// -------------------------------------------- + +#ifndef FIRMWARE_LOAD_COMPILE +#define RADIO_CONFIGURATION_DATA_ARRAY { \ + 0x07, RF_POWER_UP, \ + 0x08, RF_GPIO_PIN_CFG, \ + 0x06, RF_GLOBAL_XO_TUNE_2, \ + 0x05, RF_GLOBAL_CONFIG_1, \ + 0x06, RF_INT_CTL_ENABLE_2, \ + 0x08, RF_FRR_CTL_A_MODE_4, \ + 0x0D, RF_PREAMBLE_TX_LENGTH_9, \ + 0x09, RF_SYNC_CONFIG_5, \ + 0x0B, RF_PKT_CRC_CONFIG_7, \ + 0x10, RF_PKT_LEN_12, \ + 0x10, RF_PKT_FIELD_2_CRC_CONFIG_12, \ + 0x10, RF_PKT_FIELD_5_CRC_CONFIG_12, \ + 0x0D, RF_PKT_RX_FIELD_3_CRC_CONFIG_9, \ + 0x10, RF_MODEM_MOD_TYPE_12, \ + 0x05, RF_MODEM_FREQ_DEV_0_1, \ + 0x0C, RF_MODEM_TX_RAMP_DELAY_8, \ + 0x0D, RF_MODEM_BCR_OSR_1_9, \ + 0x0B, RF_MODEM_AFC_GEAR_7, \ + 0x05, RF_MODEM_AGC_CONTROL_1, \ + 0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \ + 0x0D, RF_MODEM_OOK_CNT1_9, \ + 0x05, RF_MODEM_RSSI_CONTROL_1, \ + 0x05, RF_MODEM_RSSI_COMP_1, \ + 0x05, RF_MODEM_CLKGEN_BAND_1, \ + 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \ + 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \ + 0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \ + 0x08, RF_PA_MODE_4, \ + 0x0B, RF_SYNTH_PFDCP_CPFF_7, \ + 0x10, RF_MATCH_VALUE_1_12, \ + 0x0C, RF_FREQ_CONTROL_INTE_8, \ + 0x00 \ + } +#else +#define RADIO_CONFIGURATION_DATA_ARRAY { 0 } +#endif + +// DEFAULT VALUES FOR CONFIGURATION PARAMETERS +#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L +#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00 +#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10 +#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01 +#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000 + +#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00 +#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00 +#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { } + +#ifndef RADIO_CONFIGURATION_DATA_ARRAY +#error "This property must be defined!" +#endif + +#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ +#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT +#endif + +#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER +#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT +#endif + +#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH +#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT +#endif + +#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP +#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT +#endif + +#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET +#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT +#endif + +#define RADIO_CONFIGURATION_DATA { \ + Radio_Configuration_Data_Array, \ + RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \ + RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \ + RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \ + RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \ + } + +#endif /* RADIO_CONFIG_H_ */ diff --git a/Supplementary/WDS/si4463_revb1_LRNS_ELEPH.xml b/Supplementary/WDS/si4463_revb1_LRNS_ELEPH.xml new file mode 100644 index 0000000..47718ae --- /dev/null +++ b/Supplementary/WDS/si4463_revb1_LRNS_ELEPH.xml @@ -0,0 +1,453 @@ + + + + + + + 1 + + + 433.05000 + + + 25 + + + + + False + + + 50 + + + 50 + + + 26 + + + 70 + + + + False + + + + 0 + + + + + False + + + 29 + + + 0 + + + 5 + + + + + + + 2 + + + 3 + + + 6 + + + False + + + 100 + + + 0 + + + 0 + + + + 2 + + + 0 + + + False + + + 255 + + + + + False + + + True + + + + True + + + False + + + False + + + True + + + True + + + + + + + 0 + + + + + 48 + + + 48 + + + 1 + + + True + + + True + + + True + + + + + False + + + + + True + + + + 4 + + + + + True + + + False + + + + + + 1 + + + FF FF + + + 0 + + + + + + True + + + False + + + + + False + + + True + + + + False + + + False + + + + + + + + + 0 + + + False + + + True + + + + 8 + + + 15 + + + False + + + 20 + + + + + + + 2 + + + 0 + + + + 2D D4 + + + + False + + + False + + + + + + + 7 + + + False + + + False + + + False + + + False + + + False + + + + + + + 7 + + + False + + + False + + + False + + + False + + + False + + + + + + + 7 + + + False + + + False + + + False + + + False + + + False + + + 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