system.vhd

-----------------------------------------------------------------------------
-- Copyright (C) 2005 IMEC                                                  -
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-- THIS CODE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''           -
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-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- File           : system.vhd
-- -----------------------------------------------------------------------------
-- Description : System top level contains the following units:
-- 1 - CPU (cpu.vhd]
-- 2 - Memory controller [memCtrl.vhd]
-- 3 - Internal memory [memory.vhd]
--------------------------------------------------------------------------------
-- Author         : Osman Allam
-- Date           : 07/02/2006
-- Version        : 1.0
-- Change history : 
----------------------------------------------------------------------------- 
-- This code was developed by Osman Allam during an internship at IMEC, 
-- in collaboration with Geert Vanwijnsberghe, Tom Tassignon en Steven 
-- Redant. The purpose of this code is to teach students good VHDL coding
-- style for writing complex behavioural models.
-----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

use WORK.micro_pk.all;
use WORK.micro_comp_pk.all;

entity system is
	port (
		rst : std_logic;
		clk : std_logic
	);
end entity;

architecture struct of system is
	-- buses
	signal fch_addr_bus : std_logic_vector (ADDR_WIDTH - 1 downto 0);
	signal DPT_addr_bus : std_logic_vector (ADDR_WIDTH - 1 downto 0);
	signal fch_data_in  : std_logic_vector (DATA_WIDTH - 1 downto 0);
	signal DPT_data_in  : std_logic_vector (DATA_WIDTH - 1 downto 0);
	signal DPT_data_out : std_logic_vector (DATA_WIDTH - 1 downto 0);
	signal mem_addr_bus : std_logic_vector (ADDR_WIDTH - 1 downto 0);
	signal mem_data_in  : std_logic_vector (DATA_WIDTH - 1 downto 0);
	signal mem_data_out : std_logic_vector (DATA_WIDTH - 1 downto 0);
	--
	signal fch_memRq    : std_logic;
	signal fch_memRd    : std_logic;
	signal fch_memReady : std_logic;
	signal DPT_memRq    : std_logic;
	signal DPT_memRd    : std_logic;
	signal DPT_memWr    : std_logic;
	signal DPT_memReady : std_logic;
	signal memRd        : std_logic;
	signal memWr        : std_logic;
	signal memReady     : std_logic;
	---
	signal IO_dataIn   : std_logic_vector (DATA_WIDTH - 1 downto 0);
	signal unconnected_databus1 : std_logic_vector (ADDR_WIDTH - 1 downto 0);
	signal unconnected_databus2 : std_logic_vector (DATA_WIDTH - 1 downto 0);
begin
	-- CPU
	cpu_1: cpu port map(
		rst => rst,
		clk => clk,
		-- Memory interface : Data
		rqDPT => DPT_memRq,
		rdDPT => DPT_memRd,
		wrDPT => DPT_memWr,
		addrDPT => DPT_addr_bus,
		inDPT => DPT_data_in,
		outDPT => DPT_data_out,
		memReadyDPT => DPT_memReady,
		-- Memory interface : Instructions
		rqFch => fch_memRq,
		rdFch => fch_memRd,
		addrFch => fch_addr_bus,
		inFch => fch_data_in,
		memReadyFch => fch_memReady,
		-- IO Unit interface
		deviceID => open,
		wordByte => open,
		IORd => open,
		IOWr => open,
		IOReady => '0',
		IO_dataIn => IO_dataIn,
		IO_dataOut => IO_dataIn		-- Los conectamos en bucle porque no los usamos
	);

	-- Memory Traffic Controller
	memoryTrafficControler: memCtrl port map(
		rst => rst,
		clk => clk,
		-- Data path
		rqDPT => DPT_memRq,
		rdDPT => DPT_memRd,
		wrDPT => DPT_memWr,
		addrDPT => DPT_addr_bus,
		inDPT => DPT_data_in,
		outDPT => DPT_data_out,
		readyDPT => DPT_memReady,
		-- Fetch unit
		rqFch => fch_memRq,
		rdFch => fch_memRd,
		addrFch => fch_addr_bus,
		inFch => fch_data_in,
		readyFch => fch_memReady,
		-- I/O unit
		rqIO => '0',
		rdIO => '0',
		wrIO => '0',
		addrIO => unconnected_databus1,
		inIO => unconnected_databus2,
		outIO => unconnected_databus2,	-- Los conectemos en blucle porque no los usamos
		readyIO => open,
		-- control signals
		addr => mem_addr_bus,
		dataIn => mem_data_in,
		dataOut => mem_data_out,
		memRd => memRd,
		memWr => memWr,
		memReady => memReady
	);

	-- Main Memory    
	mainMemory: memory port map(
		clk	=> clk,
		inBus	=> mem_data_in,
		addr	=> mem_addr_bus,
		rd	=> memRd,
		wr	=> memWr,
		outBus	=> mem_data_out,
		ready	=> memReady
	);
end architecture;