-
Notifications
You must be signed in to change notification settings - Fork 1
/
Test_SubClockDyn.v
57 lines (47 loc) · 1.01 KB
/
Test_SubClockDyn.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:02 03/02/2014
// Design Name: SubClockDyn
// Module Name: /home/eternia/Dropbox/Project Lab 1/Verilog/Test_SubClockDyn.v
// Project Name: Router
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: SubClockDyn
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_SubClockDyn;
// Inputs
reg CLK;
reg [25:0] Freq;
// Outputs
wire OUTCLK;
// Instantiate the Unit Under Test (UUT)
SubClockDyn uut (
.CLK(CLK),
.Freq(Freq),
.OUTCLK(OUTCLK)
);
initial begin
// Initialize Inputs
CLK = 0;
Freq = 240;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
while(1) begin
#10;
CLK = ~CLK;
end
end
endmodule