Rollup merge of rust-lang#76669 - lzutao:core_asm, r=Amanieu

Prefer asm! over llvm_asm! in core

Replace llvm_asm! with asm! in core.

x86 asm compare (in somecases I replaced generic type with String).
* https://rust.godbolt.org/z/59eEMv
* https://rust.godbolt.org/z/v78s6q
* https://rust.godbolt.org/z/7qYY41

Author: Dylan-DPC

library/core/src/hint.rs

@@ -111,7 +111,7 @@ pub fn spin_loop() {
 #[inline]
 #[unstable(feature = "test", issue = "50297")]
 #[allow(unreachable_code)] // this makes #[cfg] a bit easier below.
-pub fn black_box<T>(dummy: T) -> T {
+pub fn black_box<T>(mut dummy: T) -> T {
     // We need to "use" the argument in some way LLVM can't introspect, and on
     // targets that support it we can typically leverage inline assembly to do
     // this. LLVM's interpretation of inline assembly is that it's, well, a black
@@ -121,7 +121,31 @@ pub fn black_box<T>(dummy: T) -> T {
     #[cfg(not(miri))] // This is just a hint, so it is fine to skip in Miri.
     // SAFETY: the inline assembly is a no-op.
     unsafe {
-        llvm_asm!("" : : "r"(&dummy));
+        #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+        {
+            asm!(
+                "/* {0} */",
+                in(reg) &mut dummy,
+                // FIXME: We are using ATT syntax to support LLVM 8 and LLVM 9.
+                options(att_syntax, nostack, preserves_flags),
+            );
+        }
+        #[cfg(target_arch = "nvptx64")]
+        {
+            asm!(
+                "/* {0} */",
+                in(reg64) &mut dummy,
+                options(nostack, preserves_flags),
+            );
+        }
+        #[cfg(not(any(target_arch = "x86", target_arch = "x86_64", target_arch = "nvptx64")))]
+        {
+            asm!(
+                "/* {0} */",
+                in(reg) &mut dummy,
+                options(nostack, preserves_flags),
+            );
+        }
     }
 
     dummy

library/core/src/num/dec2flt/algorithm.rs

@@ -60,12 +60,19 @@ mod fpu_precision {
     fn set_cw(cw: u16) {
         // SAFETY: the `fldcw` instruction has been audited to be able to work correctly with
         // any `u16`
-        unsafe { llvm_asm!("fldcw $0" :: "m" (cw) :: "volatile") }
+        unsafe {
+            asm!(
+                "fldcw ({})",
+                in(reg) &cw,
+                // FIXME: We are using ATT syntax to support LLVM 8 and LLVM 9.
+                options(att_syntax, nostack),
+            )
+        }
     }
 
     /// Sets the precision field of the FPU to `T` and returns a `FPUControlWord`.
     pub fn set_precision<T>() -> FPUControlWord {
-        let cw = 0u16;
+        let mut cw = 0_u16;
 
         // Compute the value for the Precision Control field that is appropriate for `T`.
         let cw_precision = match size_of::<T>() {
@@ -78,7 +85,14 @@ mod fpu_precision {
         // `FPUControlWord` structure is dropped
         // SAFETY: the `fnstcw` instruction has been audited to be able to work correctly with
         // any `u16`
-        unsafe { llvm_asm!("fnstcw $0" : "=*m" (&cw) ::: "volatile") }
+        unsafe {
+            asm!(
+                "fnstcw ({})",
+                in(reg) &mut cw,
+                // FIXME: We are using ATT syntax to support LLVM 8 and LLVM 9.
+                options(att_syntax, nostack),
+            )
+        }
 
         // Set the control word to the desired precision. This is achieved by masking away the old
         // precision (bits 8 and 9, 0x300) and replacing it with the precision flag computed above.