Skip to content

Latest commit

 

History

History
19 lines (13 loc) · 605 Bytes

README.md

File metadata and controls

19 lines (13 loc) · 605 Bytes

simple-calculator-verilog

An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.

Subject: Hardware Description Language Language: Verilog

Code Previews and Waveforms

Quartus Prime Expected Outputs and Waveform enter image description here Visual Implementation in Quartus to FPGA enter image description here

DEC-SoC1 FPGA

Sample Implementation in FPGA enter image description here