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WPILibBrain Mapping#1043

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HunterBarclay merged 23 commits intodevAutodesk/synthesis:devfrom jwrigh/1746/wpilibbrain-mappingAutodesk/synthesis:jwrigh/1746/wpilibbrain-mappingCopy head branch name to clipboardJul 26, 2024

+327-64

Commits

Commits on Jul 19, 2024

• preliminary ws data parsing

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Commits on Jul 23, 2024

• added SimDevice class and RCConfigPwmGroupModal now selects from drivers

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  c2a1807

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• working mapping for pwm, can still needs work

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Commits on Jul 24, 2024

• only show initialized pwm ports in RCConfigPWMGroupModal

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  a414245

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• store joint info in driver for name display in PWM/CAN group modal

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• formatted and fixed lint warnings

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  6de7122

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• Merge branch 'dev' of github.com:Autodesk/synthesis into jwrigh/1746/wpilibbrain-mapping

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  81896d3

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• fix build and spelling

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  38cf0dc

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• format again :/

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  3e8d98f

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• reimport RCConfigPWMGroupModal to fix resolution error?

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  20d1fe8

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• change to relative import instead of alias

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• Rename RCConfigPwmGroupModal.tsx to RCConfigPWMGroupModal.tsx

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• back to path alias after rename

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  06ca91c

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• deleted unused wpilib behaviors

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• Update fission/src/systems/simulation/wpilib_brain/WPILibBrain.ts

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• Update fission/src/ui/modals/configuring/rio-config/RCConfigPWMGroupModal.tsx

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  PepperLola

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• fixed syntax error

  PepperLola

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  876e4d7

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• formatted

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  eaa403b

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• Merge branch 'dev' of github.com:Autodesk/synthesis into jwrigh/1746/wpilibbrain-mapping

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• fixed build error with SynthesisBrain usage

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Commits on Jul 26, 2024

• deleted commented/unused code and debug logs

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  4c25491

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• Merge branch 'dev' of github.com:Autodesk/synthesis into jwrigh/1746/wpilibbrain-mapping

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  35d0069

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• fixed build errors

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  a78113e

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