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DE10-Lite_Pin-Assignment.qsf
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DE10-Lite_Pin-Assignment.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition
# Date created = 14:39:57 June 20, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# teste_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY Sistema
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:39:57 JUNE 20, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_location_assignment PIN_C10 -to dadosIN[0]
set_location_assignment PIN_C11 -to dadosIN[1]
set_location_assignment PIN_D12 -to dadosIN[2]
set_location_assignment PIN_C12 -to dadosIN[3]
set_location_assignment PIN_A12 -to dadosIN[4]
set_location_assignment PIN_B12 -to dadosIN[5]
set_location_assignment PIN_A13 -to dadosIN[6]
set_location_assignment PIN_A14 -to dadosIN[7]
set_global_assignment -name ENABLE_OCT_DONE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_P11 -to realClk
set_location_assignment PIN_A8 -to estado[0]
set_location_assignment PIN_A9 -to estado[1]
set_location_assignment PIN_A10 -to estado[2]
set_location_assignment PIN_B10 -to estado[3]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_location_assignment PIN_C17 -to disp1[6]
set_location_assignment PIN_D17 -to disp1[5]
set_location_assignment PIN_E16 -to disp1[4]
set_location_assignment PIN_C16 -to disp1[3]
set_location_assignment PIN_C15 -to disp1[2]
set_location_assignment PIN_E15 -to disp1[1]
set_location_assignment PIN_C14 -to disp1[0]
set_location_assignment PIN_B17 -to disp2[6]
set_location_assignment PIN_A18 -to disp2[5]
set_location_assignment PIN_A17 -to disp2[4]
set_location_assignment PIN_B16 -to disp2[3]
set_location_assignment PIN_E18 -to disp2[2]
set_location_assignment PIN_D18 -to disp2[1]
set_location_assignment PIN_C18 -to disp2[0]
set_location_assignment PIN_B22 -to disp3[6]
set_location_assignment PIN_C22 -to disp3[5]
set_location_assignment PIN_B21 -to disp3[4]
set_location_assignment PIN_A21 -to disp3[3]
set_location_assignment PIN_B19 -to disp3[2]
set_location_assignment PIN_A20 -to disp3[1]
set_location_assignment PIN_B20 -to disp3[0]
set_location_assignment PIN_E17 -to disp4[6]
set_location_assignment PIN_D19 -to disp4[5]
set_location_assignment PIN_C20 -to disp4[4]
set_location_assignment PIN_C19 -to disp4[3]
set_location_assignment PIN_E21 -to disp4[2]
set_location_assignment PIN_E22 -to disp4[1]
set_location_assignment PIN_F21 -to disp4[0]
set_global_assignment -name VERILOG_FILE divisor.v
set_global_assignment -name VERILOG_FILE DeBounce.v
set_global_assignment -name VERILOG_FILE mux2_5b.v
set_global_assignment -name VERILOG_FILE ula_ctrl.v
set_global_assignment -name VERILOG_FILE moduloSaida.v
set_global_assignment -name VERILOG_FILE mux4_32b.v
set_global_assignment -name VERILOG_FILE shiftl2.v
set_global_assignment -name VERILOG_FILE bancoreg.v
set_global_assignment -name VERILOG_FILE decodDisplay.v
set_global_assignment -name VERILOG_FILE registrador32b.v
set_global_assignment -name VERILOG_FILE mux2_32b.v
set_global_assignment -name VERILOG_FILE memoria.v
set_global_assignment -name VERILOG_FILE extensor.v
set_global_assignment -name VERILOG_FILE ula.v
set_global_assignment -name VERILOG_FILE ctrl_undd.v
set_global_assignment -name VERILOG_FILE teste.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_global_assignment -name VERILOG_FILE processador.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform2.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform3.vwf
set_global_assignment -name VERILOG_FILE stack.v
set_global_assignment -name VERILOG_FILE registradorPC.v
set_location_assignment PIN_B14 -to rst
set_location_assignment PIN_D13 -to estado[4]
set_location_assignment PIN_C13 -to estado[5]
set_location_assignment PIN_E14 -to estado[6]
set_location_assignment PIN_D14 -to estado[7]
set_location_assignment PIN_A11 -to estado[8]
set_location_assignment PIN_B11 -to estado[9]
set_global_assignment -name VERILOG_FILE sigEnter.v
set_location_assignment PIN_F15 -to chave
set_location_assignment PIN_F18 -to disp5[0]
set_location_assignment PIN_E20 -to disp5[1]
set_location_assignment PIN_E19 -to disp5[2]
set_location_assignment PIN_J18 -to disp5[3]
set_location_assignment PIN_H19 -to disp5[4]
set_location_assignment PIN_F19 -to disp5[5]
set_location_assignment PIN_F20 -to disp5[6]
set_global_assignment -name VERILOG_FILE Sistema.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top