Bump riscv_nn and connect new signal

AlSaqr-platform · Jul 26, 2024 · ffe0ebe · ffe0ebe
1 parent e8adee3
commit ffe0ebe
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Showing 2 changed files with 3 additions and 2 deletions.
diff --git a/Bender.yml b/Bender.yml
@@ -27,7 +27,7 @@ dependencies:
   timer_unit:             { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 }
   common_cells:           { git: "https://github.com/pulp-platform/common_cells.git", version: 1.13.1 }
   tech_cells_generic:     { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.4 }
-  riscv:                  { git: "https://github.com/AlSaqr-platform/riscv_nn.git", rev: "9092e58e6c7d41e4dd19308576ef5fbcbc8c84c2"} # branch: shaheen
+  riscv:                  { git: "https://github.com/AlSaqr-platform/riscv_nn.git", rev: "291ad04adb290e8f3aa80c22e5528d0640f5a8ae"} # branch: alsaqr-2.0
   scm:                    { git: "https://github.com/pulp-platform/scm.git", version: 1.0.1}
   hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 }
   hci:                    { git: "https://github.com/pulp-platform/hci.git", version: 1.0.8 }

diff --git a/rtl/core_region.sv b/rtl/core_region.sv
@@ -265,7 +265,8 @@ module core_region
         .apu_master_flags_i    ( apu_master_flags_i    ),
 
         .ext_perf_counters_i   ( perf_counters         ),
-        .fregfile_disable_i    ( 1'b1                  )   //disable FP regfile
+        .fregfile_disable_i    ( 1'b1                  ),   //disable FP regfile
+        .data_unaligned_o      (                       )
       ); 
     end else begin: CL_CORE
       assign boot_addr = boot_addr_i & 32'hFFFFFF00; // RI5CY expects 0x80 offset, Ibex expects 0x00 offset (adds reset offset 0x80 internally)