Instantiate snitch icache.

AlSaqr-platform · Oct 7, 2024 · de1213c · de1213c
1 parent 94fae1c
commit de1213c
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Showing 2 changed files with 81 additions and 12 deletions.
diff --git a/Bender.yml b/Bender.yml
@@ -19,6 +19,7 @@ dependencies:
   event_unit_flex:        { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: "1.4.1" }
   mchan:                  { git: "https://github.com/pulp-platform/mchan.git", version: 1.2.2 }
   hier-icache:            { git: "https://github.com/pulp-platform/hier-icache.git", rev: "1e94c16b8f3082af40cc7e579027dc485202c1d6" }
+  cluster_icache:         { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "8114ab36fd446f76cd1e9f139f12a62ab1fb9a6a" } # michaero/branch: astral_cut_path
   icache_mp_128_pf:       { git: "https://github.com/pulp-platform/icache_mp_128_pf.git", rev: "6f2e54102001230db9c82432bf9e011842419a48" }
   icache_private:         { git: "https://github.com/AlSaqr-platform/icache_private.git", rev: "84436443d3a2dbad0b94a85c2c5cc8915632fd26" }
   cluster_peripherals:    { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 }
@@ -57,16 +58,8 @@ sources:
     # Level 1
   - rtl/cluster_peripherals.sv
   - rtl/core_demux.sv
+  - rtl/core_region.sv
     # Level 2
-  - target: rtl
-    defines:
-      TRACE_EXECUTION: ~
-    files:
-      - rtl/core_region.sv
-  - target: not(rtl)
-    files:
-      - rtl/core_region.sv
-    # Level 3
   - rtl/pulp_cluster.sv
 
   - target: tb_cluster_standalone

diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv
@@ -25,6 +25,7 @@ import hci_package::*;
 `include "axi/typedef.svh"
 `include "axi/assign.svh"
 
+`define SNITCH_ICACHE
 
 module pulp_cluster
 #(
@@ -1097,6 +1098,80 @@ module pulp_cluster
     end
   endgenerate
 
+`ifdef SNITCH_ICACHE
+  instr_axi_req_t s_core_instr_bus_req;
+  instr_axi_resp_t s_core_instr_bus_resp;
+
+  always_comb begin
+    s_core_instr_bus.aw_addr = '0;
+    s_core_instr_bus.ar_addr = '0;
+    `AXI_SET_FROM_REQ(s_core_instr_bus, s_core_instr_bus_req)
+  end
+  `AXI_ASSIGN_TO_RESP(s_core_instr_bus_resp, s_core_instr_bus)
+
+  pulp_icache_wrap #(
+    .NumFetchPorts  ( Cfg.NumCores                                 ),
+    .L0_LINE_COUNT  ( Cfg.iCachePrivateSize*8/256                  ),
+    .LINE_WIDTH     ( 256                                          ), // Ideally 32*NumCores
+    .LINE_COUNT     ( Cfg.iCacheSharedSize*8/256/Cfg.iCacheNumWays ),
+    .SET_COUNT      ( Cfg.iCacheNumWays                            ),
+    .L1DataParityWidth ( 8 ),
+    .L0DataParityWidth ( 8 ),
+    .FetchAddrWidth ( AddrWidth                                    ),
+    .FetchDataWidth ( Cfg.iCachePrivateDataWidth                   ),
+    .AxiAddrWidth   ( AddrWidth                                    ),
+    .AxiDataWidth   ( Cfg.AxiDataOutWidth                          ),
+    .axi_req_t      ( instr_axi_req_t                              ),
+    .axi_rsp_t      ( instr_axi_resp_t                             )
+  ) icache_top_i (
+    .clk_i                ( clk_i                       ),
+    .rst_ni               ( rst_ni                      ),
+
+    .fetch_req_i          ( instr_req                   ),
+    .fetch_addr_i         ( instr_addr                  ),
+    .fetch_gnt_o          ( instr_gnt                   ),
+    .fetch_rvalid_o       ( instr_r_valid               ),
+    .fetch_rdata_o        ( instr_r_rdata               ),
+    .fetch_rerror_o       (),
+
+    .enable_prefetching_i ( s_enable_l1_l15_prefetch[0] ),
+    .icache_l0_events_o   ( s_icache_l0_events ),
+    .icache_l1_events_o   ( s_icache_l1_events ),
+    .flush_valid_i        ( s_icache_flush_valid ),
+    .flush_ready_o        ( s_icache_flush_ready ),
+
+    .sram_cfg_data_i      ('0),
+    .sram_cfg_tag_i       ('0),
+
+    .axi_req_o            ( s_core_instr_bus_req  ),
+    .axi_rsp_i            ( s_core_instr_bus_resp )
+  );
+
+  for (genvar i = 0; i < Cfg.NumCores; i++) begin
+    assign IC_ctrl_unit_bus_pri[i].bypass_ack     = '0;
+    assign IC_ctrl_unit_bus_pri[i].flush_ack      = '0;
+    assign IC_ctrl_unit_bus_pri[i].sel_flush_ack  = '0;
+    `ifdef FEATURE_ICACHE_STAT
+      assign IC_ctrl_unit_bus_pri[i].ctrl_hit_count   = '0;
+      assign IC_ctrl_unit_bus_pri[i].ctrl_trans_count = '0;
+      assign IC_ctrl_unit_bus_pri[i].ctrl_miss_count  = '0;
+      assign IC_ctrl_unit_bus_pri[i].ctrl_cong_count  = '0;
+    `endif
+  end
+
+  for (genvar i = 0; i < Cfg.iCacheNumBanks; i++) begin
+    assign IC_ctrl_unit_bus_main[i].ctrl_flush_ack     = '0;
+    assign IC_ctrl_unit_bus_main[i].ctrl_ack_enable    = '0;
+    assign IC_ctrl_unit_bus_main[i].ctrl_ack_disable   = '0;
+    assign IC_ctrl_unit_bus_main[i].ctrl_pending_trans = '0;
+    assign IC_ctrl_unit_bus_main[i].sel_flush_ack      = '0;
+    `ifdef FEATURE_ICACHE_STAT
+      assign IC_ctrl_unit_bus_main[i].ctrl_hit_count   = '0;
+      assign IC_ctrl_unit_bus_main[i].ctrl_trans_count = '0;
+      assign IC_ctrl_unit_bus_main[i].ctrl_miss_count  = '0;
+    `endif
+  end
+`else
 `ifdef PRIVATE_ICACHE
 
   icache_hier_top #(
@@ -1391,9 +1466,10 @@ module pulp_cluster
     .IC_ctrl_unit_slave_if  ( IC_ctrl_unit_bus        ),
     .L0_ctrl_unit_slave_if  ( L0_ctrl_unit_bus        )
   );
-  `endif // Closes `ifdef SP_ICACHE
- `endif // Closes `ifdef MP_ICACHE
-`endif // Closes `ifdef PRI_ICACHE
+   `endif // Closes `ifdef SP_ICACHE
+  `endif // Closes `ifdef MP_ICACHE
+ `endif // Closes `ifdef PRI_ICACHE
+`endif // Closes `ifdef SNITCH_ICACHE