From 9140d8da6418b414b1029557278184b51ffcb54b Mon Sep 17 00:00:00 2001 From: jbleclere Date: Wed, 31 Mar 2021 17:04:41 +0000 Subject: [PATCH] Debug --- tests/test_awsf1_refdesign.py | 142 ++++++++++++++++++++++++++++++++++ tests/test_vitis_refdesign.py | 5 +- 2 files changed, 143 insertions(+), 4 deletions(-) create mode 100644 tests/test_awsf1_refdesign.py diff --git a/tests/test_awsf1_refdesign.py b/tests/test_awsf1_refdesign.py new file mode 100644 index 00000000..974d8783 --- /dev/null +++ b/tests/test_awsf1_refdesign.py @@ -0,0 +1,142 @@ +# -*- coding: utf-8 -*- +""" +Test all other vitis reference designs +""" +import pytest +from datetime import datetime +from os.path import join, dirname, realpath +from random import choices +from re import search, IGNORECASE + +import tests.conftest as conftest + + +def run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, + log_file_factory, axiclk_freq_ref, drmclk_freq_ref): + + # Program board with design + ref_designs = accelize_drm.pytest_ref_designs + try: + fpga_image = ref_designs.get_image_id(design_name) + except: + pytest.skip(f"Could not find refesign name '{design_name}' for driver '{accelize_drm.pytest_fpga_driver_name}'") + driver = accelize_drm.pytest_fpga_driver[0] + driver.program_fpga(fpga_image) + accelize_drm.scanActivators() + + # Run test + async_cb = async_handler.create() + async_cb.reset() + activators = accelize_drm.pytest_fpga_activators[0] + activators.reset_coin() + activators.autotest() + logfile = log_file_factory.create(1) + conf_json['settings'].update(logfile.json) + conf_json['drm']['frequency_mhz'] = drmclk_freq_ref + conf_json.save() + with accelize_drm.DrmManager( + conf_json.path, + cred_json.path, + driver.read_register_callback, + driver.write_register_callback, + async_cb.callback + ) as drm_manager: + assert not drm_manager.get('session_status') + assert not drm_manager.get('license_status') + assert drm_manager.get('session_id') == '' + activators.autotest(is_activated=False) + activators.generate_coin(5) + activators.check_coin() + # Start session + drm_manager.activate() + start = datetime.now() + assert sum(drm_manager.get('metered_data')) == 0 + assert drm_manager.get('session_status') + assert drm_manager.get('license_status') + session_id = drm_manager.get('session_id') + assert len(session_id) > 0 + activators.autotest(is_activated=True) + lic_duration = drm_manager.get('license_duration') + activators.generate_coin() + activators.check_coin(drm_manager.get('metered_data')) + # Wait until 2 licenses are provisioned + conftest.wait_func_true(lambda: drm_manager.get('num_license_loaded') == 2, lic_duration) + # Pause session + drm_manager.deactivate(True) + assert drm_manager.get('session_status') + assert drm_manager.get('license_status') + assert drm_manager.get('session_id') == session_id + activators.autotest(is_activated=True) + # Wait right before license expiration + conftest.wait_deadline(start, 2*lic_duration-3) + assert drm_manager.get('session_status') + assert drm_manager.get('license_status') + assert drm_manager.get('session_id') == session_id + activators.autotest(is_activated=True) + # Wait expiration + conftest.wait_deadline(start, 2*lic_duration+2) + assert drm_manager.get('session_status') + assert drm_manager.get('session_id') == session_id + assert not drm_manager.get('license_status') + activators.autotest(is_activated=False) + activators.generate_coin() + activators.check_coin(drm_manager.get('metered_data')) + # Resume session + drm_manager.activate(True) + assert drm_manager.get('session_status') + assert drm_manager.get('session_id') != session_id + assert drm_manager.get('license_status') + activators.reset_coin() + activators.autotest(is_activated=True) + activators.generate_coin() + activators.check_coin(drm_manager.get('metered_data')) + # Stop session + drm_manager.deactivate() + assert not drm_manager.get('session_status') + assert not drm_manager.get('license_status') + activators.autotest(is_activated=False) + assert drm_manager.get('session_id') == '' + # Check result + log_content = logfile.read() + # Check API calls + assert search(r"Calling Impl public constructor", log_content, IGNORECASE) + assert search(r"Calling 'activate' with 'resume_session_request'=false", log_content, IGNORECASE) + assert search(r"Calling 'deactivate' with 'pause_session_request'=true", log_content, IGNORECASE) + assert search(r"Calling 'activate' with 'resume_session_request'=true", log_content, IGNORECASE) + assert search(r"Calling 'deactivate' with 'pause_session_request'=false", log_content, IGNORECASE) + # Check DRM Controller frequencies + drmclk_match = search(r'Frequency detection of drm_aclk counter after .+ => estimated frequency = (\d+) MHz', log_content) + drmclk_freq_measure = int(drmclk_match.group(1)) + assert drmclk_freq_ref*0.9 < drmclk_freq_measure < drmclk_freq_ref*1.1 + axiclk_match = search(r'Frequency detection of s_axi_aclk counter after .+ => estimated frequency = (\d+) MHz', log_content) + axiclk_freq_measure = int(axiclk_match.group(1)) + assert axiclk_freq_ref*0.9 < axiclk_freq_measure < axiclk_freq_ref*1.1 + # Return logfile handler for more specific verification + logfile.remove() + return log_content + + +@pytest.mark.awsf1 +def test_2activator_axi4_2clk(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): + """ + Test a vivado configuration: dual clock kernels + """ + # Run test + design_name = '2activator_axi4_2clk' + axiclk_freq_ref = 250 + drmclk_freq_ref = 125 + log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, + log_file_factory, axiclk_freq_ref, drmclk_freq_ref) + + +@pytest.mark.awsf1 +def test_2activator_axi4_swap_activator(accelize_drm, conf_json, cred_json, async_handler, log_file_factory): + """ + Test a vivado configuration: dual clock kernels with activators inverted on LGDN bus + """ + # Run test + design_name = '2activator_axi4_swap_activator' + axiclk_freq_ref = 250 + drmclk_freq_ref = 125 + log_content = run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, + log_file_factory, axiclk_freq_ref, drmclk_freq_ref) diff --git a/tests/test_vitis_refdesign.py b/tests/test_vitis_refdesign.py index 4f3fa871..d8b5f188 100644 --- a/tests/test_vitis_refdesign.py +++ b/tests/test_vitis_refdesign.py @@ -11,9 +11,6 @@ import tests.conftest as conftest -SCRIPT_DIR = dirname(realpath(__file__)) - - def run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_handler, log_file_factory, axiclk_freq_ref, drmclk_freq_ref): @@ -22,7 +19,7 @@ def run_test_on_design(accelize_drm, design_name, conf_json, cred_json, async_ha try: fpga_image = ref_designs.get_image_id(design_name) except: - pytest.skip(f"Could not find refesign name '{design_name}' for driver '{DRIVER_NAME}'") + pytest.skip(f"Could not find refesign name '{design_name}' for driver '{accelize_drm.pytest_fpga_driver_name}'") driver = accelize_drm.pytest_fpga_driver[0] driver.program_fpga(fpga_image) accelize_drm.scanActivators()