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language.py
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language.py
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# Copyright 2014-2015 The Alive authors.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import collections
from constants import *
from codegen import *
def getAllocSize(type):
# round to nearest byte boundary
return int((type.getSize() + 7) / 8) * 8
def alignSize(size, align):
if align == 0:
return size
assert align & (align-1) == 0
return (size + (align-1)) & ~(align-1)
def getPtrAlignCnstr(ptr, align):
if align == 0:
return BoolVal(True)
assert align & (align-1) == 0
return ptr & (align-1) == 0
def defined_align_access(state, defined, access_size, req_align, aptr):
defined.append(aptr != 0)
must_access = []
for blck in state.ptrs:
ptr = blck.ptr
size = blck.size()
inbounds = And(UGE(aptr, ptr), UGE((size - access_size)/8, aptr - ptr))
if req_align != 0 and size >= access_size:
# overestimating the alignment is undefined behavior.
defined.append(Implies(inbounds, blck.align >= req_align))
if access_size <= size:
must_access.append(inbounds if blck.isAlloca() else BoolVal(True))
defined.append(mk_or(must_access))
# load/store are cutpoints; record BB definedness
state.defined += defined
################################
class MemInfo:
def __init__(self, ptr, ty, block_size, num_elems, align):
self.ptr = ptr
self.ty = ty
self.block_size = block_size
self.num_elems = num_elems
self.align = align
def isAlloca(self):
return self.ty == 'alloca'
def size(self):
return self.block_size * self.num_elems
def __eq__(self, b):
return self.ptr.eq(b.ptr)
class State:
def __init__(self):
self.vars = collections.OrderedDict()
self.defined = [] # definedness so far in the BB
self.ptrs = []
self.mem_qvars = []
self.bb_pres = {}
self.bb_mem = {}
def add(self, v, smt, defined, poison, qvars):
if v.getUniqueName() == '':
return
# could probably update qvars in the function but....
fastMathInfo = v.getFastConds(smt)
finalSMT = fastMathInfo[0]
new_qvars = fastMathInfo[1]
# print finalSMT
# print
# Update the formulas with the new fast math information
qvars += new_qvars
# Adds a function to the vars that defines a relaxation for the nsz fast math flag
self.vars[v.getUniqueName()] = (finalSMT, self.defined + defined, poison, qvars, \
lambda a,b: getRelaxationCond(v,a,b))
if isinstance(v, TerminatorInst):
for (bb,cond) in v.getSuccessors(self):
bb = bb[1:]
if bb not in self.bb_pres:
self.bb_pres[bb] = []
self.bb_mem[bb] = []
self.bb_pres[bb] += [cond]
self.bb_mem[bb].append((cond, self.mem))
def addAlloca(self, ptr, mem, block_size, num_elems, align):
self.mem_qvars.append(mem)
self.ptrs.append(MemInfo(ptr, 'alloca', block_size, num_elems, align))
def addInputMem(self, ptr, qvars, block_size, num_elems):
# precondition vcgen can call this function spuriously
if any(ptr.eq(blck.ptr) for blck in self.ptrs):
return
self.mem_qvars += qvars
self.ptrs.append(MemInfo(ptr, 'in', block_size, num_elems, 1))
def store(self, cnstr, idx, val):
if use_array_theory():
self.mem = mk_if(mk_and(cnstr), Update(self.mem, idx, val), self.mem)
else:
self.mem = If(mk_and(cnstr + [self.idx_var == idx]), val, self.mem)
def load(self, idx):
if use_array_theory():
return self.mem[idx]
return substitute(self.mem, (self.idx_var, idx))
def newBB(self, name):
if name in self.bb_pres:
self.defined = [mk_or(self.bb_pres[name])]
self.mem = fold_ite_list(self.bb_mem[name])
else:
self.defined = []
if use_array_theory():
self.mem = Array('mem0', BitVecSort(get_ptr_size()), BitVecSort(8))
else:
self.mem = BitVec('mem0', 8)
self.idx_var = BitVec('idx', get_ptr_size())
self.current_bb = name
def getAllocaConstraints(self):
# generate the following constraints:
# 1) Alloca ptrs are never null
# 2) Allocated regions do not overlap with each other and with input blocks
cnstr = []
for mem1 in self.ptrs:
if mem1.ty == 'in':
continue
ptr = mem1.ptr
size = mem1.size()
cnstr.append(ptr != 0)
for mem2 in self.ptrs:
if mem1 == mem2:
continue
cnstr.append(Or(UGE(mem2.ptr, ptr + size),
ULE(mem2.ptr + mem2.size(), ptr)))
return cnstr
def eval(self, v, defined, poison, qvars):
(smt, d, p, q, _) = self.vars[v.getUniqueName()]
defined += d
poison += p
qvars += q
return smt
def iteritems(self):
for k,v in self.vars.iteritems():
if k[0] != '%' and k[0] != 'C' and not k.startswith('ret_'):
continue
yield k,v
def has_key(self, k):
return self.vars.has_key(k)
def __getitem__(self, k):
return self.vars[k]
def add_other_vars(self, other_state):
for v, (smt, defined, poison, qvars, _) in other_state.vars.iteritems():
if v[0] != '%' and v[0] != 'C' and not v.startswith('ret_'):
self.vars[v] = (smt, defined, poison, qvars, lambda a,b: False)
################################
class Instr(Value):
pass
################################
class CopyOperand(Instr):
def __init__(self, v, type):
self.v = v
self.type = type
assert isinstance(self.v, Value)
assert isinstance(self.type, Type)
def __repr__(self):
t = str(self.type)
if len(t) > 0:
t += ' '
return t + self.v.getName()
def toSMT(self, defined, poison, state, qvars):
return state.eval(self.v, defined, poison, qvars)
def getTypeConstraints(self):
return And(self.type == self.v.type,
self.type.getTypeConstraints())
def register_types(self, manager):
manager.register_type(self, self.type, UnknownType())
manager.unify(self, self.v)
# TODO: visit_source?
def visit_target(self, manager, use_builder=False):
instr = manager.get_cexp(self.v)
if use_builder:
isntr = CVariable('Builder').arr('Insert', [instr])
# TODO: this probably should use manager.get_ctype,
# but that currently doesn't distinguish source instructions (Value)
# from target instructions (Instruction)
if isinstance(self.v, Instr):
ctype = manager.PtrInstruction
else:
ctype = manager.PtrValue
return [CDefinition.init(
ctype,
manager.get_cexp(self),
instr)]
################################
class BinOp(Instr):
Add, Sub, Mul, UDiv, SDiv, URem, SRem, Shl, AShr, LShr, And, Or, Xor, FAdd,\
FSub, FMul, FDiv, FRem, Last = range(19)
opnames = {
Add: 'add',
Sub: 'sub',
Mul: 'mul',
UDiv: 'udiv',
SDiv: 'sdiv',
URem: 'urem',
SRem: 'srem',
Shl: 'shl',
AShr: 'ashr',
LShr: 'lshr',
And: 'and',
Or: 'or',
Xor: 'xor',
FAdd: 'fadd',
FSub: 'fsub',
FMul: 'fmul',
FDiv: 'fdiv',
FRem: 'frem',
}
opids = {v:k for k, v in opnames.items()}
def __init__(self, op, type, v1, v2, flags = []):
assert isinstance(type, Type)
assert isinstance(v1, Value)
assert isinstance(v2, Value)
assert 0 <= op < self.Last
self.op = op
self.type = type
self.v1 = v1
self.v2 = v2
self.flags = list(flags)
self._check_op_flags()
self.v1_smt = None
self.v2_smt = None
def getFastConds(self, expr):
undefNames = []
ctr = [0]
def getNewUndefName():
newVar = FP(self.getUniqueName() + "undef" + str(ctr[0]),
self.type.sortOfFloat())
undefNames.append(newVar)
ctr[0] += 1
return newVar
if 'nnan' in self.flags:
expr = If(Or(fpIsNaN(self.v1_smt), fpIsNaN(self.v2_smt), fpIsNaN(expr)),
getNewUndefName(), expr)
if 'ninf' in self.flags:
expr = If(Or(fpIsInf(self.v1_smt), fpIsInf(self.v2_smt), fpIsInf(expr)),
getNewUndefName(), expr)
return (expr, undefNames)
def getOpName(self):
return self.opnames[self.op]
def fpFmod(self, x, y):
abs_y = fpAbs(y)
result = fpRem(fpAbs(x), abs_y)
result = If(fpIsNegative(result), result + abs_y, result)
return If(Xor(fpIsNegative(x), fpIsNegative(result)), fpNeg(result), result)
@staticmethod
def getOpId(name):
try:
return BinOp.opids[name]
except:
raise ParseError('Unknown binary instruction')
@staticmethod
def isFloatOp(op):
return op in [BinOp.FAdd, BinOp.FSub, BinOp.FMul, BinOp.FDiv, BinOp.FRem]
def __repr__(self):
t = str(self.type)
if len(t) > 0:
t = ' ' + t
flags = ' '.join(self.flags)
if len(flags) > 0:
flags = ' ' + flags
return '%s%s%s %s, %s' % (self.getOpName(), flags, t,
self.v1.getName(),
self.v2.getName())
def _check_op_flags(self):
allowed_flags = {
self.Add: ['nsw', 'nuw'],
self.Sub: ['nsw', 'nuw'],
self.Mul: ['nsw', 'nuw'],
self.UDiv: ['exact'],
self.SDiv: ['exact'],
self.URem: [],
self.SRem: [],
self.Shl: ['nsw', 'nuw'],
self.AShr: ['exact'],
self.LShr: ['exact'],
self.And: [],
self.Or: [],
self.Xor: [],
# remaining:
# arcp (reciprocal allowed)
# fast (algebraically equivalent allowed)
self.FAdd: ['nnan', 'ninf', 'nsz'],
self.FSub: ['nnan', 'ninf', 'nsz'],
self.FMul: ['nnan', 'ninf', 'nsz'],
self.FDiv: ['nnan', 'ninf', 'nsz'],
self.FRem: ['nnan', 'ninf', 'nsz'],
}[self.op]
for f in self.flags:
if f not in allowed_flags:
raise ParseError('Flag not supported by ' + self.getOpName(), f)
def _genSMTDefConds(self, v1, v2, poison):
bits = self.type.getSize()
poison_conds = {
self.Add: {'nsw': lambda a,b: SignExt(1,a)+SignExt(1,b) == SignExt(1,a+b),
'nuw': lambda a,b: ZeroExt(1,a)+ZeroExt(1,b) == ZeroExt(1,a+b),
},
self.Sub: {'nsw': lambda a,b: SignExt(1,a)-SignExt(1,b) == SignExt(1,a-b),
'nuw': lambda a,b: ZeroExt(1,a)-ZeroExt(1,b) == ZeroExt(1,a-b),
},
self.Mul: {'nsw': lambda a,b: no_overflow_smul(a, b),
'nuw': lambda a,b: no_overflow_umul(a, b),
},
self.UDiv:{'exact': lambda a,b: UDiv(a, b) * b == a,
},
self.SDiv:{'exact': lambda a,b: (a / b) * b == a,
},
self.URem:{},
self.SRem:{},
self.Shl: {'nsw': lambda a,b: Or((a << b) >> b == a,
And(a == 1, b == (bits-1)))
if use_new_semantics()
else (a << b) >> b == a,
'nuw': lambda a,b: LShR(a << b, b) == a,
},
self.AShr:{'exact': lambda a,b: (a >> b) << b == a,
},
self.LShr:{'exact': lambda a,b: LShR(a, b) << b == a,
},
self.And: {},
self.Or: {},
self.Xor: {},
# Do not need for nnan ninf nsz
self.FAdd:{},
self.FSub:{},
self.FMul:{},
self.FDiv:{},
self.FRem:{},
}[self.op]
if do_infer_flags():
for flag,fn in poison_conds.iteritems():
bit = get_flag_var(flag, self.getName())
poison += [Implies(bit == 1, fn(v1, v2))]
else:
for f in self.flags:
# these flags are not poison
if f == 'nsz' or f == 'nnan' or f == 'ninf': continue
poison += [poison_conds[f](v1, v2)]
# definedness of the instruction
return {
self.Add: lambda a,b: [],
self.Sub: lambda a,b: [],
self.Mul: lambda a,b: [],
self.UDiv: lambda a,b: [b != 0],
self.SDiv: lambda a,b: [b != 0, Or(a != (1 << (bits-1)), b != -1)],
self.URem: lambda a,b: [b != 0],
self.SRem: lambda a,b: [b != 0, Or(a != (1 << (bits-1)), b != -1)],
self.Shl: lambda a,b: [ULT(b, bits)],
self.AShr: lambda a,b: [ULT(b, bits)],
self.LShr: lambda a,b: [ULT(b, bits)],
self.And: lambda a,b: [],
self.Or: lambda a,b: [],
self.Xor: lambda a,b: [],
# Nothing, the instruction is defined no matter what
self.FAdd: lambda a,b: [],
self.FSub: lambda a,b: [],
self.FMul: lambda a,b: [],
self.FDiv: lambda a,b: [],
self.FRem: lambda a,b: [],
}[self.op](v1,v2)
def toSMT(self, defined, poison, state, qvars):
v1 = state.eval(self.v1, defined, poison, qvars)
v2 = state.eval(self.v2, defined, poison, qvars)
self.v1_smt = v1
self.v2_smt = v2
defined += self._genSMTDefConds(v1, v2, poison)
return {
self.Add: lambda a,b: a + b,
self.Sub: lambda a,b: a - b,
self.Mul: lambda a,b: a * b,
self.UDiv: lambda a,b: UDiv(a, b),
self.SDiv: lambda a,b: a / b,
self.URem: lambda a,b: URem(a, b),
self.SRem: lambda a,b: SRem(a, b),
self.Shl: lambda a,b: a << b,
self.AShr: lambda a,b: a >> b,
self.LShr: lambda a,b: LShR(a, b),
self.And: lambda a,b: a & b,
self.Or: lambda a,b: a | b,
self.Xor: lambda a,b: a ^ b,
self.FAdd: lambda a,b: fpAdd(RNE(), a, b),
self.FSub: lambda a,b: fpNeg(b) if isinstance(a, FPNumRef) and a.isZero() and a.isNegative() else fpSub(RNE(), a, b),
self.FMul: lambda a,b: fpMul(RNE(), a, b),
self.FDiv: lambda a,b: fpDiv(RNE(), a, b),
self.FRem: lambda a,b: self.fpFmod(a, b),
}[self.op](v1, v2)
# Relaxation for nsz flag
def getRelaxationCond(self, tgt, src):
cond = []
if 'nsz' in self.flags: cond = cond + [Or(fpIsZero(src), fpIsZero(tgt))]
return mk_or(cond)
def getTypeConstraints(self):
return And(self.type == self.v1.type,
self.type == self.v2.type,
self.type.getTypeConstraints())
caps = {
Add: 'Add',
Sub: 'Sub',
Mul: 'Mul',
UDiv: 'UDiv',
SDiv: 'SDiv',
URem: 'URem',
SRem: 'SRem',
Shl: 'Shl',
AShr: 'AShr',
LShr: 'LShr',
And: 'And',
Or: 'Or',
Xor: 'Xor',
FAdd: 'FAdd',
FSub: 'FSub',
FMul: 'FMul',
FDiv: 'FDiv',
FRem: 'FRem',
}
def register_types(self, manager):
t = FloatType() if BinOp.isFloatOp(self.op) else IntType()
manager.register_type(self, self.type, t)
manager.unify(self, self.v1, self.v2)
def visit_source(self, mb):
r1 = mb.subpattern(self.v1)
r2 = mb.subpattern(self.v2)
op = BinOp.caps[self.op]
if 'nsw' in self.flags and 'nuw' in self.flags:
return CFunctionCall('match',
mb.get_my_ref(),
CFunctionCall('m_CombineAnd',
CFunctionCall('m_NSW' + op, r1, r2),
CFunctionCall('m_NUW' + op,
CFunctionCall('m_Value'),
CFunctionCall('m_Value'))))
if 'nsw' in self.flags:
return mb.simple_match('m_NSW' + op, r1, r2)
if 'nuw' in self.flags:
return mb.simple_match('m_NUW' + op, r1, r2)
if 'exact' in self.flags:
return CFunctionCall('match',
mb.get_my_ref(),
CFunctionCall('m_Exact', CFunctionCall('m_' + op, r1, r2)))
return mb.simple_match('m_' + op, r1, r2)
def visit_target(self, manager, use_builder=False):
cons = CFunctionCall('BinaryOperator::Create' + self.caps[self.op],
manager.get_cexp(self.v1), manager.get_cexp(self.v2))
if use_builder:
cons = CVariable('Builder').arr('Insert', [cons])
gen = [CDefinition.init(CPtrType(CTypeName('BinaryOperator')), manager.get_cexp(self), cons)]
for f in self.flags:
setter = {'nsw': 'setHasNoSignedWrap', 'nuw': 'setHasNoUnsignedWrap', 'exact': 'setIsExact'}[f]
gen.append(manager.get_cexp(self).arr(setter, [CVariable('true')]))
return gen
################################
class ConversionOp(Instr):
# TODO: fabs is not really a conversion op
Trunc, ZExt, SExt, ZExtOrTrunc, Ptr2Int, Int2Ptr, Bitcast, FPTrunc, FPExt, FPToUI, FPToSI, UIToFP, SIToFP, FAbs, Last = range(15)
opnames = {
Trunc: 'trunc',
ZExt: 'zext',
SExt: 'sext',
ZExtOrTrunc: 'ZExtOrTrunc',
Ptr2Int: 'ptrtoint',
Int2Ptr: 'inttoptr',
Bitcast: 'bitcast',
FPTrunc: 'fptrunc',
FPExt: 'fpext',
FPToUI: 'fptoui',
FPToSI: 'fptosi',
UIToFP: 'uitofp',
SIToFP: 'sitofp',
FAbs: 'fabs',
}
opids = {v:k for k, v in opnames.items()}
def __init__(self, op, stype, v, type):
assert isinstance(stype, Type)
assert isinstance(type, Type)
assert isinstance(v, Value)
assert 0 <= op < self.Last
self.op = op
self.stype = stype
self.v = v
self.type = type
def getOpName(self):
return self.opnames[self.op]
@staticmethod
def getOpId(name):
try:
return ConversionOp.opids[name]
except:
raise ParseError('Unknown conversion instruction')
@staticmethod
def enforceIntSrc(op):
return op in [
ConversionOp.Trunc,
ConversionOp.ZExt,
ConversionOp.SExt,
ConversionOp.ZExtOrTrunc,
ConversionOp.Int2Ptr,
ConversionOp.SIToFP,
ConversionOp.UIToFP ]
@staticmethod
def enforcePtrSrc(op):
return op == ConversionOp.Ptr2Int
@staticmethod
def enforceFloatSrc(op):
return op in [
ConversionOp.FPTrunc,
ConversionOp.FPExt,
ConversionOp.FPToSI,
ConversionOp.FPToUI,
ConversionOp.FAbs ]
@staticmethod
def enforceIntTgt(op):
return op in [
ConversionOp.Trunc,
ConversionOp.ZExt,
ConversionOp.SExt,
ConversionOp.ZExtOrTrunc,
ConversionOp.Ptr2Int,
ConversionOp.FPToSI,
ConversionOp.FPToUI ]
@staticmethod
def enforcePtrTgt(op):
return op == ConversionOp.Int2Ptr
@staticmethod
def enforceFloatTgt(op):
return op in [
ConversionOp.FPTrunc,
ConversionOp.FPExt,
ConversionOp.SIToFP,
ConversionOp.UIToFP,
ConversionOp.FAbs ]
def __repr__(self):
st = str(self.stype)
if len(st) > 0:
st = ' ' + st
tt = str(self.type)
if len(tt) > 0:
tt = ' to ' + tt
return '%s%s %s%s' % (self.getOpName(), st, self.v.getName(), tt)
def toSMT(self, defined, poison, state, qvars):
size = self.type.getSize()
def make_to_int(fp_v, min_v, max_v, conv_f, size, qvars):
min_v = fpToFP(RNE(), min_v, fp_v.sort())
max_v = fpToFPUnsigned(RNE(), max_v, fp_v.sort())
undef = freshBV('to_int', size)
qvars += [undef]
return If(Or(fpIsNaN(fp_v), fpIsInf(fp_v), fp_v > max_v, fp_v < min_v), undef, conv_f(RNE(), fp_v, BitVecSort(size)))
def make_to_float(bv_v, conv_f, size, qvars):
sort = FloatType(size).sortOfFloat()
fp_v = conv_f(RNE(), bv_v, sort)
undef = freshFP('to_float', sort)
qvars += [undef]
return If(fpIsInf(fp_v), undef, fp_v)
return {
self.Trunc: lambda v: Extract(size-1, 0, v),
self.ZExt: lambda v: ZeroExt(size -
self.stype.getSize(), v),
self.SExt: lambda v: SignExt(size -
self.stype.getSize(), v),
self.ZExtOrTrunc: lambda v: truncateOrZExt(v, size),
self.Ptr2Int: lambda v: truncateOrZExt(v, size),
self.Int2Ptr: lambda v: truncateOrZExt(v, size),
self.Bitcast: lambda v: v,
self.FPTrunc: lambda v: fpToFP(RNE(), v, FloatType(size).sortOfFloat()),
self.FPExt: lambda v: fpToFP(RNE(), v, FloatType(size).sortOfFloat()),
self.FPToUI: lambda v: make_to_int(v, unsigned_min_val(size), unsigned_max_val(size), fpToUBV, size, qvars),
self.FPToSI: lambda v: make_to_int(v, signed_min_val(size), signed_max_val(size), fpToSBV, size, qvars),
self.UIToFP: lambda v: make_to_float(v, fpToFPUnsigned, size, qvars),
self.SIToFP: lambda v: make_to_float(v, fpToFP, size, qvars),
self.FAbs: lambda v: fpAbs(v),
}[self.op](state.eval(self.v, defined, poison, qvars))
def getTypeConstraints(self):
cnstr = {
self.Trunc: lambda src,tgt: src > tgt,
self.ZExt: lambda src,tgt: src < tgt,
self.SExt: lambda src,tgt: src < tgt,
self.ZExtOrTrunc: lambda src,tgt: BoolVal(True),
self.Ptr2Int: lambda src,tgt: BoolVal(True),
self.Int2Ptr: lambda src,tgt: BoolVal(True),
self.Bitcast: lambda src,tgt: src.getSize() == tgt.getSize(),
self.FPTrunc: lambda src,tgt: src > tgt,
self.FPExt: lambda src,tgt: src < tgt,
self.FPToUI: lambda src,tgt: BoolVal(True),
self.FPToSI: lambda src,tgt: BoolVal(True),
self.UIToFP: lambda src,tgt: BoolVal(True),
self.SIToFP: lambda src,tgt: BoolVal(True),
self.FAbs: lambda src,tgt: src.getSize() == tgt.getSize(),
} [self.op](self.stype, self.type)
return And(self.stype == self.v.type,
self.type.getTypeConstraints(),
self.stype.getTypeConstraints(),
cnstr)
matcher = {
Trunc: 'm_Trunc',
ZExt: 'm_ZExt',
SExt: 'm_SExt',
Ptr2Int: 'm_PtrToInt',
Bitcast: 'm_BitCast',
}
constr = {
Trunc: 'TruncInst',
ZExt: 'ZExtInst',
SExt: 'SExtInst',
Ptr2Int: 'PtrToIntInst',
Int2Ptr: 'IntToPtrInst',
Bitcast: 'BitCastInst',
}
def register_types(self, manager):
if self.enforceIntSrc(self.op):
manager.register_type(self.v, self.stype, IntType())
elif self.enforcePtrSrc(self.op):
manager.register_type(self.v, self.stype, PtrType())
elif self.enforceFloatSrc(self.op):
manager.register_type(self.v, self.stype, FloatType())
else:
manager.register_type(self.v, self.stype, UnknownType())
if self.enforceIntTgt(self.op):
manager.register_type(self, self.type, IntType())
elif self.enforcePtrTgt(self.op):
manager.register_type(self, self.type, PtrType())
elif self.enforceFloatTgt(self.op):
manager.register_type(self, self.type, FloatType())
else:
manager.register_type(self, self.type, UnknownType())
# TODO: inequalities for trunc/sext/zext
def visit_source(self, mb):
r = mb.subpattern(self.v)
if self.op == ConversionOp.ZExtOrTrunc:
return CFunctionCall('match',
mb.get_my_ref(),
CFunctionCall('m_CombineOr',
CFunctionCall('m_ZExt', r),
CFunctionCall('m_ZTrunc', r)))
return mb.simple_match(ConversionOp.matcher[self.op], r)
def visit_target(self, manager, use_builder=False):
if self.op == ConversionOp.ZExtOrTrunc:
assert use_builder #TODO: handle ZExtOrTrunk in root position
instr = CVariable('Builder').arr('CreateZExtOrTrunc',
[manager.get_cexp(self.v), manager.get_llvm_type(self)])
return [CDefinition.init(
manager.PtrValue,
manager.get_cexp(self),
instr)]
else:
instr = CFunctionCall('new ' + ConversionOp.constr[self.op],
manager.get_cexp(self.v), manager.get_llvm_type(self))
if use_builder:
instr = CVariable('Builder').arr('Insert', [instr])
return [CDefinition.init(
manager.PtrInstruction,
manager.get_cexp(self),
instr)]
################################
class Icmp(Instr):
EQ, NE, UGT, UGE, ULT, ULE, SGT, SGE, SLT, SLE, Var, Last = range(12)
opnames = {
EQ: 'eq',
NE: 'ne',
UGT: 'ugt',
UGE: 'uge',
ULT: 'ult',
ULE: 'ule',
SGT: 'sgt',
SGE: 'sge',
SLT: 'slt',
SLE: 'sle',
}
opids = {v:k for k, v in opnames.items()}
def __init__(self, op, type, v1, v2):
assert isinstance(type, Type)
assert isinstance(v1, Value)
assert isinstance(v2, Value)
self.op = self.getOpId(op)
if self.op == self.Var:
self.opname = op
self.type = IntType(1)
self.stype = type.ensureIntPtrOrVector()
self.v1 = v1
self.v2 = v2
def getOpName(self):
return 'icmp'
@staticmethod
def getOpId(name):
return Icmp.opids.get(name, Icmp.Var)
def __repr__(self):
op = self.opname if self.op == Icmp.Var else Icmp.opnames[self.op]
if len(op) > 0:
op = ' ' + op
t = str(self.stype)
if len(t) > 0:
t = ' ' + t
return 'icmp%s%s %s, %s' % (op, t, self.v1.getName(), self.v2.getName())
def opToSMT(self, op, a, b):
return {
self.EQ: lambda a,b: toBV(a == b),
self.NE: lambda a,b: toBV(a != b),
self.UGT: lambda a,b: toBV(UGT(a, b)),
self.UGE: lambda a,b: toBV(UGE(a, b)),
self.ULT: lambda a,b: toBV(ULT(a, b)),
self.ULE: lambda a,b: toBV(ULE(a, b)),
self.SGT: lambda a,b: toBV(a > b),
self.SGE: lambda a,b: toBV(a >= b),
self.SLT: lambda a,b: toBV(a < b),
self.SLE: lambda a,b: toBV(a <= b),
}[op](a, b)
def recurseSMT(self, ops, a, b, i):
if len(ops) == 1:
return self.opToSMT(ops[0], a, b)
opname = self.opname if self.opname != '' else self.getName()
var = BitVec('icmp_' + opname, 4)
assert 1 << 4 > self.Var
return If(var == i,
self.opToSMT(ops[0], a, b),
self.recurseSMT(ops[1:], a, b, i+1))
def toSMT(self, defined, poison, state, qvars):
# Generate all possible comparisons if icmp is generic. Set of comparisons
# can be restricted in the precondition.
ops = [self.op] if self.op != self.Var else range(self.Var)
return self.recurseSMT(ops, state.eval(self.v1, defined, poison, qvars),
state.eval(self.v2, defined, poison, qvars), 0)
def getTypeConstraints(self):
return And(self.stype == self.v1.type,
self.stype == self.v2.type,
self.type.getTypeConstraints(),
self.stype.getTypeConstraints())
op_enum = {
EQ: 'ICmpInst::ICMP_EQ',
NE: 'ICmpInst::ICMP_NE',
UGT: 'ICmpInst::ICMP_UGT',
UGE: 'ICmpInst::ICMP_UGE',
ULT: 'ICmpInst::ICMP_ULT',
ULE: 'ICmpInst::ICMP_ULE',
SGT: 'ICmpInst::ICMP_SGT',
SGE: 'ICmpInst::ICMP_SGE',
SLT: 'ICmpInst::ICMP_SLT',
SLE: 'ICmpInst::ICMP_SLE',
}
def register_types(self, manager):
manager.register_type(self, self.type, IntType(1))
manager.register_type(self.v1, self.stype, UnknownType().ensureIntPtrOrVector())
manager.unify(self.v1, self.v2)
PredType = CTypeName('CmpInst::Predicate')
def visit_source(self, mb):
r1 = mb.subpattern(self.v1)
r2 = mb.subpattern(self.v2)
if self.op == Icmp.Var:
opname = self.opname if self.opname else 'Pred ' + self.name
name = mb.manager.get_key_name(opname) #FIXME: call via mb?
rp = mb.binding(name, self.PredType)
return mb.simple_match('m_ICmp', rp, r1, r2)
pvar = mb.new_name('P')
rp = mb.binding(pvar, self.PredType)
return CBinExpr('&&',
mb.simple_match('m_ICmp', rp, r1, r2),
CBinExpr('==', CVariable(pvar), CVariable(Icmp.op_enum[self.op])))
def visit_target(self, manager, use_builder=False):
# determine the predicate
if self.op == Icmp.Var:
key = self.opname if self.opname else 'Pred ' + self.name
opname = manager.get_key_name(key)
assert manager.bound(opname)
# TODO: confirm type
else:
opname = Icmp.op_enum[self.op]
instr = CFunctionCall('new ICmpInst', CVariable(opname),
manager.get_cexp(self.v1),
manager.get_cexp(self.v2))
if use_builder:
instr = CVariable('Builder').arr('Insert', [instr])
return [
CDefinition.init(manager.PtrInstruction, manager.get_cexp(self), instr)]
################################
class Fcmp(Instr):
FALSE, OEQ, OGT, OGE, OLT, OLE, ONE, ORD, UEQ, UGT, UGE, ULT, ULE, UNE, UNO, TRUE, Var, \
Last = range(18)
opnames = {
FALSE: 'false',
OEQ: 'oeq',
OGT: 'ogt',
OGE: 'oge',
OLT: 'olt',
OLE: 'ole',
ONE: 'one',
ORD: 'ord',
UEQ: 'ueq',
UGT: 'ugt',
UGE: 'uge',
ULT: 'ult',
ULE: 'ule',
UNE: 'une',
UNO: 'uno',
TRUE: 'true',
}
opids = {v:k for k, v in opnames.items()}
# Number of bits needed to represent the type of comparison.
# Useful for comparisons with variable predicates.
TYPE_BITS = 5
@staticmethod
def isUnorderedCmp(op):
return op >= Fcmp.UEQ
# TODO: Make isUnorderedCmp/isOrderedCmp one function
@staticmethod
def isOrderedCmp(op):
return And(op >= Fcmp.OEQ, op <= Fcmp.ORD)
@staticmethod
def swapCmp(op1, op2):
return And([Implies(Or([
op1 == Fcmp.FALSE,
op1 == Fcmp.TRUE,
op1 == Fcmp.OEQ,
op1 == Fcmp.ONE,
op1 == Fcmp.UEQ,
op1 == Fcmp.UNE,
op1 == Fcmp.ORD,
op1 == Fcmp.UNO]), op1 == op2),
Implies(op1 == Fcmp.OGT, op2 == Fcmp.OLT),
Implies(op1 == Fcmp.OLT, op2 == Fcmp.OGT),
Implies(op1 == Fcmp.OGE, op2 == Fcmp.OLE),
Implies(op1 == Fcmp.OLE, op2 == Fcmp.OGE),
Implies(op1 == Fcmp.UGT, op2 == Fcmp.ULT),
Implies(op1 == Fcmp.ULT, op2 == Fcmp.UGT),
Implies(op1 == Fcmp.UGE, op2 == Fcmp.ULE),
Implies(op1 == Fcmp.ULE, op2 == Fcmp.UGE),
op1 >= Fcmp.FALSE, op2 >= Fcmp.FALSE,
op1 <= Fcmp.TRUE, op2 <= Fcmp.TRUE])
def __init__(self, op, type, v1, v2):
assert isinstance(type, Type)
assert isinstance(v1, Value)
assert isinstance(v2, Value)
self.op = self.getOpId(op)
if self.op == self.Var:
self.opname = op
self.type = IntType(1)
self.stype = type.ensureFloatType()
self.v1 = v1
self.v2 = v2
def getOpName(self):
return 'fcmp'
@staticmethod
def getOpId(name):
return Fcmp.opids.get(name, Fcmp.Var)
def __repr__(self):
op = self.opname if self.op == Fcmp.Var else Fcmp.opnames[self.op]
if len(op) > 0:
op = ' ' + op
t = str(self.stype)
if len(t) > 0: